WM2616 [WOLFSON]
12-bit Serial Input Voltage Output DAC; 12位串行输入电压输出DAC
| 型号： | WM2616 |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | 12-bit Serial Input Voltage Output DAC |
| 文件： | 总9页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM2616
12-bit Serial Input Voltage Output DAC
Production Data June 1999, Rev1.0
FEATURES
DESCRIPTION
·
·
·
·
12-bit voltage output DAC
Single supply from 2.7V to 5.5V
DNL ±0.5 LSB, INL ±1.9 LSB
The WM2616 is a 12-bit voltage output, resistor string digital-to-
analogue converter that can be powered down under software
control. Power down reduces current consumption to 10nA.
Very low power consumption (3V supply):
The device has been designed to interface efficiently to industry
standard microprocessors and DSPs, including the TMS320
family. The WM2616 is programmed with a 16-bit serial word
comprising 4 control bits and 12 data bits.
-
-
900mW, slow mode
2.1mW, fast mode
·
TMS320, (Q)SPIä , and Microwireä compatible serial
interface
·
·
Programmable settling time of 4ms or 12ms typical
High impedance reference input buffer
Excellent performance is delivered with a typical DNL of 0.5LSBs.
The settling time of the DAC is programmable to allow the designer
to optimize speed versus power dissipation. The output stage is
buffered by a x2 gain rail-to-rail amplifier, which features a Class
AB output stage.
APPLICATIONS
·
·
·
·
·
·
·
Battery powered test instruments
Digital offset and gain adjustment
Battery operated/remote industrial controls
Machine and motion control devices
Wireless telephone and communication systems
Speech synthesis
The device is available in an 8-pin SOIC package. Commercial
temperature (0° to 70°C) and Industrial temperature (-40° to 85°C)
variants are supported.
Arbitrary waveform generation
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM2616CD
WM2616ID
0° to 70°C
8-pin SOIC
8-pin SOIC
-40° to 85°C
BLOCK DIAGRAM
TYPICAL PERFORMANCE
VDD
(8)
1
REFERENCE
INPUT BUFFER
AVDD = DVDD = 5V, VREF = 2.048V, Speed = Fast mode, Load = 10k/100pF
0.8
REFIN(6)
X1
DAC
OUTPUT
BUFFER
0.6
0.4
0.2
0
12-BIT
DAC
DIN (1)
data
(7) OUT
X2
LATCH
16-BIT
SHIFT
REGISTER
AND
SCLK (2)
CONTROL
LOGIC
NCS (3)
FS (4)
-0.2
-0.4
-0.6
-0.8
-1
POWERDOWN/
SPEED
CONTROL
2-BIT
CONTROL
LATCH
POWER-ON
RESET
WM2616
0
512
1024
1536
2048
2559
3071
3583
4095
DIGITAL CODE
(5)
AGND
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
Production Data Datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics’ Terms and conditions.
2616 master.doc June 17, 1999 14:13
http://www.wolfson.co.uk
Ó1999 Wolfson Microelectronics Ltd.
WM2616
Production Data Rev 1.0
PIN CONFIGURATION
VDD
DIN
SCLK
NCS
FS
1
2
3
4
8
7
6
5
OUT
REFIN
AGND
PIN DESCRIPTION
PIN NO
NAME
DIN
TYPE
Digital input
Digital input
Digital input
Digital input
Supply
DESCRIPTION
Serial data input.
Serial clock input.
1
2
3
4
5
6
7
8
SCLK
NCS
FS
Chip select. This pin is active low.
Frame synchronisation for serial input data.
Analogue ground.
AGND
REFIN
OUT
VDD
Analogue input
Analogue output
Supply
Voltage reference input.
DAC analogue output
Positive power supply.
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this
device.
CONDITION
MIN
MAX
7V
Supply voltage, VDD to AGND
Digital input voltage
-0.3V
-0.3V
VDD + 0.3V
VDD + 0.3V
Reference input voltage
Operating temperature range, TA
WM2616CD
WM2616ID
0°C
70°C
85°C
-40°C
Storage temperature
-65°C
150°C
260°C
Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage
VDD
2.7
5.5
V
High-level digital input voltage
Low-level digital input voltage
Reference voltage to REFIN
Load resistance
VIH
VIL
VDD = 2.7V to 5.5V
VDD = 2.7V to 5.5V
See Note
2
V
V
0.8
VREF
RL
VDD - 1.5
V
2
10
kW
pF
Load capacitance
CL
100
20
Serial clock rate
fSCLK
TA
MHz
Operating free-air temperature
WM2616CD
WM2616ID
0
70
85
°C
°C
-40
Note: Reference input voltages greater then VDD/2 will cause saturation for large DAC codes.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
2
Production Data Rev 1.0
WM2616
ELECTRICAL CHARACTERISTICS
Test Conditions:
RL = 10kW, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air
temperature range (unless noted otherwise).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static DAC Specifications
Resolution
12
bits
LSB
Integral non-linearity
INL
DNL
See Note 1
See Note 2
See Note 3
See Note 4
See Note 5
See Note 6
See Note 6
±1.9
±0.5
2
±4
±1
Differential non-linearity
Zero code error
LSB
ZCE
mV
±10
±0.6
Gain error
GE
0.1
0.5
10
% FSR
mV/V
ppm/°C
ppm/°C
D.c. power supply rejection ratio
Zero code error temperature coefficient
Gain error temperature coefficient
DAC Output Specifications
Output voltage range
d.c. PSRR
10
0
VDD - 0.1
0.25
V
Output load regulation
2kW to 10kW load
0.1
%
See Note 7
Power Supplies
Active supply current
IDD
No load, VIH = VDD, VIL = 0V
VDD = 5V,
VREF = 2.048V Slow
0.4
0.9
0.3
0.7
0.6
1.35
0.45
1.1
mA
mA
mA
mA
VDD = 5V,
VREF = 2.048V Fast
VDD = 3V,
VREF = 1.024V Slow
VDD = 3V,
VREF = 1.024V Fast
See Note 8
Power down supply current
No load,
all digital inputs 0V or VDD
See Note 9
0.01
10
mA
Dynamic DAC Specifications
Slew rate
DAC code 128 to 4095,
10%-90%
Slow
0.5
2.5
0.9
3.6
V/ms
V/ms
Fast
See Note 10
Settling time
DAC code 128 to 4095
Slow
12.0
4.0
ms
ms
Fast
See Note 11
Code 2047 to 2048
Glitch energy
10
74
nV-s
dB
Signal to noise ratio
SNR
SNRD
THD
fs = 400ksps, fOUT = 1kHz,
BW = 20kHz
66
54
See Note 12
Signal to noise and distortion ratio
Total harmonic distortion
fs = 400ksps, fOUT = 1kHz,
BW = 20kHz
66
-68
70
dB
dB
dB
See Note 12
fs = 400ksps, fOUT = 1kHz,
BW = 20kHz
-56
See Note 12
Spurious free dynamic range
SPFDR
fs = 400ksps, fOUT = 1kHz,
BW = 20kHz
56
See Note 12
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
3
WM2616
Production Data Rev 1.0
Test Conditions:
RL = 10kW, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air
temperature range (unless noted otherwise).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference
Reference input resistance
Reference input capacitance
Reference feedthrough
RREFIN
CREFIN
10
5
MW
pF
VREF = 1VPP at 1kHz
-75
dB
+ 1.024V dc, DAC code 0
Reference input bandwidth
VREF = 0.2VPP + 1.024V dc
DAC code 2048
Slow
0.5
1.3
MHz
MHz
Fast
Digital Inputs
High level input current
Low level input current
Input capacitance
IIH
IIL
CI
Input voltage = VDD
Input voltage = 0V
1
mA
mA
pF
-1
3
Notes:
1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero
code and full scale errors).
2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A
guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code.
3. Zero code error is the voltage output when the DAC input code is zero.
4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.
5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the
zero code error and the gain error.
6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage.
7. Output load regulation is the difference between the output voltage at full scale with a 10kW load and 2kW load. It is expressed as a
percentage of the full scale output voltage with a 10kW load.
8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will increase.
9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.
10. Slew rate results are for the lower value of the rising and falling edge slew rates
11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits
are ensured by design and characterisation, but are not production tested.
12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling frequency fs.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
4
Production Data Rev 1.0
WM2616
SERIAL INTERFACE
tWL
tWH
SCLK
DIN
1
2
3
4
5
15
16
tSUD
tHD
D15
D14
D13
D12
D1
D0
tSUC16CS
tSUCSFS
NCS
FS
tWHFS
tSUFS
tSUC16FS
Figure 1 Timing Diagram
Test Conditions:
RL = 10kW, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air
temperature range (unless noted otherwise).
SYMBOL
tSUCSFS
tSUFS
TEST CONDITIONS
MIN
10
8
TYP
MAX
UNIT
ns
Setup time NCS low before negative FS edge.
Setup time FS low before first negative SCLK edge.
ns
Setup time, sixteenth negative SCLK edge after FS low
on which D0 is sampled before rising edge of FS.
tSUC16FS
10
ns
ns
Setup time, sixteenth positive SCLK edge (first positive
after D0 sampled) before NCS rising edge. If FS is used
instead of the sixteenth positive edge to update the DAC,
then the setup time is between the FS rising edge and
the NCS rising edge.
tSUC16CS
10
Pulse duration, SCLK high.
tWH
tWL
tSUD
tHD
25
25
8
ns
ns
ns
ns
ns
Pulse duration, SCLK low.
Setup time, data ready before SCLK falling edge.
Hold time, data held valid after SCLK falling edge.
Pulse duration, FS high.
5
tWHFS
20
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
5
WM2616
Production Data Rev 1.0
TYPICAL PERFORMANCE GRAPHS
3
AVDD = DVDD = 5V, VREF = 2.048V, Speed = Fast mode, Load = 10k/100pF
2
1
0
-1
-2
-3
0
512
1024
1536
2048
2559
3071
3583
4095
DIGITAL CODE
Figure 2 Integral Non-Linearity
0.4
0.4
0.35
0.3
VDD = 3V, VREF = 1V, Input Code = 0
VDD = 5V, VREF = 2V, Input Code = 0
0.35
0.3
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0
0.05
0
0
1
2
3
4
5
6
7
8
9
10
Fast
0
1
2
3
4
5
6
7
8
9
10
Fast
ISINK - mA
ISINK - mA
Slow
Slow
Figure 3 Sink Current VDD = 3V
Figure 4 Sink Current VDD = 5V
2.06
4.1
VDD = 3V, VREF = 1V, Input Code = 4095
VDD = 5V, VREF = 2V, Input Code = 4095
2.055
2.05
4.095
4.09
2.045
2.04
4.085
4.08
2.035
2.03
4.075
4.07
2.025
4.065
0
1
2
3
4
5
6
7
8
9
10
Fast
0
1
2
3
4
5
6
7
8
9
Slow
10
Fast
ISOURCE - mA
ISOURCE - mA
Slow
Figure 5 Source Current VDD = 3V
Figure 6 Source Current VDD = 5V
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
6
Production Data Rev 1.0
WM2616
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input
voltage and the input code according to the following relationship:
CODE
Output voltage = 2
(
VREFIN
)
4096
INPUT
OUTPUT
4095
4096
1111
1111
1111
(
REF
)
)
2 V
:
:
2049
4096
1000
1000
0111
0000
0001
0000
1111
2
(V
REF
2048
4096
0000
1111
2
(
V
REF
)
= VREF
2047
(
REF
)
2 V
4096
:
:
1
0000
0000
0000
0001
0000
2
(V
REF
)
4096
0000
0V
Table 1 Binary Code Table (0V to 2VREFIN Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kW
load with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent of code.
The REFIN pin has an input resistance of 10MW and an input capacitance of typically 5pF. The
reference voltage determines the DAC full-scale output.
SERIAL INTERFACE
Explanation of data transfer:
First, the device has to be enabled with NCS set to low. Then, a falling edge of FS starts shifting the
data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits
have been transferred, the next rising edge on SCLK or FS causes the content of the shift register to be
moved to the DAC latch which updates the voltage output to the new level.
The serial interface of the device can be used in two basic modes:
·
·
four wire (with chip select)
three wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one device connected to the serial
port of the data source (DSP or microcontroller). If there is no need to have more than one device on the
serial bus, then NCS can be tied low.
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
1
fSCLKmax =
= 20MHz
tWCH min+ tWCL min
The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC settling
time to 12 bits limits the update rate for large input step transitions.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
7
WM2616
Production Data Rev 1.0
SOFTWARE CONFIGURATION OPTIONS
The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D0 contains the 12-bit
data word. D14-D13 hold the programmable options.
D15 D14 D13 D12 D11 D10 D9
SPD PWR
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
New DAC value (12 bits)
Table 2 Register Map
PROGRAMMABLE SETTLING TIME
Settling time is a software selectable 12ms or 4ms typical, to within ±0.5LSB of final value. This is
controlled by the value of D14. A ONE defines a settling time of 4ms, a ZERO defines a settling time of
12ms.
PROGRAMMABLE POWER DOWN
The power down function is controlled by D13. A ZERO configures the device as active, or fully
powered up, a ONE configures the device into power down mode. When the power down function is
released the device reverts to the DAC code set prior to power down.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
8
Production Data Rev 1.0
WM2616
PACKAGE DIMENSIONS
D: 8 PIN SOIC 3.9mm Wide Body
DM009.B
B
e
8
5
E
H
L
1
4
D
h x 45o
A1
A
-C-
a
C
0.10 (0.004)
SEATING PLANE
Dimensions
(mm)
Dimensions
(Inches)
Symbols
MIN
1.35
0.10
0.33
0.19
4.80
MAX
1.75
0.25
0.51
0.25
5.00
MIN
MAX
A
A1
B
C
D
e
0.0532
0.0040
0.0130
0.0075
0.1890
0.0688
0.0098
0.0200
0.0098
0.1968
1.27 BSC
0.050 BSC
E
h
H
L
3.80
0.25
5.80
0.40
0o
4.00
0.50
6.20
1.27
8o
0.1497
0.0099
0.2284
0.0160
0o
0.1574
0.0196
0.2440
0.0500
8o
a
REF:
JEDEC.95, MS-012
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
9
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