WM2639 [WOLFSON]

12-Bit Parallel Input Voltage Output DAC with Internal Reference; 12位并行输入电压输出DAC ，内置基准


型号：	WM2639
厂家：	WOLFSON MICROELECTRONICS PLC
描述：	12-Bit Parallel Input Voltage Output DAC with Internal Reference 12位并行输入电压输出DAC ，内置基准
文件：	总10页 (文件大小：345K)
中文：	中文翻译
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WM2639

12-Bit Parallel Input Voltage Output DAC

with Internal Reference

Production Data, July 1999, Rev 1.0

FEATURES

DESCRIPTION

12-bit voltage output DAC

The WM2639 is a 12-bit voltage output, resistor string, digital-to-

analogue converter. A hardware controlled power down mode is

provided that reduces current consumption to 10nA. The device

has been designed to interface efficiently to industry standard

microprocessors and DSPs.

Single supply 2.7V to 5.5V operation

DNL ±0.3 LSBs, INL ±1.2 LSBs

Internal programmable voltage reference

Settling time 1ms typical

12-bit microprocessor compatible interface

Power down mode 10nA

The WM2639 features an internal programmable voltage reference

simplifying overall system design. The reference voltage can also

be supplied externally.

APPLICATIONS

Excellent performance is delivered with a typical DNL of 0.3 LSBs

and typical INL of 1.2 LSBs. The output stage is buffered by a x2

gain near rail-to-rail amplifier, which features a Class A output

stage (slow mode, Class AB). The 12 data bits are double buffered

enabling the output to be asynchronously updated under hardware

control. The settling time of the DAC is software programmable to

allow the designer to optimise speed versus power dissipation.

Battery powered test instruments

Digital offset and gain adjustment

Battery operated/remote industrial controls

Machine and motion control devices

Wireless telephone and communication systems

Speech synthesis

Arbitrary waveform generation

Mass storage devices

The device is available in a 20-pin TSSOP package. Commercial

temperature (0° to 70°C) and Industrial temperature (-40° to 85°C)

variants are supported.

ORDERING INFORMATION

DEVICE

TEMP. RANGE

0° to 70°C

PACKAGE

WM2639CDT

WM2639IDT

20-pin TSSOP

-40° to 85°C

BLOCK DIAGRAM

TYPICAL PERFORMANCE

VDD

(11)

REFERENCE

OUTPUT BUFFER

WITH OUPUT

ENABLE

5V = VDD, V_REF

1.024V/2.048V

0.8

SELECTABLE

REFERENCE

REF(12)

0.4

0.2

2-BIT

REFERENCE

SELECT

LATCH

REFERENCE

INPUT

BUFFER

DAC

OUTPUT

BUFFER

-0.2

-0.4

12-BIT

DAC

LATCH

D[0-11]

(19,20, 1-10)

(13) OUT

data

12-BIT

INPUT

NWE (17)

NCS (18)

2-BIT

CONTROL

LATCH

POWERDOWN

CONTROL

-0.8

-1

REG (15)

POWER-ON

RESET

512

1024

2048

2559

3583

4095

WM2639

(14)

(16)

GND

NLDAC

WOLFSON MICROELECTRONICS LTD

Production Data contain final specifications

Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK

Tel: +44 (0) 131 667 9386

current on publication date. Supply of products

conforms to Wolfson Microelectronics’ Terms

and conditions..

Fax: +44 (0) 131 667 5176

Email: sales@wolfson.co.uk

http://www.wolfson.co.uk

Master 15/07/99 15:02

Ó1999 Wolfson Microelectronics Ltd.

WM2639

Production Data

PIN CONFIGURATION

NCS

NWE

NLDAC

REG

AGND

OUT

D10

D11

REF

VDD

PIN DESCRIPTION

PIN NO

NAME

TYPE

Digital input

Supply

DESCRIPTION

Data input.

D10

D11

VDD

REF

OUT

AGND

REG

NLDAC

Data input.

Data input.(MSB)

Positive power supply.

Analogue I/O

Analogue output

Supply

Analogue reference voltage input/output.

DAC analogue voltage output.

Analogue Ground.

Digital input

Load DAC. Digital input active low. NLDAC must be taken low to update

the DAC latch from the holding latches.

NWE

NCS

Digital input

Write enable. Digital input active low.

Chip select. Digital input active low.

Data input. (LSB)

Data input.

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 July 1999

Production Data

WM2639

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at

or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

Characteristics at the test conditions specified

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible

to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage

of this device.

CONDITION

MIN

MAX

Digital supply voltages, VDD to GND

Reference input voltage

-0.3V

VDD + 0.3V

Digital input voltage range to GND

Operating temperature range, T_A

70 C

85 C

WM2639CDT

WM2639IDT

0 C

-40 C

Storage temperature

-65 C

150 C

Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds

260 C

RECOMMENDED OPERATING CONDITIONS

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply voltage

VDD

V_IH

V_IL

2.7

5.5

High-level digital input voltage

Low-level digital input voltage

Reference voltage to REF

Load resistance

VDD = 2.7V to 5.5V

See Note

0.8

V_REF

R_L

VDD - 1.5

°C

Load capacitance

C_L

100

Operating free-air temperature

T_A

WM2639CDT

WM2639IDT

-40

Note: Reference voltages greater than VDD/2 will cause output saturation for large DAC codes.

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 July 1999

WM2639

Production Data

ELECTRICAL CHARACTERISTICS

Test Conditions:

R_L= 10kW, C_L= 100pF. VDD = 5V ± 10%, V_REF= 2.048V and VDD = 3V ± 10%, V_REF= 1.024V over recommended operating free-air

temperature range (unless noted otherwise)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Static DAC Specifications

Resolution

bits

LSB

Integral non-linearity

INL

DNL

See Note 1

See Note 2

See Note 3

See Note 4

See Note 5

See Note 6

±1.2

±0.3

±3

Differential non-linearity

Zero code error

LSB

±0.5

±20

±0.3

ZCE

Gain error

% FSR

mV/V

ppm/°C

d.c. power supply rejection ratio

Zero code error temperature coefficient

Gain error temperature coefficient

DAC Output Specifications

Output voltage range

DC PSRR

0.5

VDD - 0.4

0.3

Output load regulation

2kW to 10kW load

0.1

See Note 7

Power Supplies

Active supply current

I_DD

No load, V_IH= VDD, V_IL= 0V

VDD = 5V, V_REF= 2.048V,

Internal

Slow

1.3

2.3

1.6

2.8

Fast

VDD = 5V, V_REF= 2.048V,

External

Slow

0.9

1.9

1.2

2.4

Fast

VDD = 3V, V_REF= 1.024V,

Internal

Slow

1.2

2.1

1.5

2.6

Fast

VDD = 3V, V_REF= 1.024V,

External

Slow

0.9

1.8

1.1

2.3

Fast

See Note 8

Power down supply current

No load,

0.01

all inputs 0V or VDD

See Note 9

Dynamic DAC Specifications

Slew rate

DAC code 32-4095,

10%-90%

Slow

Fast

1.2

6.0

1.7

V/ms

See Note 10

DAC code 32-4095

Slow

Settling time

3.5

Fast

See Note 11

Code 2047 to 2048

Glitch energy

nV-s

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 July 1999

Production Data

WM2639

Test Conditions:

R_L= 10kW, C_L= 100pF. VDD = 5V ± 10%, V_REF= 2.048V and VDD = 3V ± 10%, V_REF= 1.024V over recommended operating free-air

temperature range (unless noted otherwise)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fs = 480ksps, f_OUT= 1kHz,

BW = 20kHz, T_A=25°C

See Note 12

Signal to noise ratio

SNR

Signal to noise and distortion ratio

Total harmonic distortion

SNRD

THD

fs = 480ksps, f_OUT= 1kHz, BW

-69

= 20kHz, T_A=25°C

See Note 12

fs = 480ksps, f_OUT= 1kHz, BW

-62

= 20kHz, T_A=25°C

See Note 12

Spurious free dynamic range

SPFDR fs = 480ksps, f_OUT= 1kHz, BW

= 20kHz, T_A= 25°C

See Note 12

Reference configured as input

Reference input resistance

Reference input capacitance

Reference feedthrough

R_REFIN

C_REFIN

V_REF= 1V_PPat 1kHz

-60

+ 1.024Vdc, DAC code 0

Reference input bandwidth

V_REF= 0.2V_PP+ 1.024V d.c.

DAC code 2048

Slow

500

900

kHz

Fast

Reference configured as output

Low reference voltage

High reference voltage

Output source current

Output sink current

Load Capacitance

V_REFOUTL

1.003

2.027

1.024

2.048

1.045

2.069

V_REFOUTH

I_REFSRC

I_REFSNK

VDD > 4.75V

-1

100

PSRR

-48

Digital Inputs

High level input current

Low level input current

Input capacitance

I_IH

I_IL

C_I

Input voltage = VDD

Input voltage = 0V

-1

Notes:

1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects

of zero code and full scale errors).

2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two

codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in

digital input code.

3. Zero code error is the voltage output when the DAC input code is zero.

4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.

5. Power supply rejection ratio is measured by varying V_DDfrom 4.5V to 5.5V and measuring the proportion of this signal imposed on

the zero code error and the gain error.

6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage.

7. Output load regulation is the difference between the output voltage at full scale with a 10kW load and 2kW load. It is expressed as

a percentage of the full scale output voltage with a 10kW load.

8. I_DDis measured while continuously writing code 2048 to the DAC. For V_IH< V_DD- 0.7V and V_IL> 0.7V supply current will increase.

9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.

10. Slew rate results are for the lower value of the rising and falling edge slew rates.

11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges.

Limits are ensured by design and characterisation, but are not production tested.

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 July 1999

WM2639

Production Data

12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f_OUTgenerated with a sampling frequency fs_.

SERIAL INTERFACE

t_SUD

DATA

D[0-11]

REG

t_SUR

REG

t_HDR

NCS

NWE

t_SUCSWE

t_WHWE

t_SUWELD

t_WLD

NLDAC

Figure 1 Timing Diagram

Test Conditions:

R_L= 10kW, C_L= 100pF. V_DD= 5V±10%, V_REF= 2.048V and V_DD= 3V±10%, V_REF= 1.024V over recommended operating free-air

temperature range (unless noted otherwise)

SYMBOL

t_SUCSWE

t_SUD

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Setup time NCS low before positive NWE edge

Setup time data ready before positive NWE edge

Setup time REG ready before positive NWE edge

Data and REG hold after positive NWE edge

Setup time NWE high before NLDAC low

High pulse width of NWE

t_SUR

t_HDR

t_SUWELD

t_WHWE

t_WLD

Low pulse width of NLDAC

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 July 1999

Production Data

WM2639

TYPICAL PERFORMANCE GRAPHS

5V = VDD, V_REF= External. 2.048V, Speed = Fast mode, Load = 10k/100pF

-1

-2

-3

512

1024

1536

2048

2559

3071

3583

4095

DIGITAL CODE

Figure 2 Integral Non-Linearity

VDD = 5V, V_REF= Int. 2V, Input Code = 0

VDD = 3V, V_REF= Internal. 1V, Input Code = 0

4.5

2.5

3.5

2.5

1.5

0.5

1.5

2.5

3.5

0.5

1.5

2.5

3.5

ISINK - mA

Slow

Fas)

Slow

Fast

Figure 3 Sink Current VDD = 3V

Figure 4 Sink Current VDD = 5V

2.0395

4.0795

VDD = 5V, V_REF= Int. 2V, Input Code = 4095

VDD = 3V, V_REF= Int. 1V, Input Code = 4095

2.039

4.079

4.0785

4.078

2.0385

2.038

2.0375

2.037

4.0775

4.077

2.0365

2.036

4.0765

4.076

2.0355

2.035

4.0755

4.075

0.5

1.5

2.5

3.5

0.5

1.5

2.5

3.5

ISOURCE - mA

Slow

Fast

Slow

Fast

Figure 5 Source Current VDD = 3V

Figure 6 Source Current VDD = 5V

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 July 1999

WM2639

Production Data

DEVICE DESCRIPTION

GENERAL FUNCTION

The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to

analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input

voltage and the input code according to the following relationship:

CODE

Output voltage = 2

(

VREF

)

4096

INPUT

OUTPUT

1111

4095

4096

(

VREF

)

1000

0111

0000

0001

0000

1111

2049

4096

VREF

0000

1111

2048

4096

(

VREF

)

= VREF

2047

(

VREF

)

4096

0000

0001

0000

VREF

4096

0000

Table 1 Binary Code Table (0V to 2V_REFOutput), Gain = 2

POWER ON RESET

An internal power-on-reset circuit resets the DAC register to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kW

load with a 100pF load capacitance.

HARDWARE CONFIGURATION OPTIONS

The WM2639 has one configuration option that is controlled by a device pin.

DAC UPDATE

The NLDAC pin (Pin 16) can be held high to prevent word writes from updating the DAC latch. By writing

the new value to the DAC then pulling NLDAC low, the new DAC code is loaded into the DAC latch.

PARALLEL INTERFACE

The device registers data on the positive edge of NWE (Pin 17). It must be enabled with NCS (Pin 18)

low. Whether the data is written to the DAC holding latch or the control register, depends on the state of

input pin REG (Pin 15). REG = 0 selects the DAC holding latch, REG = 1 selects the control register.

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 July 1999

Production Data

WM2639

SOFTWARE CONFIGURATION OPTIONS

DATA FORMAT

The WM2639 writes data either to the DAC holding latch or to the control register depending on the state

of input pin REG.

REG

DATA DESTINATION

(PIN 15)

DAC holding latch

Control register

D11

D10

REF1 REF0

PWR SPD

Table 1 Register Bits

PROGRAMMABLE SETTLING TIME

Settling time is a software selectable 3.5ms or 1ms, typical to within ±0.5LSB of final value. This is

controlled by the value of SPD – Bit D0. A ONE defines a settling time of 1ms, a ZERO (default) defines a

settling time of 3.5ms.

PROGRAMMABLE POWER DOWN

The power down function can be controlled by PWR. A ZERO configures the device as active, or fully

powered up, a ONE configures the device into power down mode. When the power down function is

released the device reverts to the DAC code set prior to power down.

PROGRAMMABLE INTERNAL REFERENCE

The reference can be sourced internally or externally under software control. If an external reference

voltage is applied to the REF pin, the device must be configured to accept this.

If an external reference is selected, the reference voltage input is buffered which makes the DAC input

resistance independent of code. The REF pin has an input resistance of 10MW and an input capacitance

of typically 55pF. The reference voltage determines the DAC full-scale output.

If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal reference can

source up to 1mA and can therefore be used as an external system reference.

REF1

REF0

REFERENCE

External (default)

1.024V

2.048V

External

Table 2 Programmable Internal Reference

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 July 1999

WM2639

Production Data

PACKAGE DIMENSIONS

DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm)

DM008.C

GAUGE

PLANE

0.25

-C-

0.05

SEATING PLANE

Dimensions

(mm)

NOM

-----

Symbols

MIN

-----

MAX

1.20

0.15

1.05

0.30

0.20

6.60

A₁

A₂

E₁

0.05

0.80

0.19

0.09

6.40

-----

1.00

-----

6.50

0.65 BSC

6.4 BSC

4.40

4.30

0.45

0^o

4.50

0.75

0.60

REF:

NOTES:

A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.

B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.

D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

WOLFSON MICROELECTRONICS LTD

Production Data Rev 1.0 July 1999

WM2639 [WOLFSON]

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