WM8216SEFL [WOLFSON]
60MSPS 10-bit 2-channel CCD Digitiser; 60MSPS 10位2通道CCD数字转换器
| 型号： | WM8216SEFL |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | 60MSPS 10-bit 2-channel CCD Digitiser |
| 文件： | 总27页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8216
w
60MSPS 10-bit 2-channel CCD Digitiser
DESCRIPTION
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
10-bit ADC
The WM8216 is a 10-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 60MSPS.
60MSPS conversion rate
Low power – 330mW typical
3.3V single supply operation
Single or dual channel operation
Correlated double sampling
The device includes two analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset adjust functions. The output from each of these
channels is time multiplexed into a single high-speed 10-bit
Analogue to Digital Converter. The digital output data is
available in 10-bit wide parallel format.
Programmable gain (9-bit resolution)
Programmable offset adjust (8-bit resolution)
Flexible clamp timing
Programmable clamp voltage
Internally generated voltage references
32-lead QFN package
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Clamping to clamp CCD signals. An
external reference level may also be supplied. ADC
references are generated internally, ensuring optimum
performance from the device.
Serial control interface
APPLICATIONS
•
•
•
•
Digital Copiers
Using an analogue supply voltage of 3.3V and a digital
interface supply of 3.3V, the WM8216 typically only
consumes 330mW
USB2.0 compatible scanners
Multi-function peripherals
High-speed CCD/CIS sensor interface
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
Production Data, March 2007, Rev 4.0
Copyright ©2007 Wolfson Microelectronics plc.
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/
WM8216
Production Data
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM .................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
PIN DESCRIPTION ................................................................................................4
ABSOLUTE MAXIMUM RATINGS.........................................................................5
RECOMMENDED OPERATING CONDITIONS .....................................................5
THERMAL PERFORMANCE .................................................................................5
ELECTRICAL CHARACTERISTICS ......................................................................6
INPUT VIDEO SAMPLING ............................................................................................ 8
SERIAL INTERFACE................................................................................................... 10
INTERNAL POWER ON RESET CIRCUIT ..........................................................10
DEVICE DESCRIPTION.......................................................................................12
INTRODUCTION......................................................................................................... 12
INPUT SAMPLING ...................................................................................................... 12
RESET LEVEL CLAMPING (RLC)............................................................................... 12
CDS/NON-CDS PROCESSING................................................................................... 15
OFFSET ADJUST AND PROGRAMMABLE GAIN ...................................................... 15
ADC INPUT BLACK LEVEL ADJUST.......................................................................... 16
OVERALL SIGNAL FLOW SUMMARY........................................................................ 17
CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT ..................................... 18
REFERENCES............................................................................................................ 19
POWER MANAGEMENT ............................................................................................ 19
CONTROL INTERFACE.............................................................................................. 19
NORMAL OPERATING MODES ................................................................................. 20
DEVICE CONFIGURATION .................................................................................21
REGISTER MAP ......................................................................................................... 21
REGISTER MAP DESCRIPTION ................................................................................ 22
APPLICATIONS INFORMATION .........................................................................25
RECOMMENDED EXTERNAL COMPONENTS.......................................................... 25
RECOMMENDED EXTERNAL COMPONENT VALUES ............................................. 25
PACKAGE DIMENSIONS ....................................................................................26
IMPORTANT NOTICE..........................................................................................27
ADDRESS: .................................................................................................................. 27
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PIN CONFIGURATION
ORDERING INFORMATION
MOISTURE
SENSITIVITY
TEMPERATURE
PEAK SOLDERING
TEMPERATURE
DEVICE
RANGE
PACKAGE
LEVEL
32-lead QFN
(5x5x0.9mm)
(Pb free)
WM8216SEFL
0 to 70oC
0 to 70oC
MSL1
260°C
260°C
32-lead QFN
(5x5x0.9mm)
WM8216SEFL/R
MSL1
(Pb free, tape and reel)
Note:
Reel quantity = 3,500
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PIN DESCRIPTION
PIN
1
NAME
RSMP
MCLK
DGND
SEN
TYPE
DESCRIPTION
Digital input
Digital input
Supply
Reset sample pulse (when CDS=1) or clamp control (CDS=0)
Master (ADC) clock. This clock determines the ADC conversion rate.
Digital ground.
2
3
4
Digital input
Supply
Enables the serial interface when high.
Digital supply, all digital I/O pins.
Serial data input.
5
DVDD2
SDI
6
Digital input
Digital input
No connect
No connect
7
SCK
Serial clock.
8
NC
No internal connection.
9
NC
No internal connection.
Digital output data bus. ADC output data (d9:d0) is available in 10-bit parallel
format.
10
11
12
13
14
15
16
17
18
19
OP[0]
OP[1]
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
d0 (LSB)
d1
OP[2]
d2
OP[3]
d3
OP[4]
d4
OP[5]
d5
OP[6]
d6
OP[7]
d7
OP[8]
d8
OP[9]/SDO
d9 (MSB)
Alternatively, pin OP[9]/SDO may be used to output register read-back data when
OEB=0, OPD(register bit)=0 and SEN has been pulsed high. See Serial Interface
description in Device Description section for further details.
20
21
22
AVDD
AGND1
VRB
Supply
Supply
Analogue supply. This must be operated at the same potential as DVDD1.
Analogue ground.
Analogue output Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Analogue output Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Analogue output Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
23
24
25
VRT
VRX
VRLC/VBIAS
Analogue I/O
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
26
27
28
29
30
TEST
EINP
Analogue I/O
Analogue input
Analogue input
Supply
Used for test purposes only. Do not externally connect – leave this pin floating.
Even channel input video.
Odd channel input video.
Analogue ground.
OINP
AGND2
DVDD1
Supply
Digital supply for logic and clock generator. This must be operated at the same
potential as AVDD.
31
32
OEB
Digital input
Digital input
Output Hi-Z control. All digital outputs set to high-impedance state when input pin
OEB=1 or register bit OPD=1.
VSMP
Video sample pulse.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
MAX
Analogue supply voltage: AVDD
Digital supply voltages: DVDD1 − 2
Digital ground: DGND
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND + 4.2V
GND + 4.2V
GND + 0.3V
GND + 0.3V
DVDD2 + 0.3V
AVDD + 0.3V
AVDD + 0.3V
Analogue grounds: AGND1 − 2
Digital inputs, digital outputs and digital I/O pins
Analogue inputs (EINP, OINP)
Other pins
°
°
Operating temperature range: TA
Storage temperature prior to soldering
Storage temperature after soldering
Notes:
0 C
+70 C
°
30 C max / 85% RH max
°
°
+150 C
-65 C
1.
2.
GND denotes the voltage of any ground pin.
AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages
between these pins will degrade performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION
SYMBOL
TA
MIN
0
TYP
MAX
70
UNITS
Operating temperature range
Analogue supply voltage
Digital core supply voltage
Digital I/O supply voltage
Notes:
°C
V
AVDD
DVDD1
DVDD2
2.97
2.97
2.97
3.3
3.3
3.3
3.63
3.63
3.63
V
V
1. DVDD2 should be operated at the same potential as DVDD1 ± 0.3V.
THERMAL PERFORMANCE
PARAMETER
Performance
SYMBOL
RθJC
TEST CONDITIONS
MIN
TYP
10.27
29.45
MAX
UNIT
°C/W
°C/W
Thermal resistance – junction to
case
Tambient = 25°C
Thermal resistance – junction to
ambient
RθJA
Notes:
1. Figures given are for package mounted on 4-layer FR4 according to JESD51-5 and JESD51-7.
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ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 60MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Overall System Specification (including 10-bit ADC, PGA, Offset and CDS functions)
Conversion rate
60
MSPS
Vp-p
Vp-p
Vp-p
Vp-p
V
Full-scale input voltage range
(see Note 1)
LOWREFS=0, Max Gain
LOWREFS=0, Min Gain
LOWREFS=1, Max Gain
LOWREFS=1, Min Gain
0.25
3.03
0.15
1.82
Input signal limits (see Note 2)
Input capacitance
VIN
AGND-0.3
AVDD+0.3
10
45
20
pF
Input switching impedance
Full-scale transition error
Ω
mV
Gain = 0dB;
PGA[7:0] = 4B(hex)
Zero-scale transition error
Gain = 0dB;
20
mV
PGA[7:0] = 4B(hex)
Differential non-linearity
Integral non-linearity
DNL
INL
0.75
2
LSB
LSB
Channel to channel gain matching
Output noise
1%
0.2
2.15
%
Min Gain
Max Gain
LSB rms
LSB rms
References
Upper reference voltage
VRT
VRB
LOWREFS=0
LOWREFS=1
LOWREFS=0
LOWREFS=1
1.95
0.95
2.05
1.85
1.05
1.25
1.25
1.0
2.25
1.25
V
V
V
V
V
V
V
Ω
Lower reference voltage
Input return bias voltage
VRX
VRTB
Diff. reference voltage (VRT-VRB)
LOWREFS=0
LOWREFS=1
0.9
1.10
0.6
Output resistance VRT, VRB, VRX
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
1
45
2
Ω
mA
Ω
VRLC output resistance
2
VRLC Hi-Z leakage current
RLCDAC resolution
VRLC = 0 to AVDD
1
µA
4
bits
V/step
V/step
V
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
VRLCSTEP
VRLCSTEP
VRLCBOT
AVDD=3.3V
LOWREFS = 0
AVDD=3.3V
0.173
0.11
0.4
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
VRLCTOP
VRLCTOP
LOWREFS = 0
AVDD=3.3V
0.4
3.0
V
V
V
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
RLCDAC output voltage at
LOWREFS = 0
2.05
code F(hex), RLCDACRNG = 1
RLCDAC
RLCDAC
Notes:
DNL
INL
-0.5
+0.5
LSB
LSB
+/-0.5
1.
Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC full-scale
input range.
2.
Input signal limits are the limits within which the full-scale input voltage signal must lie.
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Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 60MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Offset DAC, Monotonicity Guaranteed
Resolution
8
bits
LSB
Differential non-linearity
Integral non-linearity
Step size
DNL
0.15
0.4
INL
LSB
2.04
-255
+255
mV/step
mV
Output voltage
Code 00(hex)
Code FF(hex)
mV
Programmable Gain Amplifier
Resolution
Gain
9
bits
V/V
7.34
0.66 +
* PGA[8 : 0]
511
Max gain, each channel
Min gain, each channel
Channel matching
Analogue to Digital Converter
Resolution
GMAX
GMIN
8
V/V
V/V
%
0.66
1
10
2
bits
MSPS
V
Speed
60
Full-scale input range
(2*(VRT-VRB))
LOWREFS=0
LOWREFS=1
1.2
V
DIGITAL SPECIFICATIONS
Digital Inputs
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
VIH
VIL
IIH
0.7 ∗ DVDD2
V
0.2 ∗ DVDD2
V
1
1
µA
µA
pF
IIL
CI
5
Digital Outputs
High level output voltage
Low level output voltage
High impedance output current
Digital IO Pins
VOH
VOL
IOZ
IOH = 1mA
IOL = 1mA
DVDD2 - 0.5
V
V
0.5
1
µA
Applied high level input voltage
Applied low level input voltage
High level output voltage
Low level output voltage
Low level input current
High level input current
Input capacitance
VIH
VIL
VOH
VOL
IIL
0.7 ∗ DVDD2
V
V
0.2 ∗ DVDD2
IOH = 1mA
IOL = 1mA
DVDD2 - 0.5
V
0.5
1
V
µA
µA
pF
µA
IIH
1
CI
5
High impedance output current
Supply Currents
IOZ
1
Total supply current − active
118
105
mA
mA
Analogue supply current – active
(two channel mode)
Digital supply current, – active
(two channel mode)
13
20
mA
Supply current − full power down
mode
µA
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INPUT VIDEO SAMPLING
tMF1RS
tRSD
tRSFVSR
tVSD
tPR2
tMRVSR
tMFVSF
tVSFMR
tPD
tMCLKL
tMCLKH
tPER
E
O
E
O
E
O
E
n-5
n-4
n-3
n-2
n-1
Figure 1 Two-channel CDS Operation (CDS=1)
Input
Video
PIXEL n
tMF1RS
tPR1
tRSD
tRSFVSR
RSMP
tVSD
tVSFMR
tMRVSR
VSMP
tPD
tMFVSF
MCLK
tMCLKH
tMCLKL
tPER
Output
Data
OP[9:0]
n-8
n-7
n-6
n-5
Figure 2 One-channel CDS Operation (CDS=1)
Notes:
1. The relationship between input video signal and sample points is controlled by VSMP and RSMP.
2. When VSMP is high the input video signal is connected to the Video sampling capacitors.
3. When RSMP is high the input video signal is connected to the Reset sampling capacitors.
4. RSMP must not go high before the first falling edge of MCLK after VSMP goes low.
5. It is required that the falling edge of VSMP should occur before the rising edge of MCLK.
6. In 1-channel CDS mode it is not possible to have equally spaced Video and Reset sample points with a 45MHz
MCLK.
7. Non-CDS operation is also possible; RSMP is not required in this mode but can be used to control input clamping.
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Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 60MHz for 2-channel mode and 45MHz for 1-
channel mode unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
16.6
22.2
7.5
TYP
MAX
UNITS
MCLK period – 2 channel mode
1 channel mode
tPER
ns
MCLK high period – 2 channel mode
1 channel mode
tMCLKH
tMCLKL
8.3
11.1
8.3
ns
ns
MCLK low period – 2 channel mode
1 channel mode
7.5
11.1
RSMP pulse high time
tRSD
tVSD
5
5
0
3
5
1
1
ns
ns
ns
ns
ns
ns
ns
VSMP pulse high time
RSMP falling to VSMP rising time
MCLK rising to VSMP rising time
MCLK falling to VSMP falling time
VSMP falling to MCLK rising time 2
1st MCLK falling edge after VSMP
falling to RSMP rising time
tRSFVSR
tMRVSR
tMFVSF
tVSFMR
tMF1RS
2-channel mode pixel rate
1-channel mode pixel rate
Output propagation delay
Output latency. From 1st rising edge
of MCLK after VSMP falling to data
output
tPR2
tPR1
tPD
33.2
16.6
ns
ns
ns
5
7
10
LAT
MCLK
periods
Notes:
1.
2.
Parameters are measured at 50% of the rising/falling edge.
In 1-Channel mode, if the VSMP falling edge is placed more than 3ns before the rising edge of MCLK the output
amplitude of the WM8216 will decrease.
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SERIAL INTERFACE
Figure 3 Serial Interface Timing
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SCK period
tSPER
83.3
ns
SCK high
tSCKH
tSCKL
tSSU
37.5
37.5
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK low
SDI set-up time
SDI hold time
tSH
6
SCK to SEN set-up time
SEN to SCK set-up time
SEN pulse width
tSCE
12
12
60
tSEC
tSEW
tSERD
tSCRD
tSCRDZ
SEN low to SDO = Register data
SCK low to SDO = Register data
SCK low to SDO = ADC data
30
30
30
Note: 1.
Parameters are measured at 50% of the rising/falling edge
INTERNAL POWER ON RESET CIRCUIT
Figure 4 Internal Power On Reset Circuit Schematic
The WM8216 includes an internal Power-On-Reset Circuit, as shown in Figure 4, which is used to
reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and
monitors DVDD1. It asserts PORB low if AVDD or DVDD1 is below a minimum threshold.
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The powers supplies can be brought up in any order but is important that either AVDD is brought up
before DVDD or vice versa as shown in Figure 5 and Figure 6.
Figure 5 Typical Power up Sequence where AVDD is Powered before DVDD1
Figure 5 shows a typical power-up sequence where AVDD comes up first. When AVDD goes above
the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted
low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now
AVDD is at full supply level. Next DVDD1 rises to Vpord_on and PORB is released high and all
registers are in their default state and writes to the control interface may take place.
Note: It is recommended that every time power is cycled to the WM8216 a software reset is written
to the software register to ensure that the contents of the control registers are at their default values
before carrying out any other register writes.
On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the
minimum threshold Vpora_off.
Figure 6 Typical Power up Sequence where DVDD1 is Powered before AVDD
Figure 6 shows a typical power-up sequence where DVDD1 comes up first. First it is assumed that
DVDD1 is already up to specified operating voltage. When AVDD goes above the minimum
threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the
chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD rises
to Vpora_on, PORB is released high and all registers are in their default state and writes to the
control interface may take place.
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On power down, where DVDD1 falls first, PORB is asserted low whenever DVDD1 drops below the
minimum threshold Vpord_off.
SYMBOL
Vpora
TYP
0.6
1.2
0.6
0.7
0.6
UNIT
V
V
V
V
V
Vpora_on
Vpora_off
Vpord_on
Vpord_off
Table 1 Typical POR Operation (typical values, not tested)
DEVICE DESCRIPTION
INTRODUCTION
A block diagram of the device showing the signal path is presented on the front page of this
datasheet.
The WM8216 samples up to two inputs (OINP and EINP) simultaneously. The device then processes
the sampled video signal with respect to the video reset level or an internally/externally generated
reference level using either one or two processing channels.
Each processing channel consists of an Input Sampling block with optional Reset Level Clamping
(RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and a 9-bit
Programmable Gain Amplifier (PGA).
The ADC then converts each resulting analogue signal to a 10-bit digital word. The digital output from
the ADC is presented in parallel on the 10-bit wide output bus, OP[9:0]. The ten output pins can be
set to a high impedance state using either the OEB control pin or the OPD register bit.
On-chip control registers determine the configuration of the device, including the offsets and gains
applied to each channel. These registers are programmable via a serial interface.
INPUT SAMPLING
The WM8216 can sample and process up to two inputs through one or two processing channels as
follows:
Two Channel Pixel-by-pixel: Two input channels (OINP and EINP) are simultaneously sampled for
each pixel and a separate channel processes each input. The signals are then multiplexed into the
ADC, which converts both inputs within the pixel period.
Monochrome: A single chosen input (OINP or EINP) is sampled, processed by the corresponding
channel, and converted by the ADC. The choice of input and channel can be changed via the control
interface. The unused channel is powered down when this mode is selected.
RESET LEVEL CLAMPING (RLC)
To ensure that the signal applied to the WM8216 lies within the supply voltage range (0V to AVDD)
the output signal from a CCD is usually level shifted by coupling through a capacitor, CIN. The RLC
circuit clamps the WM8216 side of this capacitor to a suitable voltage through a CMOS switch during
the CCD reset period (pixel clamping) or during the black pixels (line clamping). In order for clamping
to produce correct results the input voltage during the clamping must be a constant value.
The WM8216 allows the user to control the RLC switch in a variety of ways. Odd and Even channels
are identical, each with its own clamp switch controlled by the common CLMP signal.
The method of control chosen depends upon the characteristics of the input video. The RLCEN
register bit must be set to 1 to enable clamping, otherwise the RLC switch cannot be closed (by
default RLCEN=1).
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Figure 7 RLC Clamp Control Options
When an input waveform has a stable reference level on every pixel it may be desirable to clamp
every pixel during this period. Setting CLMPCTRL=0 means that the RLC switch is closed whenever
the RSMP input pin is high, as shown in Figure 8.
reference
("black") level
INPUT VIDEO
SIGNAL
video level
MCLK
VSMP
RSMP
Video sample taken on
fallling edge of VSMP
Reset/reference sample taken
on fallling edge of RSMP
RLC switch control
"CLMP"
RLC switch closed
when RSMP=1
(RLCEN=1,CLMPCTRL=0)
Figure 8 Reset Level Clamp Operation (CLMPCTRL=0), CDS operation shown, non-CDS also possible
In situations where the input video signal does not have a stable reference level it may be necessary
to clamp only during those pixels which have a known state (e.g. the dummy, or “black” pixels at the
start or end of a line on most image sensors). This is known as line-clamping and relies on the input
capacitor to hold the DC level between clamp intervals. However, it should be noted that in non-CDS
mode, this method of operation will result in a slow drift in the output codes. In non-CDS mode
(CDS=0) line clamping can be done directly by controlling the RSMP input pin to go high during the
black pixels only.
Alternatively it is possible to use RSMP to identify the black pixels and enable the clamp at the same
time as the input is being sampled (i.e. when VSMP is high and RSMP is high). This mode is
enabled by setting CLMPCTRL=1 and the operation is shown in Figure 9.
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unstable
reference level
dummy or
"black" pixel
INPUT VIDEO
SIGNAL
MCLK
VSMP
RSMP
video level
Video and reference sample
taken on fallling edge of VSMP
RLC switch closed when RSMP=1 &&
VSMP=1 (during "black" pixels)
RLC switch control,
"CLMP"
(RLCEN=1,CLMPCTRL=1)
Figure 9 Reset Level Clamp Operation (CLMPCTRL=1), non-CDS mode only
RLCEN
CLAMPCTRL
OUTCOME
USE
RLC is not enabled. RLC switch is always open.
When input is DC coupled and within supply
rails.
0
X
RLC switch is controlled directly from RSMP input
pin:
When user explicitly provides a reset sample
signal and the input video waveform has a
suitable reset level.
1
1
0
1
RSMP=0: switch is open
RMSP=1: switch is closed
VSMP applied as normal, RSMP is used to
indicate the location of black pixels
When clamping during the video period of black
pixels or there is no stable per-pixel reference
level.
RLC switch is controlled by logical combination of
RSMP and VSMP:
RSMP && VSMP = 0: switch is open
RSMP && VSMP = 1: switch is closed
Table 2 Reset Level Clamp Control Summary
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CDS/NON-CDS PROCESSING
For CCD type input signals, containing a fixed reference/reset level, the signal may be processed
using Correlated Double Sampling (CDS), which will remove pixel-by-pixel common mode noise.
With CDS processing the input waveform is sampled at two different points in time for each pixel,
once during the reference/reset level and once during the video level. To sample using CDS, register
bit CDS must be set to 1 (default). This causes the signal reference to come from the video reference
level as shown in Figure 10.
The video sample is always taken on the falling edge of the input VSMP signal (VS). In CDS-mode
the reset level is sampled on the falling edge of the RSMP input signal (RS).
For input signals that do not contain a reference/reset level (e.g. CIS sensor signals), non-CDS
processing is used (CDS=0). In this case, the video level is processed with respect to the voltage on
pin VRLC/VBIAS. The VRLC/VBIAS voltage is sampled at the same time as VSMP samples the
video level in this mode.
It should be noted that if a coupling capacitor is used on OINP or EINP in non-CDS mode, a drift in
output code will be seen, unless the input is clamped each pixel – see Reset Level Clamping section.
The drift effect can be reduced by increasing the size of coupling capacitor used or reducing the
number of samples between clamping.
Figure 10 CDS/non-CDS Input Configuration
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by a 9-bit PGA. The gain and offset for each
channel are independently programmable by writing to control bits DAC[7:0] and PGA[8:0].
The gain characteristic of the WM8216 PGA is shown in Figure 11.. Figure 12 shows the maximum
device input voltage that can be gained up to match the ADC full-scale input range (default=2V).
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3.5
3
8
Max i/p Voltage
LOWREFS=0
7
6
5
4
3
2
1
Max i/p Voltage
LOWREFS=1
2.5
2
1.5
1
0.5
0
0
0
128
256
384
512
0
128
256
384
512
Gain Code (PGA[8:0])
Gain Code (PGA[8:0])
Figure 11 PGA Gain Characteristic
Figure 12 Peak Input Voltage to Match ADC Full-scale Range
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA can be offset to match the full-scale range of the differential ADC (2*[VRT-
VRB]).
For negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. This will give an output
code of 3FF (hex) from the WM8216 for zero input. If code zero is required for zero differential input
then the INVOP bit should be set.
For positive going input signals the black level should be offset to the bottom of the ADC range by
setting PGAFS[1:0]=11. This will give an output code of 000 (hex) from the WM8216 for zero input.
Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01. Zero differential
input voltage gives mid-range ADC output, 1FF (hex).
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Figure 13 ADC Input Black Level Adjust Settings
OVERALL SIGNAL FLOW SUMMARY
Figure 14 represents the processing of the video signal through the WM8216.
Figure 14 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the
difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the
difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC
optionally set via the RLC DAC.
,
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V2.
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V3.
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The ADC BLOCK then converts the analogue signal, V3, to a 10-bit unsigned digital output, D1.
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.
CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT
The following equations describe the processing of the video and reset level signals through
the WM8216.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the
input video.
V1
=
VIN - VRESET
Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
V1
=
VIN - VVRLC
Eqn. 2
If VRLCDACPD = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.
If VRLCDACPD = 0, VVRLC is the output from the internal RLC DAC.
VVRLC
=
(VRLCSTEP ∗ RLC DAC[3:0]) + VRLCBOT
Eqn. 3
VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V1 is added to the Offset DAC output.
V2
=
V1 + {255mV ∗ (DAC[7:0]-127.5) } / 127.5
Eqn. 4
Eqn. 5
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain.
V3
=
V2 ∗ (0.66 + PGA[8:0]x7.34/511)
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 10-bit unsigned number, with input range configured by
PGAFS[1:0].
D1[9:0] = INT{ (V3 /VFS) ∗ 1023} + 511
D1[9:0] = INT{ (V3 /VFS) ∗ 1023}
PGAFS[1:0] = 00 or 01
PGAFS[1:0] = 11
Eqn. 6
Eqn. 7
Eqn. 8
D1[9:0] = INT{ (V3 /VFS) ∗ 1023} + 1023
PGAFS[1:0] = 10
where the ADC full-scale range, VFS = 2V when LOWREFS=0 and VFS = 1.2V when LOWREFS=1.
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
D2[9:0] = D1[9:0]
(INVOP = 0)
(INVOP = 1)
Eqn. 9
D2[9:0] = 1023 – D1[9:0]
Eqn. 10
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REFERENCES
The ADC reference voltages are derived from an internal band-gap reference, and buffered to pins
VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and
also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin
VRLC/VBIAS.
The ADC references can be switched from the default values (VRT=2.05V, VRB=1.05V, ADC input
range=2V) to give a smaller ADC reference range (VRT=1.85V, VRB=1.25V, ADC input range=1.2V)
under control of the LOWREFS register bit. Setting LOWREFS=1 allows smaller input signals to be
accommodated.
Note:
When LOWREFS = 1 the output of the RLCDAC will scale if RLCDACRNG = 1. The max output
from RLCDAC will change from 2.05 to 1.85V and the step size will proportionally reduce.
POWER MANAGEMENT
Power management for the device is performed via the Control Interface. By default the device is
fully enabled. The EN bit allows the device to be fully powered down when set low. Individual blocks
can be powered down using the bits in Setup Register 5. When in MONO mode the unused input
channels are automatically disabled to reduce power consumption.
CONTROL INTERFACE
The internal control registers are programmable via the serial digital control interface. The register
contents can be read back via the serial interface on pin OP[9]/SDO.
It is recommended that a software reset is carried out after the power-up sequence, before writing to
any other register. This ensures that all registers are set to their default values (as shown in Table
5).
SERIAL INTERFACE: REGISTER WRITE
Figure 15 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit
address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data
word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Setting address bit a4 to 0 indicates that the
operation is a register write. Each bit is latched on the rising edge of SCK. When the data has been
shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal
register.
SCK
a5
0
a3
a2
a1
a0
b7
b6
b5
b4
b3
b2
b1
b0
SDI
Address
Data Word
SEN
Figure 15 Serial Interface Register Write
A software reset is carried out by writing to Address “000100” with any value of data, (i.e. Data Word
= XXXXXXXX).
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SERIAL INTERFACE: REGISTER READ-BACK
Figure 16 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus
as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing
address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of
corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge
of SCK). Note that pin SDO is shared with an output pin, OP[9], therefore OEB should always be
held low and the OPD register bit should be set low when register read-back data is expected on this
pin. The next word may be read in to SDI while the previous word is still being output on SDO.
Figure 16 Serial Interface Register Read-back
NORMAL OPERATING MODES
Table 3 below shows the normal operating modes of the device. The MCLK speed can be specified
along with the MCLK:VSMP ratio to achieve the desired sample rate.
NUMBER
OF
CHANNELS
DESCRIPTION
CDS
AVAILABLE
MAXIMUM
SAMPLE
RATE
TIMING REQUIREMENTS
CHANNEL
MODE
SETTINGS
2
1
Two channel
Pixel-by-Pixel
YES
YES
30 MSPS
MCLK max = 60Mhz
MONO = 0
Minimum MCLK:VSMP ratio = 2:1
MCLK max = 45Mhz
TWOCHAN = 1
MONO = 1
One channel
Pixel-by-Pixel
45 MSPS
Minimum MCLK:VSMP ratio = 1:1
TWOCHAN = 0
Table 3 WM8216 Normal Operating Modes
Note: In one channel mode the WM8216 can operate at 60MHz but DNL/INL values cannot
be guaranteed.
Table 4 below shows the different channel mode register settings required to operate the 8216 in 1
and 2 channel modes.
MONO
TWOCHAN
CHAN
MODE DESCRIPTION
0
1
X
0
2-channel
1
1
1
0
0
1
1-channel mode. Odd Channel
1-channel mode. Even Channel
Invalid mode
1
X
Table 4 Sampling Mode Summary
Note: Unused input pins should be connected to AGND.
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DEVICE CONFIGURATION
REGISTER MAP
The following table describes the location of each control bit used to determine the operation of the
WM8216.
ADDRESS
<a5:a0>
DESCRIPTION
DEF
(hex)
03
RW
BIT
b7
b6
0
b5
b4
b3
b2
b1
CDS
b0
000001 (01h) Setup Reg 1
000010 (02h) Setup Reg 2
000011 (03h) Setup Reg 3
000100 (04h) Software Reset
000110 (06h) Reserved
RW
RW
RW
W
0
DEL[1]
0
PGAFS[1]
PGAFS[0]
TWOCHAN
OPD
MONO
INVOP
EN
0
20
DEL[0]
CHAN
RLCDACRNG LOWREFS
0
1F
00
CDSREF [1] CDSREF [0] RLCDAC[3] RLCDAC[2]
RLCDAC[1]
RLCDAC[0]
00
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
0
0
0
0
0
0
0
0
000111 (07h) Setup Reg 5
001000 (08h) Setup Reg 6
001001 (09h) Reserved
00
0
VRXPD
ADCREFPD VRLCDACPD
ADCPD
0
EVENPD
ODDPD
20
0
CLAMPCTRL
RLCEN
0
0
0
0
0
00
0
0
0
0
0
0
0
0
001010 (0Ah) Reserved
00
0
0
0
0
0
0
0
0
0
001011 (0Bh) Reserved
00
0
0
0
0
0
0
0
001100 (0Ch) Reserved
00
0
0
0
0
0
0
0
0
100000 (20h) DAC Value (Odd)
100001 (21h) DAC Value (Even)
100010 (22h) Reserved
80
DACO[7]
DACO[6]
DACO[5]
DACO[4]
DACO[3]
DACO[2]
DACO[1]
DACO[0]
DACE[0]
0
80
DACE[7]
DACE[6]
DACE[5]
DACE[4]
DACE[3]
DACE[2]
DACE[1]
80
1
0
0
0
0
0
0
100011 (23h) DAC Value (Odd&Even)
100100 (24h) PGA Gain LSB (Odd)
100101 (25h) PGA Gain LSB (Even)
100110 (26h) Reserved
80
DACOE[7]
DACOE[6]
DACOE[5]
DACOE[4]
DACOE[3]
DACOE[2]
DACOE[1]
DACOE[0]
PGAO[0]
PGAE[0]
0
00
RW
RW
RW
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
100111 (27h) PGA Gain LSB
(Odd&Even)
00
PGAOE[0]
101000 (28h) PGA Gain MSBs (Odd)
101001 (29h) PGA Gain MSBs (Even)
101010 (2Ah) Reserved
00
00
00
00
RW
RW
RW
W
PGAO[8]
PGAE[8]
0
PGAO[7]
PGAE[7]
0
PGAO[6]
PGAE[6]
0
PGAO[5]
PGAE[5]
0
PGAO[4]
PGAE[4]
0
PGAO[3]
PGAE[3]
0
PGAO[2]
PGAE[2]
0
PGAO[1]
PGAE[1]
0
101011 (2Bh) PGA Gain MSBs
(Odd&Even)
PGAOE[8]
PGAOE[7]
PGAOE[6]
PGAOE[5]
PGAOE[4]
PGAOE[3]
PGAOE[2]
PGAOE[1]
Table 5 Register Map
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REGISTER MAP DESCRIPTION
The following table describes the function of each of the control bits shown in Table 5.
REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
Setup
0
EN
1
Global Enable
Register 1
0 = complete power down,
1 = fully active (individual blocks can be disabled using individual powerdown
bits – see setup register 5).
1
CDS
1
Select correlated double sampling mode:
0 = single ended mode,
1 = CDS mode.
3:2
TWOCHAN /
MONO
10
Sampling mode select
10 = Two channel mode
01 = One channel mode. Input channel selected by CHAN register bit (Reg 3
bit 6), unused channel is powered down.
5:4
PGAFS[1:0]
00
Offsets PGA output to optimise the ADC range for different polarity sensor
output signals. Zero differential PGA input signal gives:
0x = Zero output from the PGA (Output code=511)
10 = Full-scale positive output (OP=1023) - use for negative going video.
NB, Set INVOP=1 if zero differential input should give a zero output
code with negative going video.
11 = Full-scale negative output (OP=0) - use for positive going video
Must be set to 0
7:6
1:0
2
Not Used
Not Used
INVOP
00
00
0
Setup
Register 2
Must be set to 0
Digitally inverts the polarity of output data.
0 = negative going video gives negative going output,
1 = negative-going video gives positive going output data.
3
OPD
0
Output Disable. This works with the OEB pin to control the output pins.
0=Digital outputs enabled, 1=Digital outputs high impedance
OEB (pin)
OPD
OP pins
0
0
1
1
0
1
0
1
Enabled
High Impedance
High Impedance
High impedance
4
LOWREFS
0
Reduces the ADC reference range (2*[VRT-VRB]), thus changing the max/min
input video voltages (ADC ref range/PGA gain).
0= ADC reference range = 2.0V
1= ADC reference range = 1.2V
5
RLCDACRNG
DEL[1:0]
1
Sets the output range of the RLCDAC.
0 = RLCDAC ranges from 0 to AVDD (approximately),
1 = RLCDAC ranges from 0 to VRT (approximately).
7:6
00
Controls the latency from sample to data appearing on output pins
DEL
00
Latency
7 MCLK periods
8 MCLK periods
9 MCLK periods
10 MCLK periods
01
10
11
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REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
Setup
Register 3
3:0
RLCDAC[3:0]
1111
Controls RLCDAC driving VRLC/VBIAS pin to define single ended signal
reference voltage or Reset Level Clamp voltage. See Electrical Characteristics
section for ranges.
5:4
CDSREF[1:0]
01
CDS mode reset timing adjust.
00 = Advance reset sample by 1 MCLK period (relative to default).
01 = Default reset sample position.
10 = Delay reset sample by 1 MCLK period (relative to default)
11 = Delay reset sample by 2 MCLK periods (relative to default)
When MONO=0 this register bit has no effect
Monochrome mode channel select.
6
7
CHAN
0
0
00 = Odd channel select
01 = Even channel select
Must be set to 0
Not Used
Software
Reset
Any write to Software Reset causes all register bits to be reset. It is
recommended that a software reset be performed after a power-up before any
other register writes.
Setup
Register 5
0
1
3
ODDPD
EVENPD
ADCPD
0
0
0
When set powers down odd S/H, PGA
When set powers down even S/H, PGA
When set powers down ADC. Allows reduced power consumption without
powering down the references which have a long time constant when
switching on/off due to the external decoupling capacitors.
When set powers down 4-bit RLCDAC, setting the output to a high impedance
state and allowing an external reference to be driven in on the VRLC/VBIAS
pin.
4
VRLCDACPD
0
5
6
ADCREFPD
VRXPD
0
0
0
When set disables VRT, VRB buffers to allow external references to be used.
When set disables VRX buffer to allow an external reference to be used.
Must be set to 0
7
Not Used
Setup
Register 6
4:0
5
Not Used
RLCEN
00000
1
Must be set to 0
Reset Level Clamp Enable. When set Reset Level Clamping is enabled. The
method of clamping is determined by CLAMPCTRL.
6
7
CLAMPCTRL
0
0 = RLC switch is controlled directly from RSMP input pin:
RSMP = 0: switch is open
RMSP = 1: switch is closed
1 = RLC switch is controlled by logical combination of RSMP and VSMP.
RSMP && VSMP = 0: switch is open
RSMP && VSMP = 1: switch is closed
Must be set to 0
Not Used
0
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REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
00000000
00000000
00000000
DESCRIPTION
Offset DAC
(Odd)
7:0
7:0
7:0
DACO[7:0]
DACE[7:0]
DACOE[7:0]
Odd channel 8-bit offset DAC value (mV) = 255*(DACR[7:0]-127.5)/127.5
Even channel 8-bit offset DAC value (mV) = 255*(DACG[7:0]-127.5)/127.5
Offset DAC
(Even)
Offset DAC
(Odd&Even)
A write to this register location causes both the odd and even offset DAC
registers to be overwritten by the new value
0
PGAO[0]
0
This register bit forms the LSB of the odd channel PGA gain code. PGA gain
is determined by combining this register bit and the 8 MSBs contained in
register address 28 hex.
PGA Gain
LSB
(Odd)
7:1
0
Not used
PGAE[0]
0000000
0
Must be set to 0
This register bit forms the LSB of the even channel PGA gain code. PGA gain
is determined by combining this register bit and the 8 MSBs contained in
register address 29 hex.
PGA Gain
LSB
(Even)
7:1
0
Not used
0000000
0
Must be set to 0
PGAOE[0]
PGA Gain
LSB
Writing a value to this location causes both the odd and even channel PGA
LSB gain values to be overwritten by the new value.
Must be set to 0
7:1
7:0
Not used
0000000
(Odd&Even)
PGA gain
MSBs
PGAO[8:1]
00001101
Bits 8 to 1 of Odd channel PGA gain. Combined with Odd LSB register bit to
form complete PGA gain code. This determines the gain of the Odd channel
PGA according to the equation:
(Odd)
Odd channel PGA gain (V/V) = 0.66 + PGAO[8:0]x7.34/511
PGA gain
MSBs
(Even)
7:0
7:0
PGAE[8:1]
00001101
00000000
Bits 8 to 1 of Even channel PGA gain. Combined with Even LSB register bit to
form complete PGA gain code. This determines the gain of the Even channel
PGA according to the equation:
Even channel PGA gain (V/V) = 0.66 + PGAE[8:0]x7.34/511
PGA gain
MSBs
PGAOE[8:1]
A write to this register location causes both the Odd and Even channel PGA
MSB gain registers to be overwritten by the new value.
(Odd/Even)
Table 6 Register Control Bits
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APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 17 External Components Diagram
RECOMMENDED EXTERNAL COMPONENT VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1
C2
100nF
100nF
100nF
1µF
100nF
100nF
100nF
100nF
10µF
De-coupling for DVDD1.
De-coupling for DVDD2.
C3
De-coupling for AVDD.
C5
Ceramic de-coupling between VRT and VRB (non-polarised).
De-coupling for VRB.
C6
C7
De-coupling for VRX.
C8
De-coupling for VRT.
C9
De-coupling for VRLC.
C10
C11
C12
Reservoir capacitor for DVDD1.
Reservoir capacitor for DVDD2.
Reservoir capacitor for AVDD.
10µF
10µF
Table 7 External Components Descriptions
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PACKAGE DIMENSIONS
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IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
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Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
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Any use of products by the customer for such purposes is at the customer’s own risk.
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ADDRESS:
Wolfson Microelectronics plc
Westfield House
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EH11 2QB
Tel :: +44 (0)131 272 7000
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PD Rev 4.0 March 2007
27
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