WM8521H9GED/RV [WOLFSON]
STEREO DAC WITH INTEGRATED OUTPUT STAGE FOR 2VRMS LINE OUT; 并集成了输出阶段2VRMS线路输出的立体声DAC
| 型号： | WM8521H9GED/RV |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | STEREO DAC WITH INTEGRATED OUTPUT STAGE FOR 2VRMS LINE OUT |
| 文件： | 总20页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8521
w
Stereo DAC With Integrated Output Stage
for 2Vrms LINE OUT
DESCRIPTION
FEATURES
•
Audio Performance
The WM8521 is a 96kHz stereo DAC with an integrated output
op-amp stage, designed to generate a 2.0Vrms output signal
directly, so reducing external component requirements in digital
audio applications.
-
-
DAC SNR 98dB (‘A’ weighted @ 48kHz)
THD -81dB (‘A’ weighted @ 48kHz)
•
•
DAC Sampling Frequency: 8kHz – 96kHz
Pin Selectable Audio Data Interface Format
- I2S, 16-bit Right Justified or 16bit DSP
2.0 Vrms output at 12V or 9V supply
8.2V to 13.2V Analogue, 2.7V to 3.6 Digital Supply
14-pin SOIC Package
WM8521 comes into two variants WM8521HC and WM8521H9
which offers different line drive output capabilities. WM8521HC
outputs 2Vrms at 12V supply, while WM8521H9 outputs
2.0Vrms at 9V supply. WM8521HC/H9 are designed for cost
sensitive consumer digital audio applications requiring 2Vrms
line output.
•
•
•
APPLICATIONS
A 24-bit multi-bit sigma delta DAC is used with oversampling
digital interpolation filters. Digital audio input word lengths from
16-32 bits and sampling rates from 8kHz to 96kHz are
supported.
•
Consumer digital audio applications requiring 2 Vrms output
- DVD Players
- Digital TV
- Digital Set Top Boxes
- A/V Receivers
The audio interface supports I2S, Right Justified and DSP digital
audio formats.
The devices are controlled via a hardware interface which
provides access to features including de-emphasis, mute and
data formats. These devices are pin equivalent and are
available in a 14-pin SOIC package.
BLOCK DIAGRAM
Product Preview, December 2004, Rev 1.3
Copyright 2004 Wolfson Microelectronics plc.
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
WM8521
Product Preview
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM .................................................................................................1
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
ABSOLUTE MAXIMUM RATINGS.........................................................................5
DC ELECTRICAL CHARACTERISTICS ................................................................6
ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY............................................................................................................. 7
MASTER CLOCK TIMING.............................................................................................. 8
DIGITAL AUDIO INTERFACE........................................................................................ 8
DEVICE DESCRIPTION.........................................................................................9
GENERAL INTRODUCTION.......................................................................................... 9
DAC CIRCUIT DESCRIPTION....................................................................................... 9
CLOCKING SCHEMES................................................................................................ 10
DIGITAL AUDIO INTERFACE...................................................................................... 10
AUDIO DATA SAMPLING RATES ............................................................................... 12
HARDWARE CONTROL MODES................................................................................ 13
DIGITAL FILTER CHARACTERISTICS ....................................................................... 15
DAC FILTER RESPONSES ......................................................................................... 15
DIGITAL DE-EMPHASIS CHARACTERISTICS ........................................................... 16
APPLICATIONS INFORMATION .........................................................................17
RECOMMENDED EXTERNAL COMPONENTS........................................................... 17
RECOMMENDED EXTERNAL COMPONENTS VALUES............................................ 17
RECOMMENDED ANALOGUE LOW PASS FILTER................................................... 18
PCB LAYOUT RECOMMENDATIONS......................................................................... 18
PACKAGE DRAWING..........................................................................................19
IMPORTANT NOTICE..........................................................................................20
ADDRESS:................................................................................................................... 20
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WM8521
PIN CONFIGURATION
ORDERING INFORMATION
TEMPERATURE
MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
TEMPERATURE
DEVICE
RANGE
PACKAGE
240oC
WM8521HCED/V
WM8521HCED/RV
-25 to +85oC
14-pin SOIC
MSL1
MSL1
14-pin SOIC
(tape and reel)
240oC
-25 to +85oC
14-pin SOIC
(lead free)
260oC
260oC
WM8521HCGED/V
WM8521HCGED/RV
-25 to +85oC
-25 to +85oC
MSL1
MSL1
14-pin SOIC
(lead free, tape and reel)
240oC
240oC
WM8521H9ED/V
WM8521H9ED/RV
-25 to +85oC
-25 to +85oC
14-pin SOIC
MSL1
MSL1
14-pin SOIC
(tape and reel)
14-pin SOIC
(lead free)
260oC
260oC
WM8521H9GED/V
WM8521H9GED/RV
-25 to +85oC
-25 to +85oC
MSL1
MSL1
14-pin SOIC
(lead free, tape and reel)
Note:
1. Reel quantity = 3,000
2. WM8521H9: 2Vrms output at 9V supply
3. WM8521HC: 2Vrms output at 12V supply
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WM8521
PIN DESCRIPTION
Product Preview
PIN
1
NAME
DGND
TYPE
DESCRIPTION
Supply
Digital Negative supply
Sample rate clock input
Serial audio data input
Bit clock input
2
LRCLK
DIN
Digital input
Digital input
Digital input
Digital input
3
4
BCLK
MUTE
5
Soft mute control, Internal pull down
High Impedance = Automute
High = Mute ON
Low = Mute OFF
6
7
VOUTR
AGND
CAP
Analogue output
Supply
Right channel DAC output
Analogue Negative supply
Analogue internal reference
Analogue Positive supply
8
Analogue output
Supply
9
AVDD
10
11
VOUTL
DEEMPH
Analogue output
Digital input
Left channel DAC output
De-emphasis select, Internal pull down
High = de-emphasis ON
Low = de-emphasis OFF
12
FORMAT
Digital input
Data input format select, Internal pull up
Low = 16-bit right justified or 16bit DSP ‘late’
High = 16-32-bit I2S or 16bit DSP ‘early’
Master clock input
13
14
MCLK
DVDD
Digital input
Supply
Digital Positive supply
Note:
1. Digital input pins have Schmitt trigger input buffers.
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WM8521
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
Analogue Supply Voltage (AVDD)
MIN
-0.3V
MAX
+15V
Digital Supply voltage (DVDD)
Voltage range digital inputs
-0.3V
+4.2V
DGND -0.3V
DVDD +0.3V
50MHz
Master Clock Frequency
Operating temperature range, TA
Storage temperature prior to soldering
Storage temperature after soldering
-25°C
+85°C
30°C max / 85% RH max
-65°C
+150°C
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DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WM8521HC Analogue
AVDD
8.2
12
13.2
V
supply range
WM8521H9 Analogue
supply range
AVDD
8.2
2.7
9
13.2
3.6
V
Digital supply range
Ground
DVDD
3.3
0
V
V
AGND / DGND
WM8521HC Supply current
AVDD = 12V
DVDD = 3.3V
AVDD = 9V
32.0
mA
WM8521H9 Supply current
24.9
23.7
17.9
mA
mA
mA
DVDD = 3.3V
AVDD = 12V
DVDD = 3.3V
AVDD = 9V
WM8521HC Power down
current (note 4)
WM8521H9 Power down
current (note 4)
DVDD = 3.3V
ELECTRICAL CHARACTERISTICS
Test Conditions
WM8521HC: AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise
stated.
WM8521H9: AVDD = 9V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
VIH
0.7 x DVDD
0.1 x DVDD
V
V
V
V
Input HIGH level
0.3 x DVDD
0.9 x DVDD
Output LOW
VOL
VOH
I
OL = 1mA
Output HIGH
IOH = -1mA
Analogue Reference Levels
Reference voltage (CAP)
Potential divider resistance
AVDD/2
50
V
RCAP
VDD to CAP and CAP
to GND
kΩ
DAC Output (Load = 10kΩ. 50pF)
WM8521HC 0dBFs Full scale
output voltage
At DAC outputs
At DAC outputs
2.0
2.0
98
Vrms
Vrms
dB
WM8521H9 0dBFs Full scale
output voltage
2.64 @ 12V
AVDD
SNR (Terminology Note 1,2,3)
SNR (Terminology Note 1,2,3)
SNR (Terminology Note 1,2,3)
A-weighted,
@ fs = 48kHz
A-weighted
95
91
98
95
dB
dB
@ fs = 96kHz
Non ‘A’ weighted @ fs
= 48kHz
THD (Note 3)
1kHz, 0dBFs
1kHz, THD+N @
-60dBFs
-81
98
dB
dB
Dynamic Range (Note 2)
DAC Channel Separation
1kHz, 0dBFs
93
dB
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WM8521
Test Conditions
WM8521HC: AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise
stated.
WM8521H9: AVDD = 9V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Output Levels
Gain Mismatch
Channel-to-channel
1
5
%FSR
Minimum Resistance Load
To midrail or a.c.
coupled
kΩ
Maximum Capacitance Load
Output d.c. Level
220
pF
V
AVDD/2
Power On Reset (POR)
POR Threshold
DVDD
1.64
V
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’
weighted over a 20Hz to 20kHz bandwidth.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use
such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic
specification values.
3. CAP pin decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
4. Digital reset occurs 1.5µs after MCLK is stopped.
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
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MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK Master clock pulse width
high
tMCLKH
tMCLKL
tMCLKY
11
11
ns
ns
ns
MCLK Master clock pulse width
low
MCLK Master clock cycle time
MCLK Duty cycle
28
40:60
1.5
60:40
12
Time from MCLK stopping to
digital reset
µs
DIGITAL AUDIO INTERFACE
t
t
BCL
BCH
BCLK
LRCLK
DIN
t
BCY
t
t
t
LRH
LRSU
DS
t
DH
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK
rising edge
tLRSU
LRCLK hold time from
BCLK rising edge
tLRH
tDS
10
10
10
ns
ns
ns
DIN set-up time to BCLK
rising edge
DIN hold time from BCLK
rising edge
tDH
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WM8521
DEVICE DESCRIPTION
GENERAL INTRODUCTION
The WM8521 is a high performance DAC designed for digital consumer audio applications requiring
a 2Vrms output. The range of features make it ideally suited for use in DVD players, Digital TV,
Digital Set Top Boxes, AV receivers and other consumer audio equipment.
The WM8521 is a complete 2-channel stereo audio digital-to-analogue converter, including digital
interpolation filter, multi-bit sigma delta with dither, switched capacitor multi-bit stereo DAC and
output smoothing filters combined with 2Vrms outputs. It is fully compatible and an ideal partner for a
range of industry standard microprocessors, controllers and DSPs. A novel multi bit sigma-delta DAC
design is used, utilising a 128x oversampling rate, to optimise signal to noise performance and offer
increased clock jitter tolerance.
Control of internal functionality of the device is provided by hardware control (pin programmed).
Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between clock
rates being automatically controlled. Sample rates (fs) from 8kHz to 96kHz are allowed provided the
appropriate system clock is input.
The audio data interface supports 16-bit right justified or 16-, 20-, 24-, 32-bit I2S (Philips left justified,
one bit delayed) interface formats. A 16bit DSP interface is also supported, enhancing the interface
options for the user.
The device is packaged in a small 14-pin SOIC.
DAC CIRCUIT DESCRIPTION
The WM8521 DAC is designed to allow playback of 24-bit PCM audio or similar data with high
resolution and low noise and distortion. Sample rates from 8kHz to 96kHz may be used provided that
the ratio of sample rate (LRCLK) to master clock (MCLK) is maintained at one of the required rates.
The two DACs on the WM8521 are implemented using sigma-delta oversampled conversion
techniques. These require that the PCM samples are digitally filtered and interpolated to generate a
set of samples at a much higher rate than the input rate. This sample stream is then digitally
modulated to generate a digital pulse stream that is then converted to analogue signals in a switched
capacitor DAC. The advantage of this technique is that the DAC is linearised using noise shaping
techniques, allowing the 24-bit resolution to be met using non-critical analogue components. A
further advantage is that the high sample rate at the DAC output means that smoothing filters on the
output of the DAC need only have fairly crude characteristics in order to remove the characteristic
steps, or images on the output of the DAC. To ensure that generation of tones characteristic to
sigma-delta convertors is not a problem, dithering is used in the digital modulator along with a higher
order modulator. The multi-bit switched capacitor technique used in the DAC reduces sensitivity to
clock jitter, and dramatically reduces out of band noise compared to switched current or single bit
techniques used in other implementations.
The voltage on the CAP pin is used as the reference for the DACs. Therefore the amplitude of the
signals at the DAC outputs will scale with the amplitude of the voltage at the CAP pin. An external
reference could be used to drive into the CAP pin if desired, with a value typically of about midrail
ideal for optimum performance. However driven in normal operation, an internal divider will set a
valve of AVDD/2 on the cap pin.
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Typically an external low pass filter circuit will be used to remove residual out of band noise
characteristic of delta sigma converters. However, the advanced multi-bit DAC used in WM8521
produces far less out of band noise than single bit traditional sigma delta DACs, and so in many
applications this filter may be removed, or replaced with a simple RC pole.
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. The external master clock can be applied directly through the MCLK input pin with no
configuration necessary for sample rate selection.
Note that on the WM8521, MCLK is used to derive clocks for the DAC path. The DAC path is
affected by DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a
system where there are a number of possible sources for the reference clock it is recommended that
the clock source with the lowest jitter be used to optimise the performance of the DAC.
The device can be reset by stopping MCLK. In this state the power consumption is substantially
reduced.
DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Three interface
formats are supported:
•
•
•
I2S mode
Right Justified mode
DSP mode
All formats send the MSB first. The data format is selected with the FORMAT pin. When FORMAT is
LOW, right justified data format is selected and word lengths up to 16-bits may be used. If a word
length shorter than 16-bits is used, the unused bits should be padded with zeroes. When the
FORMAT pin is HIGH, I2S format is selected and word length of any value up to 32-bits may be used.
Unless in 16-bit ‘packed’ mode, if a word length shorter than 24-bits is used, the unused bits should
be padded with zeros. If LRCLK is 4 BCLKs or less duration, the 16bit DSP compatible format is
selected. Early and Late clock formats are supported, selected by the state of the FORMAT pin.
I2S MODE INPUT FORMAT
The WM8521 supports word lengths of 16-32 bits in I2S mode.
In I2S mode, the digital audio interface receives data on the DIN input. Audio Data is time multiplexed
with LRCLK indicating whether the left or right channel is present. LRCLK is also used as a timing
reference to indicate the beginning or end of the data words.
25-32 bits: LRCLK must be high for a minimum of data wordlength BCLKs and low for a minimum of
data wordlength BCLKs. The LSBs will be truncated and the most significant 24 bits will be used by
the internal processing.
24 bits: LRCLK must be high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
17-23 bits: Data must be zero padded to 24 bits and LRCLK must be high for a minimum of 24
BCLKs and low for a minimum of 24 BCLKs.
Up to 16 bits: EITHER data must be zero padded to 24 bits and LRCLK must be high for minimum
24 BCLKs and low for 24 BCLKs,
OR data must be zero padded to 16 bits and LRCLK must be high for exactly 16 BCLKs and low for
exactly 16 BCLKs. The device auto-detects this ’16-bit packed’ mode and switches to 16-bit data
length.
Any mark to space ratio on LRCLK is acceptable provided the above requirements are met.
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WM8521
In I2S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK transition.
LRCLK is low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
DIN
1 BCLK
1 BCLK
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1 n
LSB
MSB
LSB
MSB
Figure 3 I2S Mode Timing Diagram
RIGHT JUSTIFIED MODE INPUT FORMAT
The WM8521 supports word lengths of up to 16-bits in right justified mode. If a word length shorter
than 16-bits is used, the unused bits should be padded with zeroes.
In right justified mode, LRCLK must be high for a minimum of 16 BCLKs and low for a minimum of
16 BCLKs. Any mark to space ratio on LRCLK is acceptable provided the above requirement is met.
The digital audio interface receives data on the DIN input. Audio Data is time multiplexed with LRCLK
indicating whether the left or right channel is present. LRCLK is also used as a timing reference to
indicate the beginning or end of the data words.
In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK transition.
LRCLK is high during the left samples and low during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
DIN
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
MSB
MSB
Figure 4 Right Justified Mode Timing Diagram
DSP MODE INPUT FORMAT
A DSP compatible, time division multiplexed format is also supported by the WM8521.
This format is of the type where a ‘synch’ pulse is followed by two data words (left and right) of 16 bit
word length. The ‘synch’ pulse replaces the normal duration LRCLK, and DSP mode is auto-detected
by the shorter than normal duration of the LRCLK. If LRCLK is of 4 BCLK or less duration, the DSP
compatible format is selected. Early and Late clock formats are supported, selected by the state of
the FORMAT pin.
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1/fs
Max 4 BCLKs
LRCLK
BCLK
DIN
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
1
2
15 16
1
2
15 16
1
MSB
LSB
MSB
Input Word Length (16 bits)
Figure 5 DSP ‘Late’ Mode Timing
1 BCLK
1 BCLK
1/fs
Max 4 BCLKs
LRCLK
BCLK
LEFT CHANNEL
RIGHT CHANNEL
2
NO VALID DATA
1
2
15 16
1
15 16
DIN
MSB
LSB
Input Word Length (16 bits)
Figure 6 DSP ‘Early’ Mode Timing
AUDIO DATA SAMPLING RATES
The master clock for WM8521 supports audio sampling rates from 256fs to 768fs, where fs is the
audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz or 96kHz. The master clock is
used to operate the digital filters and the noise shaping circuits.
The WM8521 has a master clock detection circuit that automatically determines the relationship
between the master clock frequency and the sampling rate (to within +/- 32 master clocks). If there is
a greater than 32 clocks error, the master clock defaults to 768fs. The master clock should be
synchronised with LRCLK, although the WM8521 is tolerant of phase differences or jitter on this
clock.
SAMPLING
RATE
MASTER CLOCK FREQUENCY (MHz) (MCLK)
256fs
384fs
512fs
768fs
(LRCLK)
32kHz
8.192
11.2896
12.288
24.576
12.288
16.9344
18.432
36.864
16.384
22.5792
24.576
24.576
33.8688
36.864
44.1kHz
48kHz
96kHz
Unavailable Unavailable
Table 1 Master Clock Frequencies Versus Sampling Rate
Note:
For sample rates down to 8k, scale MCLK accordingly.
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WM8521
HARDWARE CONTROL MODES
The WM8521 is hardware programmable providing the user with options to select input audio data
format, de-emphasis and mute.
MUTE AND AUTO MUTE OPERATION
Pin 5 (MUTE) controls the mute function, or can be used as an output to monitor the state of
the automuted signal.
MUTE PIN
DESCRIPTION
0
1
Normal Operation, MUTE off
Mute DAC channels
Floating
Enable IZD, MUTE becomes an output to indicate when IZD occurs.
Table 2 Mute and Automute Control
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
0.001
0.002
0.003
0.004
0.005
0.006
Time(s)
Figure 7 Application and Release of MUTE
MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio
signal over a few milliseconds. Taking MUTE low again allows data into the filter. Refer to Figure 7.
Therefore if MUTE is tied low then mute is disabled and the automute function is overridden.
If MUTE is floating or connected to a high impedance then the automute function will operate. The
AUTOMUTED internal signal, which is generated by the IZD function, is connected to the MUTE pin
internally via a 10k resistor. This can provide a weak output (10k source impedance) which can be
used to drive external mute circuits. Refer to Figure 8.
The Infinite Zero Detect (IZD) function detects 1024 zero value audio samples applied to both
channels. After such an event, a latch is set whose output is the AUTOMUTED internal signal.
AUTOMUTED will be reset as soon as either channel receives a non-zero input.
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A diagram showing how the various Mute modes interact is shown below in Figure 8.
AUTOMUTED
(Internal Signal)
10k
Ω
MUTE
PIN
SOFTMUTE
(Internal Signal)
Figure 8 Selection Logic for MUTE Modes
INPUT AUDIO FORMAT SELECTION
FORMAT (pin 12) controls the data input format.
FORMAT
INPUT DATA MODE
0
16 bit right justified
16–32 bit I2S
1
Table 3 Input Audio Format Selection
INPUT DSP FORMAT SELECTION
FORMAT
LRCLK DATAWIDTH BCLKS
LRCLK OF 4 BCLK OR LESS DURATION
0
16 bit
16 bit DSP format – ‘late’ mode
(MSB-first, right justified)
1
I2S format up to 24 bit
16 bit DSP format – ‘early’ mode
(Philips serial data protocol)
Table 4 DSP Interface Formats
DE-EMPHASIS CONTROL
DEEMPH (pin 11) is an input control for selection of de-emphasis filtering to be applied.
DEEMPH
DE-EMPHASIS
0
Off
On
1
Table 5 De-emphasis Control
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WM8521
DIGITAL FILTER CHARACTERISTICS
PARAMETER
Passband Edge
SYMBOL
TEST CONDITIONS
-3dB
MIN
TYP
MAX
UNIT
0.487fs
Passband Ripple
f < 0.444fs
f > 0.555fs
±0.05
dB
dB
Stopband Attenuation
-60
Table 6 Digital Filter Characteristics
DAC FILTER RESPONSES
10
0
0
-20
-10
-20
-30
-40
-50
-60
-70
-80
-40
-60
-80
-100
-120
0.4
0.45
0.5
0.55
0.6
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 9 DAC Digital Filter Frequency Response
Figure 10 DAC Digital Filter Transition Band
–44.1,48 and 96kHz
–44.1,48 and 96kHz
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 11 DAC Digital Filter Ripple – 44.1, 48 and 96kHz
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DIGITAL DE-EMPHASIS CHARACTERISTICS
0
1
0.5
0
-2
-4
-0.5
-1
-6
-1.5
-2
-8
-2.5
-3
-10
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Frequency (kHz)
Frequency (kHz)
Figure 12 De-Emphasis Frequency Response (32kHz)
Figure 13 De-Emphasis Error (32KHz)
0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
5
10
15
20
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
Figure 14 De-Emphasis Frequency Response (44.1KHz)
Figure 15 De-Emphasis Error (44.1KHz)
0
1
0.8
0.6
0.4
0.2
0
-2
-4
-6
-0.2
-0.4
-0.6
-0.8
-1
-8
-10
0
5
10
15
20
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
Figure 16 De-Emphasis Frequency Response (48kHz)
Figure 17 De-Emphasis Error (48kHz)
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WM8521
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 18 Recommended External Components
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
SUGGESTED VALUE
DESCRIPTION
C1
C2
10µF
0.1µF
10µF
0.1µF
10µF
0.1µF
10µF
De-coupling for AVDD
De-coupling for AVDD
De-coupling for DVDD
De-coupling for DVDD
C3
C4
C5 and C6
C7
Output AC coupling caps to remove midrail DC level from outputs
Reference de-coupling capacitors for CAP pin
C8
Table 7 External Components Description
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RECOMMENDED ANALOGUE LOW PASS FILTER
AC coupling cap
220
Ω
VOUTR
10nF
10k
Ω
AC coupling cap
220
Ω
VOUTL
10nF
10k
Ω
Figure 19 Recommended 1st Order Low Pass Filter
An external single pole RC filter is recommended (see Figure 19) if the device is driving a wideband
amplifier. However the WM8521 does contain an internal low pass filter which should be adequate in
most applications.
PCB LAYOUT RECOMMENDATIONS
Care should be taken in the layout of the PCB that the WM8521 is to be mounted to. The following
notes will help in this respect:
The VDD supply to the device should be as noise free as possible. This can be accomplished to
a large degree with a 10uF bulk capacitor placed locally to the device and a 0.1uF high frequency
decoupling capacitor placed as close to the VDD pin as possible. It is best to place the 0.1uF
capacitor directly between the VDD and GND pins of the device on the same layer to minimize track
inductance and thus improve device decoupling effectiveness.
The CAP pin should be as noise free as possible. This pin provides the decoupling for the on
chip reference circuits and thus any noise present on this pin will be directly coupled to the device
outputs. In a similar manner to the VDD decoupling described in 1. above, this pin should be
decoupled with a 10uF bulk capacitor local to the device and a 0.1uF capacitor as close to the CAP
pin as possible.
Separate analogue and digital track routing from each other. The device is split into analogue
(pins 5 – 10) and digital (pins 1 – 4 & pins 11 – 14) sections that allow the routing of these signals to
be easily separated. By physically separating analogue and digital signals, crosstalk from the PCB
can be minimized.
Use an unbroken solid GND plane. To achieve best performance from the device, it is advisable
to have either a GND plane layer on a multilayer PCB or to dedicate one side of a 2 layer PCB to be
a GND plane. For double sided implementations it is best to route as many signals as possible on
the device mounted side of the board, with the opposite side acting as a GND plane. The use of a
GND plane greatly reduces any electrical emissions from the PCB and minimizes crosstalk between
signals.
An evaluation board is available for the WM8521 that demonstrates the above techniques and the
excellent performance achievable from the device. This can be ordered or the User manual
downloaded from the Wolfson web site at www.wolfsonmicro.com
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WM8521
PACKAGE DRAWING
DM001.C
D: 14 PIN SOIC 3.9mm Wide Body
e
B
14
8
H
E
1
7
D
L
h x 45o
A1
SEATING PLANE
-C-
α
A
C
0.10 (0.004)
Dimensions
(MM)
Dimensions
(Inches)
Symbols
MIN
MAX
1.75
0.25
0.51
0.25
8.75
4.00
MIN
MAX
A
A1
B
C
D
E
1.35
0.10
0.33
0.19
8.55
3.80
0.0532
0.0040
0.0130
0.0075
0.3367
0.1497
0.0688
0.0098
0.0200
0.0098
0.3444
0.1574
e
1.27 BSC
0.05 BSC
H
h
L
5.80
0.25
0.40
0o
6.20
0.50
1.27
8o
0.2284
0.0099
0.0160
0o
0.2440
0.0196
0.0500
8o
α
REF:
JEDEC.95, MS-012
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical
components in life support devices or systems without the express written approval of an officer of the company. Life
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual
property right of WM covering or relating to any combination, machine, or process in which such products or services might
be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s
approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and
deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
PP Rev 1.3 December 2004
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