WM8523GEFL/RV [WOLFSON]
24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output;
| 型号： | WM8523GEFL/RV |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | 24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output 转换器 |
| 文件： | 总51页 (文件大小：618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8523
w
24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output
DESCRIPTION
FEATURES
•
High performance stereo DAC with ground referenced line
driver
Audio Performance
The WM8523 is a stereo DAC with integral charge pump
and software control interface. This provides 2Vrms line
driver outputs using a single 3.3V power supply rail.
•
−
−
106dB SNR (‘A-weighted’)
-89dB THD @ -1dBFS
The device features ground-referenced outputs and the use
of a DC servo to eliminate the need for line driving coupling
capacitors and effectively eliminate power on pops and
clicks.
•
•
•
•
•
•
•
•
•
•
•
Digital Volume control ranging from -100dB to +12dB
120dB mute attenuation
All common sample rates from 8kHz to 192kHz supported
I2C/SPI compatible and hardware control modes
Data formats: LJ, RJ, I2S, DSP
The device is controlled and configured either via the
I2C/SPI compliant serial control interface or a hardware
control interface.
De-emphasis supported
Maximum 1mV DC offset on Line Outputs
Pop/Click suppressed Power Up/Down Sequencer
AVDD and LINEVDD +3.3V ±10% allowing single supply
20-lead TSSOP or 24-lead QFN packages
Operating temperature range: -40°C to 85°C
The device supports all common audio sampling rates
between 8kHz and 192kHz using all common MCLK fs
rates. Master and Slave modes are available and de-
emphasis is also supported.
APPLICATIONS
The WM8523 has a 3.3V tolerant digital interface, allowing
logic up to 3.3V to be connected.
•
Consumer digital audio applications requiring 2Vrms output
−
−
−
−
−
Set Top Box
Digital TV
DVD Players
Games Consoles
A/V Receivers
The device is available in a 20-lead TSSOP or 24-lead
QFN.
WOLFSON MICROELECTRONICS plc
Production Data, August 2011, Rev 4.1
Copyright ©2011 Wolfson Microelectronics plc
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WM8523
Production Data
BLOCK DIAGRAM
W
WM8523
CONTROL INTERFACE
LEFT
DAC
LINEVOUTL
MCLK
BCLK
LRCLK
DACDAT
DIGITAL
AUDIO
INTERFACE
DIGITAL
FILTERS
RIGHT
DAC
LINEVOUTR
CHARGE PUMP
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WM8523
TABLE OF CONTENTS
DESCRIPTION ................................................................................................................... 1
FEATURES......................................................................................................................... 1
APPLICATIONS ................................................................................................................. 1
BLOCK DIAGRAM ............................................................................................................. 2
TABLE OF CONTENTS ..................................................................................................... 3
PIN CONFIGURATION....................................................................................................... 4
ORDERING INFORMATION .............................................................................................. 4
PIN DESCRIPTION – 20-LEAD TSSOP ............................................................................ 5
PIN DESCRIPTION – 24-LEAD QFN................................................................................. 6
ABSOLUTE MAXIMUM RATINGS..................................................................................... 8
RECOMMENDED OPERATING CONDITIONS ................................................................. 8
ELECTRICAL CHARACTERISTICS .................................................................................. 9
TERMINOLOGY..........................................................................................................................9
POWER CONSUMPTION MEASUREMENTS ..........................................................................10
SIGNAL TIMING REQUIREMENTS................................................................................. 11
SYSTEM CLOCK TIMING .........................................................................................................11
AUDIO INTERFACE TIMING – MASTER MODE ......................................................................11
AUDIO INTERFACE TIMING – SLAVE MODE..........................................................................12
CONTROL INTERFACE TIMING – I2C MODE ..........................................................................13
CONTROL INTERFACE TIMING – SPI MODE .........................................................................14
POWER ON RESET CIRCUIT ..................................................................................................15
DEVICE DESCRIPTION................................................................................................... 17
INTRODUCTION.......................................................................................................................17
SOFTWARE CONTROL INTERFACE.......................................................................................17
DIGITAL AUDIO INTERFACE...................................................................................................21
DIGITAL AUDIO INTERFACE CONTROL.................................................................................24
DIGITAL AUDIO DATA SAMPLING RATES..............................................................................26
DAC FEATURES.......................................................................................................................27
HARDWARE CONTROL INTERFACE......................................................................................32
POWER DOMAINS ...................................................................................................................34
REGISTER MAP............................................................................................................... 35
REGISTER BITS BY ADDRESS ...............................................................................................36
DIGITAL FILTER CHARACTERISTICS........................................................................... 40
DAC FILTER RESPONSES.......................................................................................................41
DIGITAL DE-EMPHASIS CHARACTERISTICS.........................................................................42
APPLICATIONS INFORMATION ..................................................................................... 43
RECOMMENDED EXTERNAL COMPONENTS – 20-LEAD TSSOP.........................................43
RECOMMENDED PCB LAYOUT – 20-LEAD TSSOP ...............................................................44
RECOMMENDED EXTERNAL COMPONENTS – 24-LEAD QFN .............................................45
RECOMMENDED PCB LAYOUT – 24-LEAD QFN....................................................................46
RECOMMENDED ANALOGUE LOW PASS FILTER ................................................................47
RELEVANT APPLICATION NOTES..........................................................................................47
PACKAGE DIMENSIONS – 20-LEAD TSSOP ................................................................ 48
PACKAGE DIMENSIONS – 24-LEAD QFN..................................................................... 49
IMPORTANT NOTICE...................................................................................................... 50
ADDRESS.................................................................................................................................50
REVISION HISTORY........................................................................................................ 51
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PIN CONFIGURATION
24
23
22
21
20
19
DACDAT
LRCLK
1
2
3
4
5
6
18
17
16
15
14
13
NC
LINEVOUTL
LINEVOUTR
NC
BCLK
MCLK
SDOUT/DEEMPH
SDA/AIFMODE0
AVDD
AVDD
7
8
9
10
11
12
20-LEAD TSSOP
24-LEAD QFN (TOP VIEW)
ORDERING INFORMATION
ORDER CODE
WM8523GEDT
WM8523GEDT/R
WM8523GEFL/V
WM8523GEFL/RV
Note:
TEMPERATURE
RANGE
PACKAGE
MOISTURE
SENSITIVITY LEVEL
PEAK SOLDERING
TEMPERATURE
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
20-lead TSSOP
(pb-free)
MSL1
MSL1
MSL3
MSL3
260oC
260oC
260oC
260oC
20-lead TSSOP
(pb-free, tape and reel)
24-lead QFN
(pb-free)
24-lead QFN
(pb-free, tape and reel)
TSSOP Reel quantity = 2000
QFN Reel quantity = 3500
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WM8523
PIN DESCRIPTION – 20-LEAD TSSOP
PIN NO
NAME
LINEVOUTL
CPVOUTN
CPCB
TYPE
DESCRIPTION
1
Analogue Out
Left line output
2
3
Analogue Out
Analogue Out
Supply
Charge Pump negative rail decoupling pin
Charge Pump fly back capacitor pin
Charge Pump ground
4
LINEGND
CPCA
5
Analogue Out
Supply
Charge Pump fly back capacitor pin
Charge Pump supply
6
LINEVDD
ZFLAG
7
Digital Out
Digital In
Zero flag output
8
Digital audio interface data input
Digital audio interface left/right clock
Digital audio interface bit clock
Master clock
DACDAT
LRCLK
9
Digital I/O
Digital I/O
Digital In
10
11
BCLK
MCLK
I2C SOFTWARE
MODE
SPI SOFTWARE
HARDWARE MODE
MODE
SDOUT/
I2C address select
bit[1]
Serial control interface
data output pin
0 – No de-emphasis
1 – De-emphasis
12
13
Digital I/O
DEEMPH
AIFMODE[1:0]
00 – LJ 24 bits
01 – I2S 24 bits
10 – RJ 16 bits
11 – RJ 24 bits
Digital I/O
SDA/
Serial control interface
data input pin
Serial control interface
data input pin
Internal pull-down
AIFMODE0
Digital I/O
SCLK/
Serial control interface
clock input pin
Serial control interface
clock input pin
14
Internal pull-down
AIFMODE1
C¯ ¯S/
I2C address select
bit[0]
Serial control interface
chip select
0 – Mute enabled
1 – Mute disabled
15
16
17
18
19
20
Digital In
M¯ ¯U¯T¯E¯
0 – I2C compatible
mode select
1 – SPI compatible
mode select
Digital In
Tri-level
Z – Hardware mode
CIFMODE
AGND
Supply
Analogue Out
Supply
Analogue ground
Analogue midrail decoupling pin
Analogue supply
VMID
AVDD
Analogue Out
Right line output
LINEVOUTR
Note: Tri-level pins which require the ‘Z’ state to be selected should be left floating (open)
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Production Data
PIN DESCRIPTION – 24-LEAD QFN
PIN NO
NAME
DACDAT
LRCLK
BCLK
TYPE
DESCRIPTION
1
Digital In
Digital audio interface data input
2
3
4
Digital I/O
Digital I/O
Digital In
Digital audio interface left/right clock
Digital audio interface bit clock
Master clock
MCLK
I2C SOFTWARE
MODE
SPI SOFTWARE
HARDWARE MODE
MODE
SDOUT/
I2C address select
bit[1]
Serial control interface
data output pin
0 – No de-emphasis
1 – De-emphasis
5
6
Digital I/O
Digital I/O
DEEMPH
AIFMODE[1:0]
00 – LJ 24 bits
01 – I2S 24 bits
10 – RJ 16 bits
11 – RJ 24 bits
SDA/
Serial control interface
data input pin
Serial control interface
data input pin
AIFMODE0
SCLK/
Serial control interface
clock input pin
Serial control interface
clock input pin
7
Digital I/O
Digital In
AIFMODE1
C¯ ¯S/
I2C address select
bit[0]
Serial control interface
chip select
0 – Mute enabled
1 – Mute disabled
8
M¯ ¯U¯T¯E¯
0 – I2C compatible
mode select
1 – SPI compatible
mode select
Digital In
Tri-level
9
Z – Hardware mode
CIFMODE
AGND
10
11
12
13
14
15
16
17
18
19
20
21
Supply
Supply
Analogue ground
Analogue ground
AGND
Analogue Out
Supply
Analogue midrail decoupling pin
Analogue supply
VMID
AVDD
Supply
Analogue supply
AVDD
No Connect
Analogue Out
Analogue Out
No Connect
Analogue Out
Analogue Out
Supply
No internal connection
Right line output
NC
LINEVOUTR
LINEVOUTL
NC
Left line output
No internal connection
Charge Pump negative rail decoupling pin
Charge Pump fly back capacitor pin
Charge Pump ground
CPVOUTN
CPCB
LINEGND
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WM8523
PIN NO
NAME
CPCA
TYPE
DESCRIPTION
22
Analogue Out
Charge Pump fly back capacitor pin
23
24
Supply
Charge Pump supply
Zero flag output
LINEVDD
ZFLAG
Digital Out
Note: Tri-level pins which require the ‘Z’ state to be selected should be left floating (open)
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during
handling and storage of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
-0.3V
MAX
+4.5V
AVDD, LINEVDD
Voltage range digital inputs
Voltage range analogue inputs
Temperature range, TA
LINEGND -0.3V
AGND -0.3V
-40°C
LINEVDD +0.3V
AVDD +0.3V
+125°C
Storage temperature after soldering
-65°C
+150°C
Notes
1. Analogue grounds must always be within 0.3V of each other.
2. LINEVDD and AVDD must always be within 0.3V of each other.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Analogue supply range
Ground
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVDD, LINEVDD
AGND, LINEGND
2.97
3.3
0
3.63
V
V
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WM8523
ELECTRICAL CHARACTERISTICS
Test Conditions
LINEVDD=AVDD=3.3V, LINEGND=AGND=0V, TA=+25°C, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Output Levels
Output Level
0dBFS
1.89
1
2.1
2.31
Vrms
kΩ
Load Impedance
Load Capacitance
No external RC filter
300
1
pF
With filter shown in
Error! Reference
source not found.
μF
DAC Performance
Signal to Noise Ratio
SNR
RL = 10kΩ
A-weighted
RL = 10kΩ
Un-weighted
RL = 10kΩ
A-weighted
RL = 10kΩ
-1dBFS
100
106
104
104
-89
-86
dB
dB
dB
dB
dB
Dynamic Range
DNR
THD
Total Harmonic Distortion
RL = 10kΩ
0dBFS
AVDD + LINEVDD
PSRR
100Hz
54
54
dB
dB
Power Supply Rejection Ratio
1kHz
20kHz
50
dB
Channel Separation
1kHz
dB
100
20Hz to 20kHz
dB
95
0
System Absolute Phase
Channel Level Matching
Mute Attenuation
degrees
dB
0.1
-120
0
dB
DC Offset at LINEVOUTL and
LINEVOUTR
-1
1
mV
Digital Logic Levels
Input HIGH Level
VIH
VIL
0.7×
V
V
V
V
LINEVDD
Input LOW Level
Output HIGH Level
Output LOW Level
0.3×
LINEVDD
VOH
VOL
0.9×
LINEVDD
IOL = 1mA
0.1×
LINEVDD
IOH = -1mA
Input Capacitance
Input Leakage
10
pF
-0.9
0.9
μA
TERMINOLOGY
1. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum theoretical full scale output signal
and the output with no input signal applied.
2. Total Harmonic Distortion (dB) – THD is the level of the rms value of the sum of harmonic distortion products relative to the
amplitude of the measured output signal.
3. All performance measurements carried out with 20kHz low pass filter, and where noted an A-weighted filter. Failure to use such a
filter will result in higher THD and lower SNR readings than are found in the Electrical Characteristics. The low pass filter removes
out of band noise; although it is not audible it may affect dynamic specification values.
4. Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with mute
applied.
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POWER CONSUMPTION MEASUREMENTS
Test Conditions
LINEVDD=AVDD=3.3V, LINEGND=AGND=0V, TA=+25°C, Slave Mode, quiescent (no signal)
TEST CONDITIONS
IAVDD
(mA)
ILINEVDD
(mA)
TOTAL
(mA)
No clocks applied
SYS_ENA[1:0]=00
Off
0.8
1.1
1.9
fs=48kHz, MCLK=256fs
Standby
SYS_ENA[1:0]=01
SYS_ENA[1:0]=11
0.2
4.8
2.2
6.0
2.4
Playback
10.8
fs=96kHz, MCLK=256fs
Standby
SYS_ENA[1:0]=01
SYS_ENA[1:0]=11
0.2
5.5
2.9
8.5
3.1
Playback
14.0
fs=192kHz, MCLK=128fs
Standby
SYS_ENA[1:0]=01
SYS_ENA[1:0]=11
0.2
5.5
2.9
8.5
3.1
Playback
14.0
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WM8523
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 1 System Clock Timing Requirements
Test Conditions
LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25°C
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Master Clock Timing Information
MCLK cycle time
tMCLKY
tMCLKH
tMCLKL
27
11
500
ns
ns
ns
%
MCLK high time
MCLK low time
11
MCLK duty cycle (tMCLKH/tMCLKL)
40:60
60:40
AUDIO INTERFACE TIMING – MASTER MODE
Figure 2 Master Mode Digital Audio Data Timing
Test Conditions
LINEVDD=AVDD=2.97~3.63, LINEGND=AGND=0V, TA=+25°C, Master Mode
PARAMETER
SYMBOL
MIN
TYP
MAX
16
UNIT
Audio Data Input Timing Information
LRCLK propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time to BCLK falling edge
tDL
4
ns
ns
ns
tDST
tDHT
22
25
Table 1 Master Mode Audio Interface Timing
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AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25°C, Slave Mode
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
27
11
11
7
ns
ns
ns
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DACDAT hold time from LRCLK rising edge
DACDAT set-up time to BCLK rising edge
5
5
tDS
7
Table 2 Slave Mode Audio Interface Timing
Note:
BCLK period should always be greater than or equal to MCLK period.
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WM8523
CONTROL INTERFACE TIMING – I2C MODE
I2C mode is selected by driving the CIFMODE pin low.
Figure 4 Control Interface Timing – I2C Control Mode
Test Conditions
LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25°C
PARAMETER
Program Register Input Information
SCLK Frequency
SYMBOL
MIN
TYP
MAX
UNIT
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Low Pulse-Width
t1
t2
t3
t4
t5
t6
t7
t8
t9
100
100
600
600
100
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
SDA, SCLK Rise Time
300
300
SDA, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
600
2
900
8
Pulse width of spikes that will be suppressed
Table 3 Control Interface Timing – I2C Control Mode
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CONTROL INTERFACE TIMING – SPI MODE
SPI mode is selected by connecting the CIFMODE pin high.
Figure 5 Control Interface Timing – SPI Control Mode (Read Cycle)
Test Conditions
LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25°C
PARAMETER
Program Register Input Information
SCLK rising edge to CSB falling edge
SCLK falling edge to CSB rising edge
SCLK pulse cycle time
SYMBOL
MIN
TYP
MAX
UNIT
tCSU
tCHO
tSCY
tSCL
tSCH
tDSU
tDHO
tDL
40
40
ns
ns
ns
ns
ns
ns
ns
ns
160
64
SCLK pulse width low
SCLK pulse width high
64
SDA to SCLK set-up time
20
SDA to SCLK hold time
40
SDOUT propagation delay from SCLK falling
edge
5
8
Pulse width of spikes that will be suppressed
tps
2
ns
Table 4 Control Interface Timing –SPI Control Mode
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WM8523
POWER ON RESET CIRCUIT
Figure 6 Internal Power on Reset Circuit Schematic
The WM8523 includes an internal Power-On-Reset circuit, as shown in Figure 6, which is used to reset
the DAC digital logic into a default state after power up. The POR circuit is powered by AVDD and has
as its inputs VMID and LINEVDD. It asserts POR low if VMID or LINEVDD are below a minimum
threshold.
Figure 7 Typical Power Timing Requirements
Figure 7 shows a typical power-up sequence where LINEVDD comes up with AVDD. When AVDD goes
above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee POR is asserted
low and the chip is held in reset. In this condition, all writes to the control interface are ignored. After
VMID rises to Vpord_hi and AVDD rises to Vpora_hi, POR is released high and all registers are in their default
state and writes to the control interface may take place.
On power down, PORB is asserted low whenever LINEVDD or AVDD drop below the minimum threshold
Vpora_low
.
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Test Conditions
LINEVDD = AVDD = 3.3V AGND = LINEGND = 0V, TA = +25oC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply Input Timing Information
VDD level to POR defined
(LINEVDD/AVDD rising)
Vpora
Measured from LINEGND
Measured from LINEGND
Measured from LINEGND
Measured from LINEGND
158
0.8
mV
V
VDD level to POR rising edge
(VMID rising)
Vpord_hi
Vpora_hi
Vpora_lo
0.63
1.44
0.96
1
VDD level to POR rising edge
(LINEVDD/AVDD rising)
1.8
2.18
1.97
V
VDD level to POR falling edge
(LINEVDD/AVDD falling)
1.46
V
Table 5 Power on Reset
Note: All values are simulated results
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WM8523
DEVICE DESCRIPTION
INTRODUCTION
The WM8523 provides high fidelity, 2Vrms ground referenced stereo line output from a single supply line
with minimal external components. The integrated DC servo eliminates the requirement for external
mute circuitry by minimising DC transients at the output during power up/down. The device is well-suited
to both stereo and multi-channel systems.
The device supports all common audio sampling rates between 8kHz and 192kHz using common MCLK
fs rates. Master and slave modes are available.
The WM8523 supports both hardware and software control modes.
In hardware control mode, the digital audio interface format is switchable between 16 to 24bits LJ, RJ
and I2S. Mute and de-emphasis control pins are also available.
In software control modes the digital audio interface is highly programmable, with four control interface
addresses to allow multiple WM8523 devices to be configured independently.
SOFTWARE CONTROL INTERFACE
Software Control Mode is selected by logic 1 or 0 on the CIFMODE pin. The logic level is referenced to
the LINEVDD power domain. When software mode is selected, the associated multi-function control
pins are defined as described in Table 6.
PIN NAME
SDOUT
PIN NUMBER
DESCRIPTION
TSSOP
QFN
12
5
I2C Mode - Device Address[1]
SPI Mode - Serial Data Output
Serial Data Input
SDA
SCLK
C¯ ¯S
13
14
15
6
7
8
Serial Data Clock
I2C Mode - Device Address[0]
SPI Mode - Chip Select
Control Interface Mode
0 = I2C Mode
CIFMODE
16
9
1 = SPI Mode
Z = Hardware Mode
Table 6 Software Control Pin Configuration
In software control mode, the WM8523 is controlled by writing to its control registers. Readback is
available for all registers, including device ID and power management status bits. The control interface
can operate as an I2C or SPI control interface: register read-back is provided on the bi-directional pin
SDA in I2C mode, and on the SDOUT pin in SPI mode. The WM8523 software control interface is
supplied by the LINEVDD power domain.
The available software control interface modes are summarised as follows:
.
.
I2C mode uses pins SCLK and SDA.
SPI mode uses pins C¯ ¯S, SCLK and SDA and SDOUT.
I2C mode is selected by setting the CIFMODE pin to logic 0. When CIFMODE is set to logic 1, SPI mode
is selected.
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I2C CONTROL MODE
In I2C mode, the WM8523 is a slave device on the control interface; SCLK is a clock input, while SDA is
a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same
interface, the WM8523 transmits logic 1 by tri-stating the SDA pin, rather than pulling it high. An external
pull-up resistor is required to pull the SDA line high so that the logic 1 can be recognised by the master.
In order to allow many devices to share a single I2C control bus, every device on the bus has a unique 7-
bit device address (this is not the same as the 8-bit address of each register in the WM8523). The
device address is determined by the logic level on the SDOUT and C¯ ¯S pins as shown in Table 7. The
LSB of the device address is the R/¯W¯ bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”.
SDOUT
C¯ ¯S
DEVICE ADDRESS
ADDR1
ADDR0
0
0
1
1
0
1
0
1
0011 0100 (34h)
0011 0110 (36h)
0011 1100 (3Ch)
0011 1110 (3Eh)
Table 7 Control Interface Device Address Selection
The WM8523 operates as an I2C slave device only. The controller indicates the start of data transfer
with a high to low transition on SDA while SCLK remains high. This indicates that a device address,
register address and data will follow. All devices on the I2C bus respond to the start condition and shift in
the next eight bits on SDA (7-bit device address + Read/Write bit, MSB first). If the device address
received matches the device address of the WM8523, then the WM8523 responds by pulling SDA low on
the next clock pulse (ACK). If the device address is not recognised or the R/¯W¯ bit is ‘1’ when operating
in write only mode, the WM8523 returns to the idle condition and waits for a new start condition and valid
address.
If the device address matches the device address of the WM8523, the data transfer continues as
described below. The controller indicates the end of data transfer with a low to high transition on SDA
while SCLK remains high. After receiving a complete address and data sequence the WM8523 returns
to the idle state and waits for another start condition. If a start or stop condition is detected out of
sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns to
the idle condition.
The WM8523 supports the following read and write operations:
•
•
Single write
Single read
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The sequence of signals associated with a single register write operation is illustrated in Figure 8.
Figure 8 Control Interface I2C Register Write
The sequence of signals associated with a single register read operation is illustrated in Figure 9.
Figure 9 Control Interface I2C Register Read
Figure 10 Single Register Write to Specified Address
Figure 11 Single Register Read from Specified Address
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SPI CONTROL MODE
The WM8523 can also be controlled by writing to registers through a SPI control interface. A control
word consists of 24 bits. The first bit is the read/write bit (R/¯W¯ ), which is followed by 7 address bits (A6
to A0) that determine which control register is accessed. The remaining 16 bits (B15 to B0) are data bits,
corresponding to the 16 bits in each control register.
Volume update registers R06h and R07h are unavailable in SPI control mode. To use volume update in
software control mode, I2C mode must be used.
In SPI mode, every rising edge of SCLK clocks in one data bit from the SDA pin. A rising edge on C¯ ¯S
latches in a complete control word consisting of the last 24 bits.
The SPI mode write operation protocol is illustrated in Figure 12.
Figure 12 SPI Control Interface – write operation
In Write operations (R/¯W¯ =0), all SDA bits are driven by the controlling device.
In Read operations (R/¯W¯ =1), the SDA pin is ignored following receipt of the valid register address. The
data bits are output by the WM8523 on the SDOUT pin.
The SPI mode read operation protocol is illustrated in Figure 13.
Figure 13 SPI Control Interface – read operation
REGISTER RESET
Any write to register R0 (00h) will reset the WM8523. All register bits are reset to their default values.
DEVICE ID AND REVISION
Reading from register R0 (00h) returns the device ID. Reading from register R1 returns the device
revision number.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R0
DEVICE_ID
00h
15:0 DEVICE_ID
[15:0]
10000101
00100011
Device ID
A read of this register will return the device
ID, 0x8523.
R1
2:0
CHIP_REV
[2:0]
N/A
Device Revision
REVISION
01h
A read of this register will return the device
revision number. This number is
sequentially incremented if the device
design is updated.
Table 8 Device ID and Revision Number
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DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting audio data to the WM8523. The digital audio interface
uses three pins:
•
•
•
DACDAT: DAC data input
LRCLK: Left/Right data alignment clock
BCLK: Bit clock, for synchronisation
In software control mode, all interface data formats and modes of operation can be selected. In
hardware control mode, only a subset of formats and modes are supported – see the Hardware Interface
Control section on page 32 for details.
MASTER AND SLAVE MODE OPERATION
The WM8523 digital audio interface can operate as a master or as a slave as shown in Figure 14 and
Figure 15.
Figure 14 Slave Mode
Figure 15 Master Mode
INTERFACE FORMATS
The WM8523 supports five different audio data formats:
•
•
•
•
•
Left justified
Right justified
I2S
DSP Mode A
DSP Mode B
PCM operation is supported using the DSP mode. All seven of these modes are MSB first. They are
described in Audio Data Formats on page 22. Refer to the “Electrical Characteristics” section for timing
information. Refer to Table 10 for interface control format register settings.
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AUDIO DATA FORMATS
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition.
All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample
rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 16 Right Justified Audio Interface (assuming n-bit word length)
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency
and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 17 Left Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The
other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and
sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the
next.
Figure 18 I2S Justified Audio Interface (assuming n-bit word length)
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In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of
BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRCLK output will resemble the frame pulse shown in Figure 19 and Figure
20. In device slave mode, Figure 21 and Figure 22, it is possible to use any length of frame pulse less
than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the
rising edge of the next frame pulse.
Figure 19 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master)
Figure 20 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master)
Figure 21 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave)
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Figure 22 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave)
DIGITAL AUDIO INTERFACE CONTROL
The control of the audio interface in software mode is achieved by register write. Dynamically changing
the audio data format may cause erroneous operation and is not recommended.
Digital audio data is transferred to the WM8523 via the digital audio interface. The DAC operates in
master or slave mode.
The DAC audio interface requires left/right frame clock (LRCLK) and bit clock (BCLK). These can be
supplied externally (slave mode) or they can be generated internally (master mode). Selection of master
and slave mode is achieved by setting AIF_MSTR bit in Register 3.
The frequency of LRCLK in master mode is dependent upon the DAC master clock frequency and the
AIF_SR[2:0] bits. The frequency of BCLK in master mode can be selected by AIF_BCLKDIV[2:0]. In
slave mode, the MCLK to LRCLK ratio can be auto-detected or set manually using the AIF_SR[2:0] bits.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R3
AIF_CTRL1
03h
7
AIF_MSTR
0
Master/Slave Select
0 = Slave
1 = Master
R4
2:0
AIF_SR[2:0
000
MCLK:LRCLK Ratio
000 = Auto detect
001 = 128fs
AIF_CTRL2
04h
010 = 192fs
011 = 256fs
100 = 384fs
101 = 512fs
110 = 768fs
111 = 1152fs
5:3
AIF_BCLK
DIV[2:0]
000
BCLK Divider Control (Master Mode)
000 = MCLK/4
001 = MCLK/8
010 = 32fs
011 = 64fs
100 = 128fs
101 - 111 reserved
Table 9 DAC Clocking Mode Control
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Interface timing is such that the input data and left/right clock are sampled on the rising edge of BCLK.
By setting the appropriate BCLK and LRCLK polarity bits, the WM8523 DAC can sample data on the
opposite clock edges.
The control of audio interface formats and clock polarities is summarised in Table 10.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R3
AIF_CTRL1
03h
1:0
AIF_FMT
10
Audio Data Interface Format
00 = Right justified
01 = Left justified
10 = I2S format
11 = DSP mode
2
Reserved
AIF_WL
0
Reserved
4:3
10
Audio Data Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
5
AIF_BCLK_
INV
0
BCLK Inversion Control
Slave mode:
0 = use rising edge
1 = use falling edge
Master mode:
0 = BCLK normal
1 = BCLK inverted
LRCLK Inversion Control
0 = normal polarity
1 = inverted polarity
When AIF_FMT[2:0]=011 (DSP Mode):
0 = mode A (2nd clock)
1 = mode B (1st clock)
6
AIF_LRCLK
_INV
0
Table 10 Audio Interface Control
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DIGITAL AUDIO DATA SAMPLING RATES
The external master clock is applied directly to the MCLK input pin. In a system where there are a
number of possible sources for the reference clock, it is recommended that the clock source with the
lowest jitter be used for the master clock to optimise the performance of the WM8523.
In slave mode the WM8523 has a detection circuit that automatically determines the relationship
between the master clock frequency (MCLK) and the sampling rate (LRCLK), to within ±32 system clock
periods. The MCLK must be synchronised with the LRCLK, although the device is tolerant of phase
variations or jitter on the MCLK.
If the device is configured in slave mode using auto-detect or in hardware mode, and during sample rate
change the ratio between MCLK and LRCLK varies more than once within 1026 LRCLK periods, then it is
recommended that the device be taken into the standby state or the off state before the sample rate
change and held in standby until the sample rate change is complete. This will ensure correct operation
of the detection circuit on the return to the enabled state. For details on the standby state, please refer to
the Software Control Interface (software mode, page 17) and Power Up and Down Control In Hardware
Mode section of the datasheet (hardware mode, on page 33).
The DAC supports MCLK to LRCLK ratios of 128fs to 1152fs and sampling rates of 8kHz to 192kHz,
provided the internal signal processing of the DAC is programmed to operate at the correct rate.
Table 11 shows typical master clock frequencies and sampling rates supported by the WM8523 DAC.
MASTER CLOCK FREQUENCY (MHz)
SAMPLING
RATE LRCLK
128fs
Unavailable
Unavailable
Unavailable
Unavailable
11.2896
192fs
Unavailable
Unavailable
Unavailable
Unavailable
16.9344
256fs
2.048
384fs
3.072
512fs
4.096
768fs
6.144
1152fs
9.216
8kHz
32kHz
8.192
12.288
16.384
24.576
36.864
44.1kHz
48kHz
11.2896
12.288
16.9344
18.432
22.5792
33.8688
Unavailable
Unavailable
Unavailable
Unavailable
Unavailable
Unavailable
24.576
36.864
88.2kHz
96kHz
22.5792
24.576
33.8688
36.864
Unavailable
Unavailable
Unavailable
Unavailable
Unavailable
Unavailable
Unavailable
Unavailable
12.288
18.432
176.4kHz
192kHz
22.5792
33.8688
Unavailable
Unavailable
Unavailable
Unavailable
24.576
36.864
Table 11 MCLK Frequencies and Audio Sample Rates
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DAC FEATURES
SYSTEM ENABLE
The WM8523 includes a number of enable and disable mechanisms to allow the device to be powered
on and off in a pop-free manner. The SYS_ENA[1:0] control bits enable the DAC and analogue paths.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2
PSCTRL1
02h
1:0
SYS_
00
System Power Control
ENA[1:0]
00 = Off
01 = Power down
10 = Power up and mute
11 = Power up and unmute
Table 12 System Enable Control
Note: MCLK must be present at all times when using the SYS_ENA[1:0] bits. If MCLK is stopped at any
point the device will power down to the ‘off’ state, but all register settings will remain. Restarting MCLK
will start the device internal power sequence and the device will return to the power state set by the
SYS_ENA[1:0] bits.
The power up and power down sequences are summarised in Figure 23. There is no requirement to
manually cycle the device through the sequence via register writes, as the device will always
automatically step through each stage in the sequence.
Power Up
When SYS_ENA[1:0]=00, the internal clocks are stopped and all analogue and digital blocks are
disabled for maximum power saving. The device starts up in this state in software mode. Setting
SYS_ENA[1:0]=01 enables the internal charge pump and required control circuitry, but the signal path
remains powered down. When SYS_ENA[1:0]=10 all blocks are powered up sequentially and full system
configuration is achieved. Once this is complete, the device is ready to pass audio but is muted. Setting
SYS_ENA[1:0]=11 releases the mute and audio playback begins.
Power Down
When SYS_ENA[1:0]=11 the device is powered up and passing audio. Changing SYS_ENA[1:0]=10
applies a digital softmute to the output. Setting SYS_ENA[1:0]=01 sequentially powers down all circuit
blocks but leaves the charge pump and required control circuitry enabled. This can be considered the
low-power standby state. Finally, setting SYS_ENA[1:0]=00 will disable all circuit blocks including the
charge pump, and full system initialisation will be required to restart the device.
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Figure 23 SYS_ENA[1:0] Power Up and Down Sequences
DIGITAL VOLUME CONTROL
The WM8523 DAC includes digital volume control, allowing the digital gain to be adjusted between
−100dB and +12dB in 0.25dB steps. Volume update bits allow the user to write both left and right
channel volume changes before the volume is updated. Digital volume control is only available in I2C
mode.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
DAC Digital Volume
R6
DAC_GAINL
06h
8:0
DACL
110001000
_VOL[8:0]
0 0000 0000 = −100dB
0 0000 0001 = −99.75dB
0 0000 0010 = −99.5dB
…0.25dB steps
R7
DAC_GAINR
07h
8:0
9
DACR
1 1001 0000 = 0dB
_VOL[8:0]
…0.25dB steps
1 1011 1110 = +11.75dB
1 11XX XXXX = +12dB
DAC Digital Volume Update
R6
DAC_GAINL
06h
DACL_VU
DACR_VU
0
0
0 = Latch DAC volume setting into
Register Map but do not update volume
1 = Latch DAC volume setting into
Register Map and update left and right
channels simultaneously
R7
DAC_GAINR
07h
9
Table 13 DAC Digital Volume Control
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VOLUME CHANGE MODES
Volume can be adjusted by step change (either using zero cross or not) or by soft ramp. The volume
change mode is controlled by the DAC_VOL_DOWN_RAMP and DAC_VOL_UP_RAMP bits in R5:
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5
DAC_CTRL3
05h
0
DAC_VOL
_DOWN_
RAMP
1
DAC Digital Volume Decrease Control
0 = apply volume decreases instantly (step)
1 = ramp volume decreases
1
DAC_VOL
_UP_
0
DAC Digital Volume Increase Control
0 = apply volume increases instantly (step)
1 = ramp volume increases
RAMP
Table 14 Volume Ramp Control
Figure 24 illustrates the effect of the volume ramp:
Figure 24 Volume Ramp Functionality
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Ramp Volume Changes
If ramp volume changes are selected, the ramp rate is dependent upon the sampling rate. The ramp
rates for common audio sample rates are shown in Table 15.
SAMPLE RATE FOR DAC (kHz)
GAIN RAMP RATE
(ms/dB)
1
8
32
0.25
0.18
0.17
0.1
44.1
48
88.2
96
0.08
0.05
0.04
176.4
192
Table 15 Volume Ramp Rate
For example, when using a sample rate of 48kHz, the time taken for a volume change from an initial
setting of 0dB to -20dB is calculated as follows:
Volume Change (dB) x Volume Ramp Rate (ms/dB) = 20 x 0.17 = 3.4ms
Zero cross is not used when ramping. The volume level in the DAC is set by the user in 0.25dB
increments, but during the volume ramp increments of 0.125dB are actually used. This step size is
inaudible and means there is no requirement to wait until a zero crossing occurs. Another benefit of not
using zero cross when ramping is that predictable ramp times are produced – there is no signal
dependency on the ramp time.
Step Volume Changes and Zero Cross
The step volume control includes optional zero cross functionality. When zero cross is enabled, by
setting DAC_ZCEN=1, volume changes are not applied until the signal crosses zero so no discontinuity
is seen in the output signal. Zero cross helps to prevent pop and click noise when changing volume
settings and is therefore recommended if using step volume changes.
The zero cross function includes a timeout which forces volume changes if a zero cross event does not
occur. The timeout period is 14400 samples, equivalent to 300ms at 48kHz sample rate.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5
DAC_CTRL3
05h
4
DAC_
ZCEN
0
Zero Cross Enable
0 = Do not use zero cross
1 = Use zero cross
Table 16 Zero Cross Control
Table 17 gives a summary of the volume mode settings and their effect.
DAC_VOL_
DAC_VOL_
DAC_ZCEN
VOLUME CHANGE
UP
VOLUME CHANGE
DOWN
UP_RAMP
DOWN_RAMP
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
Step, no zero cross
Step, no zero cross
Ramp
Step, no zero cross
Ramp
Step, no zero cross
Ramp
Ramp
Step, use zero cross Step, use zero cross
Step, use zero cross
Ramp
Ramp
Step, use zero cross
Ramp
Ramp
Table 17 Volume Change Summary
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MUTE
A digital mute can be applied to left and right channels independently.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5
DAC_CTRL3
05h
2
DACL_
MUTE
0
Left DAC Mute
0 = Normal operation
1 = Mute
R5
3
DACR_
MUTE
0
Right DAC Mute
0 = Normal operation
1 = Mute
DAC_CTRL3
05h
Table 18 DAC Mute Control
The DAC mute function in software mode is controlled by the register settings DAC_VOL_UP_RAMP,
DAC_VOL_DOWN_RAMP and DAC_ZCEN as described in Table 17.
DIGITAL MONOMIX CONTROL
The DAC can be set to output a range of mono and stereo options using DAC_OP_MUX[1:0].
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R4
AIF_CTRL2
04h
7:6
DAC_OP_
MUX[1:0]
00
DAC Digital Monomix
00 = Stereo (Normal Operation)
01 = Mono (Left data to DACR)
10 = Mono (Right data to DACL)
11 = Digital Monomix, (L+R)/2
Table 19 Digital Monomix Control
DE-EMPHASIS
A digital de-emphasis filter may be applied to the DAC output when the sampling frequency is 44.1kHz.
Operation at 48kHz and 32kHz is also possible, but with an increase in the error from the ideal response.
Details of the de-emphasis filter characteristic for 32kHz, 44.1kHz and 48kHz can be seen in Figure 31 to
Figure 36.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R3
AIF_CTRL1
03h
6
DAC
0
DAC De-emphasis
_DEEMP
0 = No de-emphasis
1 = Apply de-emphasis
Table 20 De-emphasis Control
ZERO DETECT
The infinite zero detect allows the user to select the number of zero samples received before the ZFLAG
pin is asserted high, as described in Table 21.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8
ZERO_DETECT
08h
0
ZD_
0
Zero Detect Count Control
0 = 1024
COUNT
1 = 2048
Table 21 Zero Detect Control
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HARDWARE CONTROL INTERFACE
The WM8523 can be controlled in hardware mode or in software modes. In hardware mode, the device
is configured according to logic levels applied to hardware pins.
Hardware control mode is selected by leaving CIFMODE pin open-circuit (high-impedance). When
hardware mode is selected, the associated multi-function control pins are defined as described in Table
22.
PIN NAME
PIN NAME
PIN NUMBER
DESCRIPTION
TSSOP
QFN
ZFLAG
7
24
Zero Flag Output
0 = Normal operation
1 = Infinite zero detect is triggered or mute is applied
De-emphasis Filter Select
0 = Filter disabled
DEEMPH
12
5
1 = Filter enabled
AIFMODE0
AIFMODE1
M¯ ¯U¯T¯E¯
13
14
15
6
7
8
AIFMODE1
AIFMODE0
FORMAT
0
0
1
0
1
24-bit Left Justified
24-bit I2S
0
1
16-bit Right Justified
24-bit Right Justified
1
Mute Control
0 = Mute
1 = Normal operation
Control Interface Mode
0 = I2C Mode
CIFMODE
16
9
1 = SPI Mode
Z = Hardware Mode
Table 22 Hardware Control Pin Configuration
DE-EMPHASIS
A digital de-emphasis filter may be applied to the DAC output when the sampling frequency is 44.1kHz.
Operation at 48kHz and 32kHz is also possible, but with an increase in the error from the ideal response.
Details of the de-emphasis filter characteristic for 32kHz, 44.1kHz and 48kHz can be seen in Figure 31 to
Figure 36.
MUTE
In hardware mode, the M¯ ¯U¯T¯E¯ pin controls the DAC mute to both left and right channels. When the mute
is asserted a softmute is applied to ramp the signal down, with the ramp rate related to the sample rate
as defined in Table 15 on page 30. Once mute is achieved, the ZFLAG is asserted. When the mute is
de-asserted the signal returns to full scale in one step and the ZFLAG is de-asserted.
ZERO DETECT
The zero detect function in hardware mode will assert the ZFLAG pin high when 1024 zero count
samples are input to the digital audio interface. Additionally, the ZFLAG is asserted when the device is
muted using the M¯ ¯U¯T¯E¯ pin and also until the device comes out of reset.
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POWER UP AND DOWN CONTROL IN HARDWARE MODE
In hardware mode the MCLK, BCLK and M¯ ¯U¯T¯E¯ pins are monitored to control how the device powers up
or down, and this is summarised in Figure 25 below.
Figure 25 Hardware Power Sequence Diagram
Off to Enable
To power up the device to enabled, start MCLK and BCLK and set M¯ ¯U¯T¯E¯ = 1.
Off to Standby
To power up the device to standby, start MCLK and BCLK and set M¯ ¯U¯T¯E¯ = 0. Once the device is in
standby mode, BCLK can be disabled and the device will remain in standby mode.
Standby to Enable
To transition from the standby state to the enabled state, set the M¯ ¯U¯T¯E¯ pin to logic 1 and start BCLK.
Enable to Standby
To power down to a standby state leaving the charge pump running, either set the M¯ ¯U¯T¯E¯ pin to logic 0 or
stop BCLK. MCLK must continue to run in these situations. The device will automatically mute and
power down quietly in either case.
Note: It is recommended that the device is placed in standby mode before sample rate change if the sample rate changes more than once
in 1026 LRCLK periods, as detailed in Digital Audio Data Sampling Rates on page 26.
Enable to Off
To power down the device completely, stop MCLK at any time. It is recommended that the device is
placed into standby mode as described above before stopping MCLK to allow a quiet shutdown.
For the timing of the off state to enabled state transition (power on to audio out timing), and the enabled
state to standby state transition (the shutdown timing), please refer to WTN0302.
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POWER DOMAINS
Figure 26 Power Domain Diagram
Power Domain
Name
Blocks Using
This Domain
Domain Description
Analogue Supply
Analogue Supply
DAC Power Supplies
3.3V ± 10%
AVDD
Line Driver
DAC
DC Servo
3.3V ± 10%
LINEVDD
Charge Pump
Digital LDO
Digital Pad buffers
Internally Generated Power Supplies and References
1.65V ± 10%
-3.3V ± 10%
VMID
DAC, LDO
Line Driver
Ext decoupled resistor string
CPVOUTN
Charge pump generated voltage
Table 23 Power Domains
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REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8523 can be configured using the Control Interface. All
unused bits should be set to '0' and access to unlisted registers should be avoided.
REG
NAME
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DEFAULT
DEVICE_ID /
SW RESET
R0 (0h)
CHIP_ID[15:0]
8523h
R1 (1h)
R2 (2h)
R3 (3h)
R4 (4h)
REVISION
PSCTRL1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHIP_REV[2:0]
0000h
0000h
1812h
0000h
0
0
SYS_ENA[1:0]
AIF_FMT[1:0]
AIF_
LRCLK_
INV
AIF_
BCLK_
INV
DAC_
AIF_
AIF_CTRL1
AIF_CTRL2
AIF_WL[1:0]
DEEMP
MSTR
0
0
DAC_OP_MUX[1:0]
AIF_BCLKDIV[2:0]
AIF_SR[2:0]
DAC_
DAC_
VOL_
DACR_
MUTE
DACL_
MUTE
VOL_
UP_
R5 (5h)
DAC_CTRL3
0
0
0
0
0
0
0
0
0
0
DAC_ZC
0001h
DOWN_
RAMP
RAMP
DACL_
VU
R6 (6h)
R7 (7h)
DAC_GAINL
DAC_GAINR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DACL_VOL[8:0]
DACR_VOL[8:0]
0
0190h
0190h
0000h
DACR_
VU
ZD_
R8 (8h) ZERO_DETECT
0
0
0
0
0
0
0
0
COUNT
Table 24 Register Map
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Production Data
REGISTER BITS BY ADDRESS
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R0 (00h)
DEVICE_ID/
SW RESET
15:0
CHIP_ID[15:0] 1000_0101_0010_0011 Read this register to obtain Device ID in hex
Page 20
Write any value to this register to reset all
register values to default.
Register 00h DEVICE_ID / SW RESET
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Device Revision Number
REFER TO
R1 (01h)
2:0
CHIP_REV[2:0]
000
Page 20
REVISION
This number is incrementally updated each time the
silicon is revised.
Register 01h REVISION
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R2 (02h)
PSCTRL1
1:0
SYS_ENA[1:0]
00
System Power Control
00 = Off
Page 27
01 = Power down
10 = Power up to mute
11 = Power up to unmute
Register 02h PSCTRL1
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WM8523
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
DAC De-emphasis Control
REFER TO
R3 (03h)
AIF_CTRL1
8
DAC_DEEMP
0
Page 31
Page 24
Page 24
0 = No de-emphasis
1 = De-emphasis enabled
Master/Slave Select
0 = Slave mode
7
6
AIF_MSTR
0
0
1 = Master mode
AIF_LRCLK_
INV
LRCLK Inversion Control
0 = Normal polarity
1 = Inverted polarity
When AIF_FMT[2:0]=011 (DSP Mode):
0 = Mode A (2nd clock)
1 = Mode B (1st clock)
BCLK Inversion Control
Slave mode:
5
AIF_BCLK_INV
0
Page 24
0 = Use rising edge
1 = Use falling edge
Master mode:
0 = BCLK normal
1 = BCLK inverted
Audio Data Word Length
00 = 16 bits
4:3
AIF_WL[1:0]
10
Page 24
Page 24
01 = 20 bits
10 = 24 bits
11 = 32 bits
2
Reserved
0
Reserved
2:0
AIF_FMT[1:0]
10
Audio Data Interface Format
00 = Right justified
01 = Left justified
10 = I2S format
11 = DSP mode
Register 03h AIF_CTRL1
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Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Digital Monomix Control
REFER TO
R4 (04h)
AIF_CTRL2
7:6
DAC_OP_
MUX[1:0]
00
Page 31
00 = Stereo (normal operation)
01 = Mono (Left data to DACR)
10 = Mono (Right data to DACL)
11 = Digital monomix, (L+R)/2
BCLK Divider Control (Master Mode)
000 = MCLK/4
5:3
AIF_
000
Page 24
BCLKDIV[2:0]
001 = MCLK/8
010 = 32fs
011 = 64fs
100 = 128fs
101 - 111 reserved
MCLK:LRCLK Ratio
000 = Auto detect
001 = 128fs
2:0
AIF_SR[2:0]
000
Page 24
010 = 192fs
011 = 256fs
100 = 384fs
101 = 512fs
110 = 768fs
111 = 1152fs
Register 04h AIF_CTRL2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R5 (05h)
4
DAC_ZC
0
Zero Cross Enable
Page 28
DAC_CTRL3
0 = Do not use zero cross
1 = Use zero cross
3
2
1
0
DACR_MUTE
DACL_MUTE
0
0
0
1
Right DAC Mute
Page 31
Page 31
Page 29
Page 29
0 = Normal operation
1 = Mute
Left DAC Mute
0 = Normal operation
1 = Mute
DAC_VOL_
UP_RAMP
DAC Digital Volume Increase Control
0 = Apply volume increases instantly (step)
1 = Ramp volume increases
DAC Digital Volume Decrease Control
0 = Apply volume decreases instantly (step)
1 = Ramp volume decreases
DAC_VOL_
DOWN_RAMP
Register 05h DAC_CTRL3
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WM8523
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R6 (06h)
DAC_GAINL
9
DACL_VU
0
Left DAC Digital Volume Update
Page 28
Page 28
0 = Latch Left DAC volume setting into register map
but do not update volume
1 = Latch Left DAC volume setting into register map
and update left and right channels simultaneously
8:0
DACL_VOL[8:0] 1_1001_0000 Left DAC Digital Volume Control
0 0000 0000 = -100dB
0 0000 0001 = -99.75dB
0 0000 0010 = -99.5dB
…0.25dB steps
1 1001 0000 = 0dB
…0.25dB steps
1 1011 1110 = +11.75dB
1 11XX XXXX = +12dB
Register 06h DAC_GAINL
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R7 (07h)
DAC_GAIN
R
9
DACR_VU
0
Right DAC Digital Volume Update
Page 28
0 = Latch Right DAC volume setting into register
map but do not update volume
1 = Latch Right DAC volume setting into register
map and update left and right channels
simultaneously
8:0
DACR_VOL[8:0] 1_1001_0000 Right DAC Digital Volume Control
0 0000 0000 = -100dB
Page 28
0 0000 0001 = -99.75dB
0 0000 0010 = -99.5dB
…0.25dB steps
1 1001 0000 = 0dB
…0.25dB steps
1 1011 1110 = +11.75dB
1 11XX XXXX = +12dB
Register 07h DAC_GAINR
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Zero Detect Count Control
REFER
TO
R8 (08h)
ZERO_
0
ZD_COUNT[1:0]
0
Page 31
0 = 1024
1 = 2048
DETECT
Register 08h ZERO_DETECT
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Production Data
DIGITAL FILTER CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
14.5
6.5
MAX
UNIT
DAC Filter – 256fs to 1152fs
Passband
0.1dB
f > 0.546fs
0.1dB
0.454fs
0.1
Passband Ripple
Stopband
dB
0.546fs
-50
Stopband attenuation
Group Delay
dB
Fs
DAC Filter – 128fs and 192fs
Passband
0.247fs
0.1
Passband Ripple
Stopband
dB
0.753fs
-50
Stopband attenuation
Group Delay
f > 0.753fs
dB
Fs
TERMINOLOGY
1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)
2. Pass-band Ripple – any variation of the frequency response in the pass-band region
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WM8523
DAC FILTER RESPONSES
0.2
0.15
0.1
0
-20
0.05
0
-40
-60
-0.05
-0.1
-0.15
-0.2
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Figure 27 DAC Digital Filter Frequency Response
– 256fs to 1152fs Clock Modes
Figure 28 DAC Digital Filter Ripple – 256fs to 1152fs
Clock Modes
0.2
0
0
-20
-0.2
-0.4
-0.6
-0.8
-1
-40
-60
-80
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
-100
Frequency (Fs)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (Fs)
Figure 29 DAC Digital Filter Frequency Response
– 128fs and 192fs Clock Modes
Figure 30 DAC Digital Filter Ripple – 128fs to 192fs Clock
Modes
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DIGITAL DE-EMPHASIS CHARACTERISTICS
0
1
0.5
0
-2
-4
-0.5
-1
-6
-1.5
-2
-8
-2.5
-3
-10
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Frequency (kHz)
Frequency (kHz)
Figure 31 De-Emphasis Frequency Response (32kHz)
Figure 32 De-Emphasis Error (32kHz)
Figure 33 De-Emphasis Frequency Response (44.1kHz)
Figure 34 De-Emphasis Error (44.1kHz)
0
1
0.8
0.6
0.4
0.2
0
-2
-4
-6
-0.2
-0.4
-0.6
-0.8
-1
-8
-10
0
5
10
15
20
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
Figure 35 De-Emphasis Frequency Response (48kHz)
Figure 36 De-Emphasis Error (48kHz)
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WM8523
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS – 20-LEAD TSSOP
Figure 37 Recommended External Components
Notes:
1. Wolfson recommend using a single, common ground plane. Where this is not possible, care should be taken to
optimise split ground configuration for audio performance.
2. Charge Pump fly-back capacitor C5 should be placed as close to WM8523 as possible, followed by Charge Pump
decoupling capacitor C1, then LINEVDD and VMID decoupling capacitors. See Recommended PCB Layout on p44.
3. Capacitor types should be chosen carefully. Capacitors with very low ESR are recommended for optimum
performance.
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RECOMMENDED PCB LAYOUT – 20-LEAD TSSOP
Figure 38 Recommended PCB Layout
Notes:
1. C5 should be placed as close to WM8523 as possible, with minimal track lengths to reduce inductance and maximise
performance of the charge pump. Vias should be avoided in the tracking to C5.
2. C1 is then next most important and should also be placed as close as possible to the WM8523. Again, minimise
track lengths and avoid vias to reduce parasitic inductance.
3. C2 and C4 are then next most important, and lastly C3.
4. The WM8523 evaluation board, details available at www.wolfsonmicro.com, shows an example of good component
placement and layout to maximise performance with a minimal BOM.
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WM8523
RECOMMENDED EXTERNAL COMPONENTS – 24-LEAD QFN
Figure 39 Recommended External Components
Notes:
1. Wolfson recommend using a single, common ground plane. Where this is not possible, care should be taken to
optimise split ground configuration for audio performance.
2. Charge Pump fly-back capacitor C5 should be placed as close to WM8523 as possible, followed by Charge Pump
decoupling capacitor C1, then LINEVDD and VMID decoupling capacitors. See Recommended PCB Layout on p44.
3. Capacitor types should be chosen carefully. Capacitors with very low ESR are recommended for optimum
performance.
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RECOMMENDED PCB LAYOUT – 24-LEAD QFN
Figure 40 Recommended PCB Layout
Notes:
1. C5 should be placed as close to WM8523 as possible, with minimal track lengths to reduce inductance and maximise
performance of the charge pump. Vias should be avoided in the tracking to C5.
2. C1 is then next most important and should also be placed as close as possible to the WM8523. Again, minimise
track lengths and avoid vias to reduce parasitic inductance.
3. C2 and C4 are then next most important, and lastly C3.
4. The WM8523 evaluation board, details available at www.wolfsonmicro.com, shows an example of good component
placement and layout to maximise performance with a minimal BOM.
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WM8523
RECOMMENDED ANALOGUE LOW PASS FILTER
Figure 41 Recommended Analogue Low Pass Filter (one channel shown)
An external single-pole RC filter is recommended if the device is driving a wideband
amplifier. Other filter architectures may provide equally good results.
The filter shown in Figure 41 has a -3dB cut-off at 105.26kHz and a droop of 0.15dB at
20kHz. The typical output from the WM8523 is 2.1Vrms – when a 10kΩ load is placed at the
output of this recommended filter the amplitude across this load is 1.99Vrms.
RELEVANT APPLICATION NOTES
The following application notes, available from www.wolfsonmicro.com, may provide
additional guidance for use of the WM8523.
DEVICE PERFORMANCE:
WAN0129 – Decoupling and Layout Methodology for Wolfson DACs, ADCs and CODECs
WAN0144 – Using Wolfson Audio DACs and CODECs with Noisy Supplies
WTN0302 - WM8524 Recommended Power Sequence and Timing (for hardware mode)
GENERAL:
WAN0108 – Moisture Sensitivity Classification and Plastic IC Packaging
WAN0109 – ESD Damage in Integrated Circuits: Causes and Prevention
WAN0158 – Lead-Free Solder Profiles for Lead-Free Components
WAN0161 – Electronic End-Product Design for ESD
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PACKAGE DIMENSIONS – 20-LEAD TSSOP
DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm)
DM008.D
b
e
20
11
E1
E
GAUGE
PLANE
θ
1
10
D
0.25
c
L
A1
A2
A
-C-
0.1
C
SEATING PLANE
Dimensions
(mm)
NOM
-----
Symbols
MIN
-----
MAX
1.20
0.15
1.05
0.30
0.20
6.60
A
A1
A2
b
c
D
e
E
E1
L
0.05
0.80
0.19
0.09
6.40
-----
1.00
-----
-----
6.50
0.65 BSC
6.4 BSC
4.40
4.30
0.45
0o
4.50
0.75
8o
0.60
-----
θ
REF:
JEDEC.95, MO-153
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
PD, Rev 4.1, August 2011
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WM8523
PACKAGE DIMENSIONS – 24-LEAD QFN
FL: 24 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.75 mm BODY, 0.50 mm LEAD PITCH
DM061.A
DETAIL 1
D
D2
19
24
1
18
EXPOSED
GROUND
PADDLE
INDEX AREA
(D/2 X E/2)
4
6
E2
A
E
SEE DETAIL 2
13
6
aaa
C
2 X
12
7
1
b
aaa
C
2 X
M
A
B
bbb
C
e
TOP VIEW
BOTTOM VIEW
ccc
C
DETAIL 1
DETAIL 2
A3
A
L
5
0.08
C
Datum
45
degrees
A1
Terminal
Tip
e/2
C
SIDE VIEW
0.3mm
EXPOSED
GROUND
PADDLE
DETAIL 3
SEATING PLANE
e
R
A3
G
b
Exposed lead
DETAIL 3
Symbols
MIN
0.70
0
NOM
0.75
MAX
NOTE
A
A1
A3
b
0.80
0.05
0.02
0.203 REF
0.25
0.20
2.65
2.65
0.30
2.75
2.75
1
D
4.00 BSC
2.70
D2
E
2
2
4.00 BSC
2.70
E2
e
0.50 BSC
0.625
G
L
0.35
0.40
0.45
Tolerances of Form and Position
aaa
bbb
ccc
0.15
0.10
0.10
REF:
JEDEC, MO-220
NOTES:
1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP.
2. FALLS WITHIN JEDEC, MO-220.
3. ALL DIMENSIONS ARE IN MILLIMETRES.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002.
5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
7. DEPENDING ON THE METHOD OF LEAD TERMINATION AT THE EDGE OF THE PACKAGE, PULL BACK (L1) MAY BE PRESENT.
8. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
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IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Any use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or
services might be or are used. Any provision or publication of any third party’s products or services does not constitute
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document
belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is
not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any
reliance placed thereon by any person.
ADDRESS
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: apps@wolfsonmicro.com
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WM8523
REVISION HISTORY
DATE
REV
ORIGINATOR
CHANGES
PAGE
23/08/10
4.1
BT
Added minimum A-weighted SNR limit of 100dB
9
BT
Changed Group delay of 256/128fs filters from 10fs to 14.5fs and 6.5fs 40
PD, Rev 4.1, August 2011
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相关型号：
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