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WM8590_06 [WOLFSON]

24-bit, 192kHz Stereo CODEC; 24位， 192kHz立体声编解码器
WM8590_06
型号： WM8590_06
厂家： WOLFSON MICROELECTRONICS PLC    WOLFSON MICROELECTRONICS PLC
描述：

24-bit, 192kHz Stereo CODEC
24位， 192kHz立体声编解码器

解码器 编解码器
文件： 总51页 (文件大小：523K)
中文：  中文翻译
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WM8590  
w
24-bit, 192kHz Stereo CODEC  
DESCRIPTION  
FEATURES  
•
Audio Performance  
The WM8590 is a high performance, stereo audio codec with  
differential inputs and outputs. It is ideal for surround sound  
processing applications for home hi-fi, DVD-RW and other  
audio visual equipment.  
−
−
110dB SNR (‘A’ weighted @ 48kHz) DAC  
102dB SNR (‘A’ weighted @ 48kHz) ADC  
•
•
•
DAC Sampling Frequency: 32kHz – 192kHz  
ADC Sampling Frequency: 32kHz – 96kHz  
The stereo 24-bit multi-bit sigma delta ADC has programmable  
gain with limiting control. Digital audio output word lengths from  
16-32 bits and sampling rates from 32kHz to 96kHz are  
supported.  
Stereo ADC input analogue gain adjust from +24dB to –21dB in  
0.5dB steps  
•
•
•
•
•
•
ADC digital gain from -21.5dB to -103dB in 0.5dB steps  
Programmable Limiter on ADC input.  
A stereo multi-bit sigma delta DAC is used with digital audio  
input word lengths from 16-32 bits and sampling rates from  
32kHz to 192kHz.  
Stereo DAC with differential analogue line outputs.  
3-Wire SPI Compatible Control Interface  
Master or Slave Clocking Mode  
The WM8590 supports fully independent sample rates for the  
ADC and DAC. The audio data interface supports I2S, left  
justified, right justified and DSP formats.  
Programmable Audio Data Interface Modes  
−
−
I2S, Left, Right Justified or DSP  
16/20/24/32 bit Word Lengths  
The device is controlled in software via a 3 wire serial interface  
which provides access to all features including volume controls,  
mutes, and de-emphasis facilities. The device is available in a  
28-lead SSOP package.  
•
•
4.5V to 5.5V Analogue, 2.7V to 3.6V Digital supply Operation  
28-lead SSOP Package  
APPLICATIONS  
•
•
Surround Sound AV Processors and Hi-Fi systems  
DVD-RW  
BLOCK DIAGRAM  
WOLFSON MICROELECTRONICS plc  
Production Data, January 2006, Rev 4.0  
Copyright 2006 Wolfson Microelectronics plc  
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/  
WM8590  
Production Data  
TABLE OF CONTENTS  
DESCRIPTION .......................................................................................................1  
FEATURES.............................................................................................................1  
APPLICATIONS .....................................................................................................1  
BLOCK DIAGRAM .................................................................................................1  
TABLE OF CONTENTS .........................................................................................2  
PIN CONFIGURATION...........................................................................................3  
ORDERING INFORMATION ..................................................................................3  
ABSOLUTE MAXIMUM RATINGS.........................................................................5  
ELECTRICAL CHARACTERISTICS ......................................................................6  
TERMINOLOGY............................................................................................................ 8  
MASTER CLOCK TIMING......................................................................................9  
DIGITAL AUDIO INTERFACE – MASTER MODE......................................................... 9  
DIGITAL AUDIO INTERFACE – SLAVE MODE .......................................................... 10  
3-WIRE MPU INTERFACE TIMING ............................................................................ 12  
DEVICE DESCRIPTION.......................................................................................13  
INTRODUCTION......................................................................................................... 13  
AUDIO DATA SAMPLING RATES............................................................................... 13  
ZERO DETECT ........................................................................................................... 15  
POWERDOWN MODES ............................................................................................. 15  
INTERNAL POWER ON RESET CIRCUIT.................................................................. 16  
DIGITAL AUDIO INTERFACE..................................................................................... 18  
CONTROL INTERFACE OPERATION........................................................................ 23  
CONTROL INTERFACE REGISTERS ........................................................................ 24  
ADC/DAC SYNCHRONIZATION................................................................................. 32  
LIMITER / AUTOMATIC LEVEL CONTROL (ALC)...................................................... 33  
REGISTER MAP ......................................................................................................... 37  
DIGITAL FILTER CHARACTERISTICS...............................................................44  
DAC FILTER RESPONSES......................................................................................... 45  
ADC FILTER RESPONSES......................................................................................... 46  
ADC HIGH PASS FILTER ........................................................................................... 46  
DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................... 47  
APPLICATIONS INFORMATION .........................................................................48  
RECOMMENDED EXTERNAL COMPONENTS.......................................................... 48  
USE OF ADC/DAC SYNCHRONIZER......................................................................... 49  
PACKAGE DIMENSIONS ....................................................................................50  
IMPORTANT NOTICE..........................................................................................51  
ADDRESS: .................................................................................................................. 51  
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Production Data  
WM8590  
PIN CONFIGURATION  
ORDERING INFORMATION  
MOISTURE  
SENSITIVITY LEVEL  
PEAK SOLDERING  
TEMPERATURE  
TEMPERATURE  
DEVICE  
RANGE  
PACKAGE  
28-lead SSOP  
(Pb-free)  
WM8590GEDS/V  
WM8590GEDS/RV  
-25 to +85oC  
-25 to +85oC  
MSL2  
MSL2  
260°C  
28-lead SSOP  
(Pb-free, tape and reel)  
260°C  
Note:  
Reel quantity = 2,000  
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WM8590  
Production Data  
PIN DESCRIPTION  
PIN  
1
NAME  
DI  
TYPE  
DESCRIPTION  
Digital Input  
Digital Input  
Digital Output  
(open drain)  
Digital Output  
(open drain)  
Serial interface data  
Serial interface clock  
2
CL  
3
ZFLAGR  
Right channel zero flag output (external pull-up required), 5V tolerant  
4
ZFLAGL  
Left channel zero flag output (external pull-up required), 5V tolerant  
5
6
ADCLRC  
ADCBCLK  
ADCMCLK  
DOUT  
Digital Input/Output ADC left/right word clock  
Digital Input/Output ADC audio interface bit clock  
7
Digital Input  
Master ADC clock; 256, 384, 512 or 768fs (fs = word clock frequency)  
ADC data output  
8
Digital Output  
9
DACLRC  
DACBCLK  
DACMCLK  
Digital Input/Output DAC left/right word clock  
Digital Input/Output DAC audio interface bit clock  
10  
11  
Digital Input  
Master DAC clock; 256, 384, 512, 768fs or 1152fs (fs = word clock  
frequency)  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
DIN  
DVDD  
DGND  
VOUTRP  
VOUTRN  
VOUTLP  
VOUTLN  
AGND  
REFN  
Digital Input  
Supply  
DAC data input  
Digital positive supply  
Digital negative supply  
Supply  
Analogue Output DAC right channel positive output  
Analogue Output DAC right channel negative output  
Analogue Output DAC left channel positive output  
Analogue Output DAC left channel negative output  
Supply  
Analogue negative supply and substrate connection  
Negative reference input  
Analogue Input  
VMID  
Analogue Output Midrail divider decoupling pin; must be externally decoupled  
REFP  
Analogue Input  
Supply  
Positive reference input  
AVDD  
AINLP  
AINLN  
AINRP  
AINRN  
CE  
Analogue positive supply  
Left channel positive input  
Left channel negative input  
Right channel positive input  
Right channel negative input  
Serial interface Latch signal  
Analogue Input  
Analogue Input  
Analogue Input  
Analogue Input  
Digital Input  
Notes:  
1. Digital input pins have Schmitt trigger input buffers. Pins 3 and 4 are 5V tolerant.  
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WM8590  
ABSOLUTE MAXIMUM RATINGS  
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at  
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical  
Characteristics at the test conditions specified.  
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible  
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage  
of this device.  
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage  
conditions prior to surface mount assembly. These levels are:  
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.  
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.  
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.  
The Moisture Sensitivity Level for each package type is specified in Ordering Information.  
CONDITION  
MIN  
-0.3V  
MAX  
+3.63V  
Digital supply voltage, DVDD  
Analogue supply voltage, AVDD  
-0.3V  
+7V  
Voltage range digital inputs (MCLK, DIN, ADCLRC, DACLRC,  
ADCBCLK, DACBCLK, DI, CL and CE)  
DGND -0.3V  
DVDD + 0.3V  
Voltage range analogue inputs  
Master Clock Frequency  
AGND -0.3V  
AVDD +0.3V  
38.462MHz  
+85°C  
Operating temperature range, TA  
Storage temperature  
-25°C  
-65°C  
+150°C  
Notes:  
1. Analogue and digital grounds must always be within 0.3V of each other.  
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Production Data  
RECOMMENDED OPERATING CONDITIONS  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
2.7  
TYP  
3.3  
5
MAX  
3.6  
UNIT  
Digital supply range  
Analogue supply range  
Ground  
DVDD  
V
V
V
AVDD, DACREFP  
4.5  
5.5  
AGND, DGND,  
DACREFN,  
0
ADCREFGND  
Difference DGND to AGND  
-0.3  
0
+0.3  
V
Note:  
1. Digital supply DVDD must never be more than 0.3V greater than AVDD in normal operation.  
2. It is possible to hold the device in reset with AVDD=0V and DVDD=3.3V.  
ELECTRICAL CHARACTERISTICS  
Test Conditions  
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Digital Logic Levels (CMOS Levels)  
Input LOW level  
VIL  
VIH  
0.3 x DVDD  
0.1 x DVDD  
V
V
Input HIGH level  
0.7 x DVDD  
0.9 x DVDD  
Output LOW  
VOL  
VOH  
I
OL=1mA  
V
Output HIGH  
IOH=1mA  
V
Digital Input Leakage Current  
0.9  
5
µA  
pF  
Digital Input Leakage  
Capacitance  
Analogue Reference Levels  
Reference voltage  
VVMID  
RVMID  
AVDD/2  
50  
V
Potential divider resistance  
kΩ  
DAC Performance (Load = 10kΩ, 50pF)  
0dBFs Full scale output voltage  
2.0 x  
AVDD/5  
110  
Vrms  
dB  
SNR (Note 1,2)  
SNR  
A-weighted,  
@ fs = 48kHz  
A-weighted  
100  
100  
SNR (Note 1,2)  
SNR  
109  
110  
dB  
@ fs = 96kHz  
Dynamic Range (Note 2)  
DNR  
THD  
A-weighted, -60dB  
full scale input  
dB  
Total Harmonic Distortion  
DAC channel separation  
Channel Level Matching  
Channel Phase Deviation  
Power Supply Rejection Ratio  
1kHz, 0dBFs  
-97  
130  
0.1  
0.04  
50  
-87  
dB  
dB  
1kHz signal  
1kHz signal  
dB  
Degree  
dB  
PSRR  
1kHz 100mVpp  
20Hz to 20kHz  
100mVpp  
45  
dB  
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WM8590  
Test Conditions  
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.  
ADC Performance  
Input Signal Level (0dB)  
2.0 x  
AVDD/5  
102  
3.0 x  
Vrms  
dB  
AVDD/5  
SNR (Note 1,2)  
SNR  
SNR  
A-weighted, 0dB gain  
@ fs = 48kHz  
93  
93  
ADCMCLK2DAC=1  
A-weighted, 0dB gain  
@ fs = 96kHz  
SNR (Note 1,2)  
99  
dB  
dB  
64 x OSR  
ADCMCLK2DAC=1  
Dynamic Range (note 2)  
Total Harmonic Distortion  
DNR  
THD  
A-weighted, -60dB  
full scale input  
102  
ADCMCLK2DAC=1  
1kHz, 0dBFs  
-90  
-95  
dB  
dB  
ADCMCLK2DAC=1  
1kHz, -3dBFs  
ADCMCLK2DAC=1  
1kHz Input  
-85  
ADC Channel Separation  
Channel Level Matching  
Channel Phase Deviation  
Programmable Gain Step Size  
Programmable Gain Range  
(Analogue)  
85  
0.1  
dB  
dB  
1kHz signal  
1kHz signal  
0.06  
0.5  
Degree  
dB  
0.25  
-21  
0.75  
+24  
1kHz Input  
1kHz Input  
dB  
Programmable Gain Range  
(Digital)  
-103  
-21.5  
dB  
Mute Attenuation (Note 4)  
Power Supply Rejection Ratio  
1kHz Input, 0dB gain  
1kHz 100mVpp  
97  
59  
56  
dB  
dB  
dB  
PSRR  
20Hz to 20kHz  
100mVpp  
Input Resistance  
PGA Gain = +24dB  
PGA Gain = 0dB  
PGA Gain = -21dB  
4.5  
37.4  
69.0  
1
kΩ  
kΩ  
kΩ  
pF  
Input Capacitance  
Supply Current  
Analogue supply current  
Digital supply current  
Analogue Powerdown Current  
Digital Powerdown Current  
Crosstalk  
AVDD = 5V  
DVDD = 3.3V  
AVDD = 5V  
60  
6
mA  
mA  
µA  
132  
2.7  
DVDD = 3.3V  
µA  
DAC to ADC  
1kHz signal, ADC fs =  
48kHz, DAC fs =  
44.1kHz  
115  
130  
131  
138  
dB  
dB  
dB  
dB  
20kHz signal, ADC fs =  
48kHz, DAC fs =  
44.1kHz  
ADC to DAC  
1kHz signal, ADC fs =  
48kHz, DAC fs =  
44.1kHz  
20kHz signal, ADC fs =  
48kHz, DAC fs =  
44.1kHz  
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Production Data  
Notes:  
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’  
weighted.  
2. All performance measurements obtained with 20kHz low pass filter, and where noted an A-weight filter. Failure to use  
such a filter will result in higher THD and lower SNR and Dynamic Range readings than are found in the Electrical  
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic  
specification values.  
3. All performance measurements obtained using certain timings conditions (ADCLRC and DACLRC should be  
synchronous with MCLK). Please refer to section ‘Digital Audio Interface’.  
4. A better MUTE Attenuation can be achieved if the ADC gain is set to minimum.  
5. All performance measurements specified for ADC and DAC operating in isolation.  
TERMINOLOGY  
1. Signal-to-noise ratio (dB) – SNR is a measure of the difference in level between the full scale output and the output  
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).  
2. Dynamic range (dB) – DNR is a measure of the difference between the highest and lowest portions of a signal.  
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB  
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).  
3. THD (dB) – THD is a ratio, of the rms values, of Distortion/Signal.  
4. Stop band attenuation (dB) – Is the degree to which the frequency spectrum is attenuated (outside audio band).  
5. Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from  
the other. Normally measured by sending a full scale signal down one channel and measuring the other.  
6. Pass-Band Ripple – Any variation of the frequency response in the pass-band region.  
7. The WM8590 employs CMOS switching levels on the digital interface input. Logic 0 VIL. Logic 1 VIH.  
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WM8590  
MASTER CLOCK TIMING  
Figure 1 Master Clock Timing Requirements  
Test Conditions  
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
System Clock Timing Information  
ADC/DACMCLK System clock  
pulse width high  
tMCLKH  
tMCLKL  
tMCLKY  
11  
11  
ns  
ns  
ADC/DACMCLK System clock  
pulse width low  
ADC/DACMCLK System clock  
cycle time  
ns  
26  
ADC/DACMCLK Duty cycle  
40:60  
60:40  
Table 1 Master Clock Timing Requirements  
DIGITAL AUDIO INTERFACE – MASTER MODE  
DACBCLK  
ADCBCLK  
ADCLRC  
DACLRC  
DOUT  
DVD  
Controller  
WM8590  
CODEC  
DIN  
Figure 2 Audio Interface – Master Mode  
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Figure 3 Digital Audio Data Timing – Master Mode  
Test Conditions  
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless  
otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Audio Data Input Timing Information  
ADC/DACLRC propagation  
delay from ADC/DACBCLK  
falling edge  
tDL  
0
10  
ns  
DOUT propagation delay  
from ADCBCLK falling edge  
tDDA  
tDST  
tDHT  
0
10  
ns  
ns  
ns  
DIN setup time to  
DACBCLK rising edge  
10  
10  
DIN hold time from  
DACBCLK rising edge  
Table 2 Digital Audio Data Timing – Master Mode  
DIGITAL AUDIO INTERFACE – SLAVE MODE  
DACBCLK  
ADCBCLK  
ADCLRC  
DVD  
Controller  
WM8590  
CODEC  
DACLRC  
DOUT  
DIN  
Figure 4 Audio Interface – Slave Mode  
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WM8590  
Figure 5 Digital Audio Data Timing – Slave Mode  
Test Conditions  
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless  
otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Audio Data Input Timing Information  
ADC/DACBCLK cycle time  
tBCY  
tBCH  
50  
20  
ns  
ns  
ADC/DACBCLK pulse width  
high  
ADC/DACBCLK pulse width  
low  
tBCL  
20  
10  
ns  
ns  
DACLRC/ADCLRC set-up  
time to ADC/DACBCLK  
rising edge  
tLRSU  
DACLRC/ADCLRC hold  
time from ADC/DACBCLK  
rising edge  
tLRH  
10  
ns  
DIN set-up time to  
DACBCLK rising edge  
tDS  
tDH  
tDD  
10  
10  
0
ns  
ns  
ns  
DIN hold time from  
DACBCLK rising edge  
DOUT propagation delay  
10  
from ADCBCLK falling edge  
Table 3 Digital Audio Data Timing – Slave Mode  
Note:  
ADCLRC and DACLRC should be synchronous with MCLK, although the WM8590 interface is tolerant of phase variations  
or jitter on these signals.  
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3-WIRE MPU INTERFACE TIMING  
Figure 6 SPI Compatible (3-wire) Control Interface Input Timing  
Test Conditions  
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated  
PARAMETER  
CL rising edge to CE rising edge  
CL pulse cycle time  
SYMBOL  
SCS 6  
MIN  
0
TYP  
MAX  
UNIT  
t
ns  
tSCY  
tSCL  
tSCH  
tDSU  
tDHO  
tCSC  
tCSH  
tCSS  
80  
30  
30  
20  
20  
20  
20  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CL pulse width low  
CL pulse width high  
DI to CL set-up time  
CL to DI hold time  
CE falling edge to CL rising edge  
CE pulse width high  
CE rising to CL rising  
Table 4 3-wire SPI Compatible Control Interface Input Timing Information  
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WM8590  
DEVICE DESCRIPTION  
INTRODUCTION  
WM8590 is a complete differential 2-channel DAC, 2-channel ADC audio codec, including digital  
interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multi-  
bit sigma delta DACs with output smoothing filters. It is available in a single package and controlled  
by a 3-wire serial interface.  
The DAC and ADC have separate left/right clocks, bit clocks, master clocks and data I/Os. The  
Audio Interfaces may be independently configured to operate in either master or slave mode. In  
Slave mode ADCLRC, DACLRC, ADCBCLK and DACBCLK are all inputs. In Master mode ADCLRC,  
DACLRC, ADCBCLK and DACBCLK are outputs, and clock signals should not be driven into these  
pins by external circuitry. The ADC audio interface defaults to master mode, and the DAC audio  
interface defaults to slave mode.  
The ADC has an analogue input PGA and a digital gain control, accessed by one register write. The  
input PGA allows input signals to be gained up to +24dB and attenuated down to -21dB in 0.5dB  
steps. The digital gain control allows attenuation from -21.5dB to -103dB in 0.5dB steps. This allows  
the user maximum flexibility in the use of the ADC.  
The DAC has its own digital volume control, which is adjustable between 0dB and -127.5dB in 0.5dB  
steps. In addition a zero cross detect circuit is provided for digital volume controls. The digital  
volume control detects a transition through the zero point before updating the volume. This  
minimises audible clicks and ‘zipper’ noise as the gain values change.  
Control of internal functionality of the device is by 3-wire SPI compatible control interface. The  
interface may be asynchronous to the audio data interface as control data will be re-synchronised to  
the audio processing internally.  
Operation using system clock of 128fs, 192fs, 256fs, 384fs, 512fs, 768fs or 1152fs (DAC only) is  
provided. ADC and DAC may run at different rates. Master clock sample rates (fs) from less than  
32kHz up to 192kHz are allowed, provided the appropriate system clock is input.  
The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP  
serial port interface.  
AUDIO DATA SAMPLING RATES  
In a typical digital audio system there is only one central clock source producing a reference clock to  
which all audio data processing is synchronised. This clock is often referred to as the audio system’s  
Master Clock. The WM8590 uses separate master clocks for the ADC and DAC. The external master  
system clocks can be applied directly through the ADCMCLK and DACMCLK input pins with no  
software configuration necessary. In a system where there are a number of possible sources for the  
reference clock it is recommended that the clock source with the lowest jitter be used to optimise the  
performance of the ADC and DAC.  
In Slave mode the WM8590 has a master detection circuit that automatically determines the  
relationship between the master clock frequency and the sampling rate (to within +/- 32 system  
clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output  
level at the last sample. The master clock must be synchronised with ADCLRC/DACLRC, although  
the WM8590 is tolerant of phase variations or jitter on this clock.  
The ADC supports system clock to sampling clock ratios of 256fs to 768fs. The DACs support ratios  
of 256fs to 1152fs when the DAC signal processing of the WM8590 is programmed to operate at 128  
times oversampling rate (DACOSR=0). The DACs support system clock to sampling clock ratios of  
128fs and 192fs when the WM8590 is programmed to operate at 64 times oversampling rate  
(DACOSR=1).  
The ADC signal processing in the WM8590 can operate at either 128 times oversampling rate  
(ADCOSR=0) or 64 times oversampling rate (ADCOSR=1). It is recommended that ADCOSR is set  
to 1 for ADC operation at 96kHz.  
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Production Data  
Table 5 shows the typical system clock frequencies for ADC operation at both 128 times  
oversampling rate (ADCOSR=0) and 64 times oversampling rate (ADCOSR=1), and DAC operation  
at 128 times oversampling rate (DACOSR=0). Table 6 shows typical system clock frequencies for  
DAC operation at 64 times oversampling rate (DACOSR =1).  
SAMPLING  
RATE  
System Clock Frequency (MHz)  
256fs  
384fs  
512fs  
768fs  
1152fs  
(ADCLRC/  
DACLRC)  
32kHz  
(DAC only)  
8.192  
11.2896  
12.288  
24.576  
12.288  
16.9340  
18.432  
36.864  
16.384  
22.5792  
24.576  
24.576  
33.8688  
36.864  
36.864  
44.1kHz  
48kHz  
Unavailable  
Unavailable  
96kHz  
Unavailable Unavailable Unavailable  
Table 5 ADC and DAC System Clock Frequencies Versus Sampling Rate  
(ADC operation at either 128 times oversampling rate (ADCOSR=0) or 64 times oversampling  
rate (ADCOSR=1), DAC operation at 128 times oversampling rate, DACOSR=0)  
SAMPLING  
RATE  
System Clock Frequency (MHz)  
128fs  
192fs  
(DACLRC)  
96kHz  
12.288  
24.576  
18.432  
36.864  
192kHz  
Table 6 DAC System Clock Frequencies Versus Sampling Rate at 64 Times  
Oversampling Rate (DACOSR=1)  
In Master mode DACBCLK, ADCBCLK, DACLRC and ADCLRC are generated by the WM8590, and  
these pins should not be driven by external circuitry. The frequencies of ADCLRC and DACLRC are  
set by setting the required ratio of DACMCLK to DACLRC and ADCMCLK to ADCLRC using the  
DACRATE and ADCRATE control bits (Table 7).  
ADCRATE[2:0]/  
DACRATE[2:0]  
ADCMCLK/DACMCLK:  
ADCLRC/DACLRC  
RATIO  
000  
001  
010  
011  
100  
101  
128fs (DAC Only)  
192fs (DAC Only)  
256fs  
384fs  
512fs  
768fs  
Table 7 Master Mode MCLK: ADCLRC/DACLRC Ratio Select  
Table 8 shows the settings for ADCRATE and DACRATE for common sample rates and  
ADCMCLK/DACMCLK frequencies.  
SAMPLING  
RATE  
System Clock Frequency (MHz)  
128fs  
192fs  
256fs  
384fs  
512fs  
768fs  
(DACLRC/  
ADCLRC)  
DACRATE  
=000  
DACRATE  
=001  
ADCRATE/  
DACRATE  
=010  
ADCRATE/  
DACRATE  
=011  
ADCRATE/  
DACRATE  
=100  
ADCRATE/  
DACRATE  
=101  
32kHz  
44.1kHz  
48kHz  
4.096  
5.6448  
6.144  
6.144  
8.467  
8.192  
11.2896  
12.288  
24.576  
12.288  
16.9340  
18.432  
36.864  
16.384  
22.5792  
24.576  
24.576  
33.8688  
36.864  
9.216  
96kHz  
12.288  
24.576  
18.432  
36.864  
Unavailable Unavailable  
192kHz  
Unavailable Unavailable Unavailable Unavailable  
Table 8 Master Mode ADC/DACLRC Frequency Selection  
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ADCBCLK and DACBCLK are also generated by the WM8590. The frequency of ADCBCLK and  
DACBCLK can be set in software.  
BCLK can be set to MCLK/4, 64fs or 128fs. If DSP mode is selected as the audio interface mode  
then BCLK can be set to MCLK, 64fs or 128fs. Note that DSP mode cannot be used in 128fs mode  
for word lengths greater than 16 bits or in 192fs mode for word lengths greater than 24 bits.  
REGISTER ADDRESS  
R28 (1Ch)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
3:2  
BCLK_RATE  
00  
Sets ADCBCLK and DACBCLK rate in master mode  
0011100  
BCLK_RATE  
BCLK Output Frequency  
MCLK/4 (MCLK in DSP Mode)  
MCLK/4 (MCLK in DSP Mode)  
ADC/DAC  
Synchronization  
00  
01  
10  
11  
64fs  
128fs  
ZERO DETECT  
The WM8590 has a zero detect circuit for each DAC channel, which detects when 1024 consecutive  
zero samples have been input. The two zero flag outputs (ZFLAGL and ZFLAGR) may be  
programmed to output the zero detect signals that may then be used to control external muting  
circuits. The ZFLAGL and ZFLAGR pins require a pull-up resistor to be connected (see external  
components diagram). The ZFLAGL and ZFLAGR pads will pull low to indicate that the zero  
condition has been detected.  
The polarity of the zero flag signals can be changed by setting the ZFLAGPOL bit. When this bit is  
set, the ZFLAGL and ZFLAGR pins will pull low when the zero condition is not found and will go to  
high impedance when the zero condition is detected.  
The zero detect may also be used to automatically enable the mute by setting IZD. The zero flag  
output may be disabled by setting DZFM to 00.  
REGISTER ADDRESS  
R9 (09h)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
2:1  
DZFM  
10  
ZFLAG decode  
0001001  
DZFM  
ZFLAGL  
ZFLAGR  
DAC Mute  
00  
01  
10  
11  
Zero flag disabled  
Left channel zero  
Both channel zero  
Either channels zero  
Zero flag disabled  
Right channel zero  
Both channel zero  
Either channel zero  
4
ZFLAGPOL  
0
ZFLAG polarity  
ZFLAGPOL  
ZFLAGL  
ZFLAGR  
Pin pulls low to indicate zero conidition,  
high impedance otherwise  
0
1
Pin is high impedance when zero  
condition detected, pulls low otherwise  
POWERDOWN MODES  
The WM8590 has powerdown control bits allowing specific parts of the WM8590 to be powered off  
when not being used. Control bit ADCPD powers off the ADC. The stereo DAC has a separate  
powerdown control bit, DACPD allowing the DAC to be powered off when not in use.  
Setting ADCPD and DACPD will powerdown everything except the references VMID, REFN and  
REFP. Setting PDWN will override all other powerdown control bits. It is recommended that ADCPD  
and DACPD are set before setting PDWN. The default is for all blocks to be enabled.  
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INTERNAL POWER ON RESET CIRCUIT  
Figure 7 Internal Power on Reset Circuit Schematic  
The WM8590 includes an internal Power On Reset Circuit which is used reset the digital logic into a  
default state after power up.  
Figure 7 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD. The  
circuit monitors DVDD and VMID and asserts PORB low if DVDD or VMID are below the minimum  
threshold Vpor_off.  
On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until  
AVDD and DVDD and VMID are established. When AVDD, DVDD, and VMID have been established,  
PORB is released high, all registers are in their default state and writes to the digital interface may  
take place.  
On power down, PORB is asserted low whenever DVDD or VMID drop below the minimum threshold  
Vpor_off.  
If AVDD is removed at any time, the internal Power On Reset circuit is powered down and PORB will  
follow AVDD.  
In most applications the time required for the device to release PORB high will be determined by the  
charge time of the VMID node.  
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Figure 8 Typical Power up Sequence where DVDD is Powered before AVDD  
Figure 9 Typical Power up Sequence where AVDD is Powered before DVDD  
Typical POR Operation (typical values, not tested)  
SYMBOL  
Vpora  
MIN  
0.5  
0.5  
1.0  
0.6  
TYP  
0.7  
0.7  
1.4  
0.8  
MAX  
1.0  
UNIT  
V
V
V
V
Vporr  
1.1  
Vpora_off  
Vpord_off  
2.0  
1.0  
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In a real application the designer is unlikely to have control of the relative power up sequence of  
AVDD and DVDD. Using the POR circuit to monitor VMID ensures a reasonable delay between  
applying power to the device and Device Ready.  
Figure 8 and Figure 9 show typical power up scenarios in a real system. Both AVDD and DVDD must  
be established and VMID must have reached the threshold Vporr before the device is ready and can  
be written to. Any writes to the device before Device Ready will be ignored.  
Figure 8 shows DVDD powering up before AVDD. Figure 9 shows AVDD powering up before DVDD.  
In both cases, the time from applying power to Device Ready is dominated by the charge time of  
VMID.  
A 10uF cap is recommended for decoupling on VMID. The charge time for VMID will dominate the  
time required for the device to become ready after power is applied. The time required for VMID to  
reach the threshold is a function of the VMID resistor string and the decoupling capacitor. The  
Resistor string has an typical equivalent resistance of 50kohm (+/-20%). Assuming a 10uF capacitor,  
the time required for VMID to reach threshold of 1V is approx 110ms.  
DIGITAL AUDIO INTERFACE  
MASTER AND SLAVE MODES  
The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In  
both Master and Slave modes DIN is always an input to the WM8590 and DOUT is always an output.  
The default for the DAC is Slave mode, and the default for the ADC is Master mode.  
In Slave mode (MS=0) ADCLRC, DACLRC, ADCBCLK and DACBCLK are inputs to the WM8590  
(Figure 10). DIN and DACLRC are sampled by the WM8590 on the rising edge of DACBCLK,  
ADCLRC is sampled on the rising edge of ADCBCLK. ADC data is output on DOUT and changes on  
the falling edge of ADCBCLK. By setting control bits ADCBCP or DACBCP the polarity of ADCBCLK  
and DACBCLK may be reversed so that DIN and DACLRC are sampled on the falling edge of  
DACBCLK, ADCLRC is sampled on the falling edge of ADCBCLK and DOUT changes on the rising  
edge of ADCBCLK.  
DACBCLK  
ADCBCLK  
ADCLRC  
DVD  
Controller  
WM8590  
CODEC  
DACLRC  
DOUT  
DIN  
Figure 10 Slave Mode  
In Master mode (MS=1) ADCLRC, DACLRC, ADCBCLK and DACBCLK are outputs from the  
WM8590 (Figure 11), and these pins should not be driven by external circuitry. ADCLRC, DACLRC,  
ADCBCLK and DACBCLK are generated by the WM8590. DIN is sampled by the WM8590 on the  
rising edge of DACBCLK so the controller must output DAC data that changes on the falling edge of  
DACBCLK. ADC data is output on DOUT and changes on the falling edge of ADCBCLK. By setting  
control bits ADCBCP and DACBCP, the polarity of ADCBCLK and DACBCLK may be reversed so  
that DIN is sampled on the falling edge of DACBCLK and DOUT changes on the rising edge of  
ADCBCLK.  
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DACBCLK  
ADCBCLK  
ADCLRC  
DVD  
Controller  
WM8590  
CODEC  
DACLRC  
DOUT  
DIN  
Figure 11 Master Mode  
AUDIO INTERFACE FORMATS  
Audio data is applied to the internal DAC filters or output from the ADC filters, via the Digital Audio  
Interface. 5 popular interface formats are supported:  
•
•
•
•
•
Left Justified mode  
Right Justified mode  
I2S mode  
DSP Mode A  
DSP Mode B  
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the  
exception of 32 bit right justified mode, which is not supported.  
In left justified, right justified and I2S modes, the digital audio interface receives DAC data on the DIN  
input and outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with  
ADCLRC/DACLRC indicating whether the left or right channel is present. ADCLRC/DACLRC is also  
used as a timing reference to indicate the beginning or end of the data words.  
In left justified, right justified and I2S modes; the minimum number of BCLKs per DACLRC/ADCLRC  
period is 2 times the selected word length. ADCLRC/DACLRC must be high for a minimum of word  
length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on  
ADCLRC/DACLRC is acceptable provided the above requirements are met.  
In DSP Mode A or B, DACLRC is used as a frame sync signal to identify the MSB of the first word.  
The minimum number of DACBCLKs per DACLRC period is 2 times the selected word length. Any  
mark to space ratio is acceptable on DACLRC provided the rising edge is correctly positioned. The  
ADC data may also be output in DSP Modes A or B, with ADCLRC used as a frame sync to identify  
the MSB of the first word. The minimum number of ADCBCLKs per ADCLRC period is 2 times the  
selected word length.  
LEFT JUSTIFIED MODE  
In left justified mode, the MSB of DIN is sampled by the WM8590 on the first rising edge of  
DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and  
changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge  
of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right  
samples (Figure 12).  
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1/fs  
LEFT CHANNEL  
RIGHT CHANNEL  
DACLRC/  
ADCLRC  
DACBCLK/  
ADCBCLK  
DIN/  
DOUT  
1
2
3
n
n-2 n-1  
1
2
3
n
n-2 n-1  
MSB  
LSB  
MSB  
LSB  
Figure 12 Left Justified Mode Timing Diagram  
RIGHT JUSTIFIED MODE  
In right justified mode, the LSB of DIN is sampled by the WM8590 on the rising edge of DACBCLK  
preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the  
falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of  
ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples  
(Figure 13).  
1/fs  
LEFT CHANNEL  
RIGHT CHANNEL  
DACLRC/  
ADCLRC  
DACBCLK/  
ADCBCLK  
DIN/  
DOUT  
1
2
3
n
1
2
3
n
n-2 n-1  
n-2 n-1  
MSB  
LSB  
MSB  
LSB  
Figure 13 Right Justified Mode Timing Diagram  
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I2S MODE  
In I2S mode, the MSB of DIN is sampled by the WM8590 on the second rising edge of DACBCLK  
following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the  
first falling edge of ADCBCLK following an ADCLRC transition and may be sampled on the rising  
edge of ADCBCLK. ADCLRC and DACLRC are low during the left samples and high during the right  
samples.  
1/fs  
LEFT CHANNEL  
RIGHT CHANNEL  
DACLRC/  
ADCLRC  
DACBCLK/  
ADCBCLK  
1 BCLK  
1 BCLK  
DIN/  
DOUT  
1
2
3
n
1
2
3
n
n-2 n-1  
n-2 n-1  
LSB  
LSB  
MSB  
MSB  
Figure 14 I2S Mode Timing Diagram  
DSP MODES  
In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A)  
rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data  
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,  
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.  
In device master mode, the LRC output will resemble the frame pulse shown in Figure 15 and Figure  
16. In device slave mode, Figure 17 and Figure 18, it is possible to use any length of frame pulse  
less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period  
before the rising edge of the next frame pulse.  
Figure 15 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)  
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Figure 16 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master)  
Figure 17 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)  
Figure 18 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave)  
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CONTROL INTERFACE OPERATION  
The WM8590 is controlled by writing to registers through a serial control interface. A control word  
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is  
accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 bits in each control  
register. The control interface operates as a 3-wire MPU interface.  
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL  
While CE is low, every rising edge of CL clocks in one data bit from the DI pin. A rising edge on CE  
latches in a complete control word consisting of the last 16 bits. The 3-wire interface protocol is  
shown in Figure 19.  
Figure 19 3-wire SPI Compatible Interface  
1. B[15:9] are Control Address Bits  
2. B[8:0] are Control Data Bits  
3. CE is edge sensitive – the data is latched on the rising edge of CE.  
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CONTROL INTERFACE REGISTERS  
DIGITAL AUDIO INTERFACE CONTROL REGISTER  
Interface format is selected via the FMT[1:0] register bits:  
REGISTER ADDRESS  
R10 (0Ah)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
1:0 DACFMT  
[1:0]  
01  
Interface format Select  
00 : right justified mode  
01: left justified mode  
10: I2S mode  
0001010  
DAC Interface Control  
R11 (0Bh)  
1:0 ADCFMT  
[1:0]  
01  
11: DSP mode A or B  
0001011  
ADC Interface Control  
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of  
ADCLRC/DACLRC. If this bit is set high, the expected polarity of ADCLRC/DACLRC will be the  
opposite of that shown Figure 12, Figure 13, etc. Note that if this feature is used as a means of  
swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes,  
the LRP register bit is used to select between modes A and B.  
REGISTER ADDRESS  
R10 (0Ah)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
In left/right/ I2S modes:  
2
DACLRP  
0
0001010  
ADCLRC/DACLRC Polarity (normal)  
DAC Interface Control  
0 : normal ADCLRC/DACLRC  
polarity  
1: inverted ADCLRC/DACLRC  
polarity  
R11 (0Bh)  
0001011  
2
ADCLRP  
0
In DSP mode:  
ADC Interface Control  
0 : DSP mode A  
1: DSP mode B  
By default, ADCLRC, DACLRC and DIN are sampled on the rising edge of ADCBCLK and  
DACBCLK and should ideally change on the falling edge. Data sources that change  
ADCLRC/DACLRC and DIN on the rising edge of ADCBCLK/DACBCLK can be supported by setting  
the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in  
Figure 12, Figure 13, etc.  
REGISTER ADDRESS  
R10 (0Ah)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
BCLK Polarity (DSP modes)  
0 : normal BCLK polarity  
1: inverted BCLK polarity  
3
DACBCP  
0
0001010  
DAC Interface Control  
R11 (0Bh)  
3
ADCBCP  
0
0001011  
ADC Interface Control  
The WL[1:0] bits are used to control the input word length.  
REGISTER ADDRESS  
R10 (0Ah)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
Word Length  
5:4  
DACWL  
[1:0]  
10  
0001010  
00 : 16 bit data  
01: 20 bit data  
10: 24 bit data  
11: 32 bit data  
DAC Interface Control  
R11 (0Bh)  
5:4  
ADCWL  
[1:0]  
10  
0001011  
ADC Interface Control  
Note: If 32-bit mode is selected in right justified mode, the WM8590 defaults to 24 bits.  
In all modes, the data is signed 2’s complement. The digital filters always input 24-bit data. If the  
DAC is programmed to receive 16 or 20 bit data, the WM8590 pads the unused LSBs with zeros. If  
the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.  
Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that ADCLRC/DACLRC is  
high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs.  
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A number of options are available to control how data from the Digital Audio Interface is applied to  
the DAC.  
MASTER MODES  
Control bit ADCMS selects between audio interface Master and Slave Modes for ADC. In ADC  
Master mode ADCLRC and ADCBCLK are outputs and are generated by the WM8590. In Slave  
mode ADCLRC and ADCBCLK are inputs to WM8590.  
REGISTER ADDRESS  
R12 (0Ch)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
8
ADCMS  
1
Audio Interface Master/Slave Mode  
select for ADC:  
0001100  
0 : Slave Mode  
1: Master Mode  
Interface Control  
Control bit DACMS selects between audio interface Master and Slave Modes for the DAC. In DAC  
Master mode DACLRC and DACBCLK are outputs and are generated by the WM8590. In Slave  
mode DACLRC and DACBCLK are inputs to WM8590.  
REGISTER ADDRESS  
R12 (0Ch)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
7
DACMS  
0
Audio Interface Master/Slave Mode  
select for DAC:  
0001100  
0 : Slave Mode  
1: Master Mode  
Interface Control  
MASTER MODE ADCLRC/DACLRC FREQUENCY SELECT  
In ADC Master mode the WM8590 generates ADCLRC and ADCBCLK, in DAC master mode the  
WM8590 generates DACLRC and DACBCLK. These clocks are derived from the master clock  
(ADCMCLK or DACMCLK). The ratios of ADCMCLK to ADCLRC and DACMCLK to DACLRC are  
set by ADCRATE and DACRATE respectively.  
REGISTER ADDRESS  
R12 (0Ch)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
2:0 ADCRATE[2:0]  
010  
Master Mode MCLK:ADCLRC  
Ratio Select:  
0001100  
010: 256fs  
011: 384fs  
100: 512fs  
101: 768fs  
ADCLRC and DACLRC  
Frequency Select  
6:4 DACRATE[2:0]  
010  
Master Mode MCLK:DACLRC  
Ratio Select:  
000: 128fs  
001: 192fs  
010: 256fs  
011: 384fs  
100: 512fs  
101: 768fs  
ADC OVERSAMPLING RATE SELECT  
For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the  
ADC signal processing oversample rate to 64fs. Operation is explained further in Table 5.  
REGISTER ADDRESS  
BIT  
DEFAULT  
DESCRIPTION  
LABEL  
R12 (0Ch)  
0001100  
3
ADCOSR  
0
ADC Oversampling Rate Select  
0: 128x oversampling  
ADC Oversampling Rate  
1: 64x oversampling  
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DAC OVERSAMPLING RATE SELECT  
Control bit DACOSR allows the user to select the DAC internal signal processing oversampling rate.  
Operation is described in Table 5 and Table 6.  
REGISTER ADDRESS  
BIT  
DEFAULT  
DESCRIPTION  
LABEL  
R10 (0Ah)  
0001010  
8
DACOSR  
0
DAC Oversampling Rate Select  
0: 128x oversampling  
DAC Oversampling Rate  
1: 64x oversampling  
MUTE MODES  
Setting MUTE for the DAC will apply a ‘soft’ mute to the input of the digital filters of the channel  
muted.  
REGISTER ADDRESS  
R9 (09h)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
DAC Soft Mute Select  
0 : Normal Operation  
1: Soft mute enabled  
3
DMUTE  
0
0001001  
DAC Mute  
1.5  
1
0.5  
0
-0.5  
-1  
-1.5  
-2  
-2.5  
0
0.001  
0.002  
0.003  
0.004  
0.005  
0.006  
Time(s)  
Figure 20 Application and Release of Soft Mute  
Figure 20 shows the application and release of DMUTE whilst a full amplitude sinusoid is being  
played at 48kHz sampling rate. When DMUTE (lower trace) is asserted, the output (upper trace)  
begins to decay exponentially from the DC level of the last input sample. The output will decay  
towards VMID with a time constant of approximately 64 input samples. If DMUTE is applied to both  
channels for 1024 or more input samples the DAC will be muted if IZD is set. When DMUTE is de-  
asserted, the output will restart immediately from the current input sample.  
Note that all other means of muting the DAC: setting the PL[3:0] bits to 0, setting the PDWN bit or  
setting attenuation to 0 will cause much more abrupt muting of the output.  
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ADC MUTE  
Each ADC channel also has an individual mute control bit, which mutes the input to the ADC PGA.  
By setting the LRBOTH bit (reg22, bit 8) both channels can be muted simultaneously.  
REGISTER ADDRESS  
R21 (15h)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
ADC Mute Select  
1
MUTELA  
0
0010101  
0 : Normal Operation  
1: mute ADC left  
ADC Mute Left  
R21 (15h)  
0
MUTERA  
0
ADC Mute Select  
0001111  
0 : Normal Operation  
1: mute ADC right  
ADC Mute Right  
DE-EMPHASIS MODE  
The De-emphasis filter for the DAC is enabled under the control of DEEMP.  
REGISTER ADDRESS  
R9 (09h)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
De-emphasis Mode Select:  
0 : Normal Mode  
0
DEEMPH  
0
0001001  
DAC De-emphasis  
Control  
1: De-emphasis Mode  
Refer to Figure 30, Figure 31, Figure 32, Figure 33, Figure 34 and Figure 35 for details of the De-  
Emphasis modes at different sample rates.  
POWERDOWN MODE AND ADC/DAC DISABLE  
Setting the PDWN register bit immediately powers down the WM8590, including the references,  
overriding all other powerdown control bits. All trace of the previous input samples is removed, but all  
control register settings are preserved. When PDWN is cleared, the digital filters will be re-initialised.  
It is recommended that the buffer, ADC and DAC are powered down before setting PDWN.  
REGISTER ADDRESS  
R13 (0Dh)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
Power Down Mode Select:  
0 : Normal Mode  
0
PDWN  
0
0001101  
Powerdown Control  
1: Power Down Mode  
The ADC and DAC may also be powered down by setting the ADCPD and DACPD disable bits.  
Setting ADCPD will disable the ADC and select a low power mode. The ADC digital filters will be  
reset and will reinitialise when ADCPD is reset. The DAC has a separate disable DACPD. Setting  
DACPD will disable the DAC, mixer and output PGAs. Resetting DACPD will reinitialise the digital  
filters.  
REGISTER ADDRESS  
R13 (0Dh)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
ADC Powerdown:  
1
ADCPD  
0
0001101  
0 : Normal Mode  
1: Power Down Mode  
DAC Powerdown:  
Powerdown Control  
2
DACPD  
0
0 : Normal Mode  
1: Power Down Mode  
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DIGITAL ATTENUATOR CONTROL MODE  
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and  
right channel DACs from the next audio input sample. No update to the attenuation registers is  
required for ATC to take effect.  
REGISTER ADDRESS  
R7 (07h)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
1
ATC  
0
Attenuator Control Mode:  
0000111  
0 : Right channel use Right  
attenuation  
DAC Channel Control  
1: Right Channel use Left  
Attenuation  
INFINITE ZERO DETECT ENABLE  
Setting the IZD register bit will enable the internal infinite zero detect function:  
REGISTER ADDRESS  
R7 (07h)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
Infinite Zero Mute Enable  
0 : disable infinite zero mute  
1: enable infinite zero Mute  
2
IZD  
0
0000111  
DAC Channel Control  
With IZD enabled, applying 1024 consecutive zero input samples to the DAC will cause both DAC  
outputs to be muted. Mute will be removed as soon as any channel receives a non-zero input.  
DAC OUTPUT CONTROL  
The DAC output control word determines how the left and right inputs to the audio Interface are  
applied to the left and right DACs:  
REGISTER ADDRESS  
R7 (07h)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
7:4  
PL[3:0]  
1001  
PL[3:0]  
Left  
Right  
Output  
Output  
0000111  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Mute  
Left  
Mute  
DAC Control  
Mute  
Mute  
Mute  
Left  
Right  
(L+R)/2  
Mute  
Left  
Left  
Right  
(L+R)/2  
Mute  
Left  
Left  
Left  
Right  
Right  
Right  
Right  
(L+R)/2  
(L+R)/2  
(L+R)/2  
(L+R)/2  
Right  
(L+R)/2  
Mute  
Left  
Right  
(L+R)/2  
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DAC DIGITAL VOLUME CONTROL  
The DAC volume may also be adjusted in the digital domain using independent digital attenuation  
control registers  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R3 (03h)  
0000011  
7:0  
LDA[7:0]  
11111111  
(0dB)  
Digital Attenuation data for Left channel DACL in 0.5dB steps. See  
Table 9  
Digital  
Attenuation  
8
UPDATED  
Not latched  
Controls simultaneous update of Attenuation Latches  
0: Store LDA in intermediate latch (no change to output)  
1: Store LDA and update attenuation on both channels  
DACL  
R4 (04h)  
0000100  
7:0  
8
RDA[6:0]  
11111111  
(0dB)  
Digital Attenuation data for Right channel DACR in 0.5dB steps. See  
Table 9  
Digital  
Attenuation  
DACR  
UPDATED  
Not latched  
Controls simultaneous update of Attenuation Latches  
0: Store RDA in intermediate latch (no change to output)  
1: Store RDA and update attenuation on both channels.  
R5 (05h)  
0000101  
7:0  
8
MDA[7:0]  
11111111  
(0dB)  
Digital Attenuation data for DAC channels in 0.5dB steps. See Table  
9
Master  
Digital  
Attenuation  
UPDATED  
Not latched  
Controls simultaneous update of Attenuation Latches  
0: Store gain in intermediate latch (no change to output)  
1: Store gain and update attenuation on channels.  
(both channels)  
The volume update circuit of the WM8590 has two registers LDA and RDA. These can be accessed  
individually by writing to registers R3 and R4, or simultaneously by writing to R5 (MDA - Master  
Digital Attenuation). Writing to R5 will overwrite the contents of R3 and R4. There is no separate  
MDA register.  
L/RDA[7:0]  
ATTENUATION LEVEL  
00(hex)  
-∞ dB (mute)  
01(hex)  
-127dB  
:
:
:
:
:
:
FE(hex)  
FF(hex)  
-0.5dB  
0dB  
Table 9 Digital Volume Control Attenuation Levels  
The digital volume control also incorporates a zero cross detect circuit which detects a transition  
through the zero point before updating the digital volume control with the new volume. This is  
enabled by control bit DZCEN.  
REGISTER ADDRESS  
R7 (07h)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
0
DZCEN  
0
DAC Digital Volume Zero Cross  
Enable:  
0000111  
0: Zero cross detect disabled  
1: Zero cross detect enabled  
DAC Control  
DAC OUTPUT PHASE  
The DAC Phase control word determines whether the output of the DAC is non-inverted or inverted  
REGISTER ADDRESS  
R6 (06h)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
1:0  
PHASE  
[1:0]  
00  
Bit  
0
DAC  
Phase  
0000110  
DACL  
1 = invert  
1 = invert  
DAC Phase  
1
DACR  
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ADC GAIN CONTROL  
The ADC has an analogue input PGA and digital gain control for each stereo channel. Both the  
analogue and digital gains are adjusted by the same register, LAG for the left and RAG for the right.  
The analogue PGA has a range of +24dB to -21dB in 0.5dB steps. The digital gain control allows  
further attenuation (after the ADC) from -21.5dB to -103dB in 0.5dB steps. Table 10 shows how the  
register maps the analogue and digital gains.  
LAG/RAG[7:0]  
ATTENUATION  
LEVEL (AT  
OUTPUT)  
ANALOGUE PGA  
DIGITAL  
ATTENUATION  
00(hex)  
01(hex)  
:
-∞ dB (mute)  
-103dB  
-21dB  
-21dB  
:
Digital mute  
-82dB  
:
:
-21.5dB  
-21dB  
:
A4(hex)  
A5(hex)  
:
-21dB  
-21dB  
:
-0.5dB  
0dB  
:
CF(hex)  
:
0dB  
0dB  
0dB  
:
:
:
FE(hex)  
FF(hex)  
+23.5dB  
+24dB  
+23.5dB  
+24dB  
0dB  
0dB  
Table 10 Analogue and Digital Gain Mapping for ADC  
In addition a zero cross detect circuit is provided for the input PGA. When ZCLA/ZCRA is set with a  
write, the gain will update only when the input signal approaches zero (midrail). This minimises  
audible clicks and ‘zipper’ noise as the gain values change. The zero cross circuit can be configured  
to detect a “zero” when the positive (xINP) and negative (xINN) channels cross, or when the negative  
channel crosses the VMID voltage, by setting ZCSCRL/ZCSCRR.  
A timeout clock is also provided which will generate an update after a minimum of 131072 master  
clocks (= ~10.5ms with a master clock of 12.288MHz). The timeout clock may be disabled by setting  
TOD.  
REGISTER ADDRESS  
R7 (07h)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
3
TOD  
0
Analogue PGA Zero Cross Detect  
Timeout Disable  
0000111  
0 : Timeout enabled  
1: Timeout disabled  
Timeout Clock Disable  
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WM8590  
Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to  
write the same attenuation value to both left and right volume control registers, saving on software  
writes.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R14 (0Eh)  
0001110  
Attenuation  
ADCL  
7:0  
LAG[7:0]  
11001111  
(0dB)  
Attenuation Data for Left Channel ADC Gain in 0.5dB steps. See  
Table 10.  
8
ZCLA  
0
Left Channel ADC Zero Cross Enable:  
0: Zero cross disabled  
1: Zero cross enabled  
R15 (0Fh)  
0001111  
7:0  
8
RAG[7:0]  
ZCRA  
11001111  
(0dB)  
Attenuation data for right channel ADC gain in 0.5dB steps. See  
Table 10.  
Attenuation  
ADCR  
0
0
0
0
Right Channel ADC Zero Cross Enable:  
0: Zero cross disabled  
1: Zero cross enabled  
Mute for Right Channel ADC  
0: Mute Off  
R21 (15h)  
0010101  
0
1
2
MUTERA  
MUTELA  
ZCSCRR  
ADC Input Mux  
1: Mute on  
Mute for Left Channel ADC  
0: Mute Off  
1: Mute on  
Zero Cross reference for right channel  
0: Zero Cross detector compares positive and negative  
inputs  
1: Zero Cross detector compares negative input to VMID  
Zero Cross reference for left channel  
3
8
ZCSCRL  
LRBOTH  
0
0
0: Zero Cross detector compares positive and negative  
inputs  
1: Zero Cross detector compares negative input to VMID  
Right Channel Input PGA Controlled by Left Channel Register  
0: Right channel uses RAG and MUTERA  
1: Right channel uses LAG and MUTELA  
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ADC/DAC SYNCHRONIZATION  
The WM8590 has a range of features which can be configured to enhance the performance of the  
ADC and DAC when operated simultaneously.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R11 (0Bh)  
6
ADCMCLKINV  
0
ADCMCLK Polarity:  
0: non-inverted  
1: inverted  
ADC Interface  
Control  
7
0
4
5
DACSYNCEN  
ADCSYNCEN  
ADCMCLK2DAC  
ADCMCLKX2  
0
0
0
0
Enable the DAC Synchronizer:  
0: Disabled  
1: Enabled  
R28 (1Ch)  
0011100  
Enable the ADC Synchronizer:  
0: Disabled  
ADC/DAC  
1: Enabled  
Synchronization  
Set both ADC and DAC to use ADCMCLK:  
0: DAC uses DACMCLK  
1: DAC uses ADCMCLK  
Allows DAC synchronizer to synchronize to ADC operating at  
2x DAC rate:  
0: Disabled  
1: Enabled  
6
7
DACMCLKINV  
DACMCLKX2  
0
0
DACMCLK Polarity:  
0: non-inverted  
1: inverted  
Allows ADC synchronizer to synchronize to DAC operating at  
2x ADC rate:  
0: Disabled  
1: Enabled  
8
DACMCLK2ADC  
0
Set both DAC and ADC to use DACMCLK:  
0: ADC uses ADCMCLK  
1: ADC uses DACMCLK  
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WM8590  
LIMITER / AUTOMATIC LEVEL CONTROL (ALC)  
The WM8590 has an automatic pga gain control circuit, which can function as a peak limiter or as an  
automatic level control (ALC). In peak limiter mode, a digital peak detector detects when the input  
signal goes above a predefined level and will ramp the pga gain down to prevent the signal becoming  
too large for the input range of the ADC. When the signal returns to a level below the threshold, the  
pga gain is slowly returned to its starting level. The peak limiter cannot increase the pga gain above  
its static level.  
input  
signal  
PGA  
gain  
signal  
Limiter  
after  
threshold  
PGA  
attack  
time  
decay  
time  
Figure 21 Limiter Operation  
In ALC mode, the circuit aims to keep a constant recording volume irrespective of the input signal  
level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC  
input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain  
if necessary.  
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input  
signal  
PGA  
gain  
signal  
after  
ALC  
ALC  
target  
level  
hold decay  
time time  
attack  
time  
Figure 22 ALC Operation  
The gain control circuit is enabled by setting the LCMODE control bit. The user can select between  
Limiter mode and three different ALC modes using the LCSEL control bits.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R17 (11h)  
0010001  
8
LCMODE  
1
ALC/Limiter Select  
0 = ALC Mode  
ALC Control 2  
R16 (10h)  
1 = Limiter Mode  
LC Function Select  
00 = Disabled  
8:7  
LCSEL  
11  
0010000  
ALC Control 1  
01 = Right channel only  
10 = Left channel only  
11 = Stereo  
Both the ALC and Limiter functions can operate in stereo or single channel modes. In stereo mode,  
the ALC/Limiter operates on both PGAs. In single channel mode, only one PGA is controlled by the  
ALC/Limiter mechanism, while the other channel runs independently with its PGA gain set through  
the control register.  
When enabled, the threshold for the limiter or target level for the ALC is programmed using the LCT  
control bits. This allows the threshold/target level to be programmed between 0dB and -22.5dB in  
1.5dB steps. Note that for the ALC, target levels of 0dB and -1.5dB give a threshold of -3dB. This is  
because the ALC can give erroneous operation if the target level is set too high.  
When disabled, the last gain level programmed by the ALC/Limiter will remain stored in the input  
PGAs. The desired fixed gain level must then be programmed manually via registers R14 and R15.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R16 (10h)  
0010000  
3:0  
LCT[3:0]  
1110  
Limiter Threshold/ALC Target Level in  
1.5dB Steps:  
(-1.5dB)  
0000: -22.5dB FS  
0001: -21dB FS  
…
ALC Control 1  
1101: -3dB FS  
1110: -1.5dB FS  
1111: 0dB FS  
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ATTACK AND DECAY TIMES  
The limiter and ALC have different attack and decay times which determine their operation. However,  
the attack and decay times are defined slightly differently for the limiter and for the ALC. DCY and  
ATK control the decay and attack times, respectively.  
Decay time (Gain Ramp-Up). When in ALC mode, this is defined as the time that it takes for the  
PGA gain to ramp up across 90% of its range (e.g. from –21dB up to +20 dB). When in limiter mode,  
it is defined as the time it takes for the gain to ramp up by 6dB.  
The decay time can be programmed in power-of-two (2n) steps. For the ALC this gives times from  
33.6ms, 67.2ms, 134.4ms etc. to 34.41s. For the limiter this gives times from 1.2ms, 2.4ms etc., up  
to 1.2288s.  
Attack time (Gain Ramp-Down) When in ALC mode, this is defined as the time that it takes for the  
PGA gain to ramp down across 90% of its range (e.g. from +20dB down to -21dB gain). When in  
limiter mode, it is defined as the time it takes for the gain to ramp down by 6dB.  
The attack time can be programmed in power-of-two (2n) steps, from 8.4ms, 16.8ms, 33.6ms etc. to  
8.6s for the ALC and from 250us, 500us, etc. up to 256ms.  
The time it takes for the recording level to return to its target value or static gain value therefore  
depends on both the attack/decay time and on the gain adjustment required. If the gain adjustment is  
small, it will be shorter than the attack/decay time.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R18 (12h)  
0010010  
ALC  
3:0  
ATK[3:0]  
0010  
LC Attack (Gain Ramp-down) Time  
ALC mode  
Limiter Mode  
0000: 250us  
0001: 500us…  
0010: 1ms  
0000: 8.4ms  
Control 3  
0001: 16.8ms  
0010: 33.6ms…  
(time doubles with  
every step)  
(time doubles with  
every step)  
1010 or higher:  
8.6s  
1010 or higher: 256ms  
7:4  
DCY [3:0]  
1001  
LC Decay (Gain Ramp-up) Time  
ALC mode  
Limiter mode  
0000: 33.5ms  
0001: 67.2ms  
0010: 134.4ms  
0000: 1.2ms  
0001: 2.4ms  
0010: 4.8ms ….(time  
….(time doubles for doubles for every  
every step)  
step)  
1001: 17.15s  
1001: 614.4ms  
1010 or higher:  
34.3s  
1010 or higher:  
1.2288s  
ZERO CROSS  
The PGA has a zero cross detector to prevent gain changes introducing noise to the signal. In ALC  
mode the register bit ALCZC allows this to be turned off if desired.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R17 (11h)  
0010001  
7
ALCZC  
1
PGA Zero Cross Enable:  
0 : disabled  
(enabled)  
ALC Control 2  
1: enabled  
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MAXIMUM GAIN (ALC ONLY) AND MAXIMUM ATTENUATION  
To prevent low level signals being amplified too much by the ALC, the MAXGAIN register sets the  
upper limit for the gain. This prevents low level noise being over-amplified. The MAXGAIN register  
has no effect on the limiter operation.  
The MAXATTEN register sets a limit for the amount of attenuation below the static gain level that the  
limiter can apply. The MAXATTEN register has no effect in ALC mode.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R16 (10h)  
0010000  
6:4  
MAXGAIN  
111  
(+24dB)  
Set Maximum Gain for the PGA (ALC  
only):  
111 : +24dB  
110 : +20dB  
…..(-4dB steps)  
010 : +4dB  
001 : 0dB  
ALC Control 1  
000 : 0dB  
R20 (14h)  
0010100  
3:0  
MAXATTEN  
0110  
Maximum Attenuation of PGA (Limiter  
only)  
(-6dB)  
Limiter (attenuation below static)  
Limiter Control  
0000 to 0011  
0100  
-3dB  
-4dB  
….  
(-1dB steps)  
-14dB  
1110  
1111  
-15dB  
When disabled, the last gain level programmed by the ALC/Limiter will remain stored in the input  
PGAs. The desired fixed gain level must then be programmed manually via registers R14 and R15.  
SOFTWARE REGISTER RESET  
Writing any value to register 0010111 will cause a register reset, resetting all register bits to their  
default values.  
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REGISTER MAP  
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The  
WM8590 can be configured using the Control Interface. All unused bits should be set to ‘0’.  
REGISTER  
B
B
B
B
B
B
B
9
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
DEFAULT  
(HEX)  
0FF  
15 14 13 12 11 10  
R3 (03h)  
R4 (04h)  
R5 (05h)  
R6 (06h)  
R7 (07h)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
UPDATED  
LDA[7:0]  
UPDATED  
RDA[7:0]  
MDA[7:0]  
0FF  
UPDATED  
0FF  
0
0
0
0
0
0
0
0
0
PHASE[1:0]  
000  
PL[3:0]  
TOD  
IZD  
ATC  
DZCEN  
090  
ZFLAG  
POL  
004  
R9 (09h)  
0
0
0
1
0
0
1
0
0
0
0
0
DMUTE  
DZFM [1:0]  
DEEMPH  
R10 (0Ah)  
R11 (0Bh)  
R12 (0Ch)  
R13 (0Dh)  
R14 (0Eh)  
R15 (0Fh)  
R16 (10h)  
R17 (11h)  
R18 (12h)  
R20 (14h)  
R21 (15h)  
R23 (17h)  
R28 (1Ch)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
1
0
DACOSR  
ADCHPD  
ADCMS  
0
DACWL[1:0]  
ADCWL[1:0]  
DACBCP DACLRP  
ADCBCP ADCLRP  
ADCOSR  
DACFMT[1:0]  
ADCFMT[1:0]  
ADCRATE[2:0]  
PDWN  
022  
022  
DACSYNCEN ADCMCLKINV  
DACMS  
0
DACRATE[2:0]  
122  
0
0
0
0
DACPD ADCPD  
000  
ZCLA  
LAG[7:0]  
RAG[7:0]  
0CF  
0CF  
1FE  
180  
ZCRA  
LCSEL[1:0]  
MAXGAIN[2:0]  
0
LCT[3:0]  
LCMODE  
ALCZC  
0
0
0
0
0
0
0
0
DCY[3:0]  
ATK[3:0]  
MAXATTEN[3:0]  
ZCSCRL ZCSCRR MUTELA MUTERA  
092  
0
0
0
0
0
0
006  
LRBOTH  
0
0
000  
SOFTWARE RESET  
not reset  
000  
DACMCLK2ADC DACMCLKX2 DACMCLKINV DCMCLKX2 DCMCLK2DAC  
BCLK_RATE  
0
ADCSYNCEN  
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REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R3 (03h)  
0000011  
7:0  
LDA[7:0]  
11111111  
(0dB)  
Digital Attenuation Data for Left Channel DACL in 0.5dB Steps  
Digital  
Attenuation  
DACL  
8
7:0  
8
UPDATED  
RDA[6:0]  
UPDATED  
MDA[7:0]  
UPDATED  
PHASE  
Not latched  
Controls Simultaneous Update of all Attenuation Latches:  
0: Store LDA1 in intermediate latch (no change to output)  
1: Store LDA1 and update attenuation on all channels  
R4 (04h)  
0000100  
11111111  
(0dB)  
Digital Attenuation Data for Right Channel DACR in 0.5dB Steps  
Digital  
Attenuation  
DACR  
Not latched  
Controls Simultaneous Update of all Attenuation Latches:  
0: Store RDA1 in intermediate latch (no change to output)  
1: Store RDA1 and update attenuation on all channels  
R5 (05h)  
0000101  
7:0  
8
11111111  
(0dB)  
Digital Attenuation Data for all DAC Channels in 0.5dB Steps  
Master  
Digital  
Attenuation  
Not latched  
Controls Simultaneous Update of all Attenuation Latches:  
0: Store gain in intermediate latch (no change to output)  
1: Store gain and update attenuation on all channels  
(All Channels)  
R6 (06h)  
0000110  
1:0  
0
00  
0
Controls Phase of DAC Outputs (LEFT, RIGHT Channel):  
0: Sets non inverted output phase  
Phase Swaps  
1: inverts phase of DAC output  
R7 (07h)  
0000111  
DZCEN  
DAC Digital Volume Zero Cross Enable:  
0: Zero Cross detect disabled  
DAC Control  
1: Zero Cross detect enabled  
ATC  
IZD  
0
0
Attenuator Control:  
1
2
0: All DACs use attenuations as programmed  
1: Right DAC uses left DAC attenuations  
Infinite Zero Detection Circuit Control and Automute Control:  
0: Infinite zero detect automute disabled  
1: Infinite zero detect automute enabled  
DAC and ADC Analogue Zero Cross Detect Timeout Disable:  
0 : Timeout enabled  
3
TOD  
0
1: Timeout disabled  
7:4  
PL[3:0]  
1001  
DAC Output Control  
PL[3:0]  
Left  
Right  
PL[3:0]  
Left  
Right  
Output  
Output  
Output  
Output  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
Mute  
Left  
Mute  
Mute  
Mute  
Mute  
Left  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Mute  
Left  
Right  
Right  
Right  
(L+R)/2  
Mute  
Left  
Right  
(L+R)/2  
Mute  
Left  
Right  
Right  
(L+R)/2  
(L+R)/2  
(L+R)/2  
(L+R)/2  
Left  
Right  
(L+R)/2  
Left  
Right  
(L+R)/2  
Left  
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Production Data  
WM8590  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
De-emphasis Mode Select:  
R9 (09h)  
0001001  
0
DEEMPH  
0
0 : Normal mode  
DAC Control  
1: De-emphasis mode  
2:1  
DZFM  
00  
DZFM  
ZFLAG1  
Disabled  
ZFLAG2  
00  
01  
10  
11  
Disabled  
Left channels zero  
Both channels zero  
Either channel zero  
Right channels zero  
Both channels zero  
Either channel zero  
3
4
DMUTE  
0
0
DAC Channel Soft Mute Enables:  
0: Mute disabled  
1: Mute enabled  
ZFLAGPOL  
ZFLAG polarity  
ZFLAGPOL  
ZFLAGL  
ZFLAGR  
Pin pulls low to indicate zero conidition, high  
impedance otherwise  
0
Pin is high impedance when zero condition  
detected, pulls low otherwise  
1
R10 (0Ah)  
0001010  
1:0  
DACFMT[1:0]  
DACLRP  
01  
0
DAC Interface Format Select:  
00: Right justified mode  
01: Left justified mode  
DAC Interface  
Control  
10: I2S mode  
11: DSP mode  
2
DACLRC Polarity or DSP Mode A or B Select  
Left Justified / Right Justified /  
I2S:  
DSP Mode:  
0: Mode A  
1: Mode B  
0: Standard DACLRC Polarity  
1: Inverted DACLRC Polarity  
DAC BITCLK Polarity:  
3
DACBCP  
0
0: Normal – DIN and DACLRC sampled on rising edge of  
DACBCLK  
1: Inverted - DIN and DACLRC sampled on falling edge of  
DACBCLK  
5:4  
DACWL[1:0]  
10  
DAC Input Word Length:  
00: 16-bit Mode  
01: 20-bit Mode  
10: 24-bit Mode  
11: 32-bit Mode (not supported in right justified mode)  
8
DACOSR  
0
DAC Oversample Rate Select:  
0: 128x oversampling  
1: 64x oversapmling  
R11 (0Bh)  
0001011  
1:0  
ADCFMT[1:0]  
01  
ADC Interface Format Select:  
00: Right justified mode  
01: Left justified mode  
ADC Interface  
Control  
10: I2S mode  
11: DSP mode  
2
ADCLRP  
0
ADCLRC Polarity or DSP Mode A or B Select  
Left Justified / Right Justified /  
I2S:  
DSP Mode:  
0: Mode A  
0: Standard ADCLRC polarity  
1: Inverted ADCLRC polarity  
1: Mode B  
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WM8590  
Production Data  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
3
ADCBCP  
0
ADC BITCLK Polarity:  
0: Normal – ADCLRC sampled on rising edge of  
ADCBCLK; DOUT changes on falling edge of ADCBCLK  
1: Inverted - ADCLRC sampled on falling edge of  
ADCBCLK; DOUT changes on rising edge of ADCBCLK  
5:4  
ADCWL[1:0]  
10  
ADC Input Word Length:  
00: 16-bit mode  
01: 20-bit mode  
10: 24-bit mode  
11: 32-bit mode (not supported in right justified mode)  
6
7
ADCMCLKINV  
DACSYNCEN  
ADCHPD  
0
0
ADCMCLK Polarity:  
0: non-inverted  
1: inverted  
Enable the DAC synchronizer:  
0: Disabled  
1: Enabled  
8
0
ADC High Pass Filter Powerdown:  
0: HP Filter Enabled  
1: HP Filter Disabled  
R12 (0Ch)  
0001100  
2:0  
ADCRATE[2:0]  
010  
Master Mode ADCMCLK:ADCLRC Ratio Select:  
010: 256fs  
Master Mode  
Control  
011: 384fs  
100: 512fs  
101: 768fs  
3
ADCOSR  
0
ADC Oversample Rate Select:  
0: 128x oversampling  
1: 64x oversampling  
6:4  
DACRATE[2:0]  
010  
Master Mode DACMCLK:DACLRC Ratio Select:  
000: 128fs  
001: 192fs  
010: 256fs  
011: 384fs  
100: 512fs  
101: 768fs  
7
8
0
DACMS  
ADCMS  
PDWN  
0
1
0
DAC Master/Slave Interface Mode Select:  
0: Slave Mode – DACLRC and DACBCLK are inputs  
1: Master Mode –DACLRC and DACBCLK are outputs  
ADC Master/Slave Interface Mode Select:  
0: Slave Mode – ADCLRC and ADCBCLK are inputs  
1: Master Mode – ADCLRC and ADCBCLK are outputs  
R13 (0Dh)  
0001101  
Chip Powerdown Control (works in tandem with ADCPD and  
DACPD):  
0: All circuits running, outputs are active  
1: All circuits in power save mode, outputs muted  
ADC Powerdown:  
PWR Down  
Control  
1
2
ADCPD  
DACPD  
0
0
0: ADC enabled  
1: ADC disabled  
DAC Powerdown:  
0: DAC enabled  
1: DAC disabled  
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Production Data  
WM8590  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R14 (0Eh)  
0001110  
7:0  
LAG[7:0]  
11001111  
(0dB)  
Attenuation Data for Left Channel ADC Gain in 0.5dB Steps:  
00000000 : digital mute  
00000001 : -103dB  
Attenuation  
ADCL  
………..  
11001111 : 0dB  
…………  
11111110 : +23.5dB  
11111111 : +24dB  
8
ZCLA  
0
Left ADC Zero Cross Enable:  
0: Zero cross disabled  
1: Zero cross enabled  
Attenuation Data for Right Channel ADC Gain in 0.5dB Steps:  
00000000 : digital mute  
00000001 : -103dB  
R15 (0Fh)  
0001111  
7:0  
RAG[7:0]  
11001111  
(0dB)  
Attenuation  
ADCR  
………..  
11001111 : 0dB  
…………  
11111110 : +23.5dB  
11111111 : +24dB  
8
ZCRA  
0
Right ADC Zero Cross Enable:  
0: Zero cross disabled  
1: Zero cross enabled  
Limiter Threshold/ALC Target Level in 1.5dB Steps:  
0000: -22.5dB FS  
R16 (10h)  
0010000  
3:0  
LCT[3:0]  
1110  
(-1.5dB)  
ALC Control 1  
0001: -21dB FS  
…
1101: -3dB FS  
1110: -1.5dB FS  
1111: 0dB FS  
6:4  
MAXGAIN[2:0]  
111 (+24dB) Set Maximum Gain of PGA:  
111 : +24dB  
110 : +20dB  
….(-4dB steps)  
010 : +4dB  
001 : 0dB  
000 : 0dB  
8:7  
LCSEL[1:0]  
11  
LC Function Select  
00 = Disabled  
(Stereo)  
01 = Right channel only  
10 = Left channel only  
11 = Stereo  
R17 (11h)  
0010001  
7
8
ALCZC  
1
ALC Uses Zero Cross Detection Circuit.  
(zero cross on)  
1
ALC Control 2  
LCMODE  
ALC/Limiter Select:  
0 = ALC Mode  
1 = Limiter Mode  
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Production Data  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R18 (12h)  
0011000  
3:0  
ATK[3:0]  
0010  
(33.6ms/  
1ms)  
ALC/Limiter Attack (gain ramp-down) Time  
ALC Mode:  
Limiter Mode:  
ALC Control 3  
0000: 8.4ms  
0000: 250us  
0001: 500us…  
0010: 1ms  
0001: 16.8ms  
0010: 33.6ms…  
(time doubles with every step)  
1010 or higher: 8.6s  
(time doubles with every step)  
1010 or higher: 256ms  
7:4  
DCY[3:0]  
1001  
ALC/Limiter Decay (gain ramp up) Time  
(17.15s/  
614.4ms)  
ALC Mode:  
Limiter Mode:  
0000: 33.5ms  
0001: 67.2ms  
0000: 1.2ms  
0001: 2.4ms  
0010: 134.4ms ….(time  
doubles for every step)  
0010: 4.8ms ….(time doubles  
for every step)  
1001: 17.15s  
1001: 614.4ms  
1010 or higher: 34.3s  
1010 or higher: 1.2288s  
R20 (14h)  
0010100  
3:0  
MAXATTEN  
[3:0]  
0110  
Maximum Attenuation of PGA (Limiter only)  
Limiter (attenuation below static)  
(-6dB)  
Limiter  
Control  
0000 to 0011  
0100  
-3dB  
-4dB  
….  
(-1dB steps)  
-14dB  
1110  
1111  
-15dB  
R21 (15h)  
0010101  
0
1
2
MUTERA  
MUTELA  
ZCSCRR  
0
0
0
Mute for Right Channel ADC:  
0: Mute off  
ADC Mux  
Control  
1: Mute on  
Mute for Left Channel ADC:  
0: Mute off  
1: Mute on  
Zero Cross Reference for Right Channel:  
0: Zero Cross detector compares positive and negative  
inputs  
1: Zero Cross detector compares negative input to VMID  
Zero Cross Reference for Left Channel:  
3
ZCSCRL  
0
0: Zero Cross detector compares positive and negative  
inputs  
1: Zero Cross detector compares negative input to VMID  
Right Channel Input PGA Controlled by Left Channel Register:  
0: Right channel uses RAG and MUTERA  
8
LRBOTH  
RESET  
0
1: Right channel uses LAG and MUTELA  
R23 (17h)  
0010111  
[8:0]  
Not reset  
Writing any value to this register will apply a reset to the device  
registers.  
Software  
Reset  
R28 (1Ch)  
0011100  
0
ADCSYNCEN  
BCLK_RATE  
0
Enable the ADC Synchronizer:  
0: Disabled  
ADC/DAC  
1: Enabled  
Synchronization  
3:2  
00  
Set ADCBCLK and DACBCLK output rate in Master Mode:  
00: BCLK = MCLK/4 (MCLK in DSP Mode)  
01: BCLK = MCLK/4 (MCLK in DSP Mode)  
10: BCLK = 64fs  
11: BCLK = 128fs  
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Production Data  
WM8590  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
4
ADCMCLK2DAC  
0
Set both ADC and DAC to use ADCMCLK:  
0: DAC uses DACMCLK  
1: DAC uses ADCMCLK  
5
ADCMCLKX2  
0
Allows DAC synchronizer to synchronize to ADC operating at 2x  
DAC rate:  
0: Disabled  
1: Enabled  
6
7
DACMCLKINV  
DACMCLKX2  
0
0
DACMCLK Polarity:  
0: non-inverted  
1: inverted  
Allows ADC synchronizer to synchronize to DAC operating at 2x  
ADC rate:  
0: Disabled  
1: Enabled  
8
DACMCLK2ADC  
0
Set both DAC and ADC to use DACMCLK:  
0: ADC uses ADCMCLK  
1: ADC uses DACMCLK  
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WM8590  
Production Data  
DIGITAL FILTER CHARACTERISTICS  
PARAMETER  
ADC Filter  
Passband  
TEST CONDITIONS  
MIN  
TYP  
MAX  
0.4535fs  
0.01  
UNIT  
0.01 dB  
-6dB  
0
0.5fs  
Passband ripple  
Stopband  
dB  
0.5465fs  
-65  
Stopband Attenuation  
Group Delay  
DAC Filter  
f > 0.5465fs  
dB  
fs  
22  
Passband  
0.05 dB  
-3dB  
0.454fs  
0.05  
0.487 fs  
Passband ripple  
Stopband  
f < 0.444fs  
dB  
0.555fs  
-60  
Stopband Attenuation  
Group Delay  
f > 0.555fs  
dB  
fs  
19  
Table 11 Digital Filter Characteristics  
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WM8590  
DAC FILTER RESPONSES  
0.2  
0.15  
0.1  
0
-20  
-40  
0.05  
0
-60  
-0.05  
-0.1  
-0.15  
-0.2  
-80  
-100  
-120  
0
0.5  
1
1.5  
2
2.5  
3
0
0.05  
0.1  
0.15  
0.2  
0.25  
0.3  
0.35  
0.4  
0.45  
0.5  
Frequency (Fs)  
Frequency (Fs)  
Figure 23 DAC Digital Filter Frequency Response  
-44.1, 48 and 96kHz  
Figure 24 DAC Digital Filter Ripple -44.1, 48 and 96kHz  
0.2  
0
0
-20  
-40  
-60  
-80  
-0.2  
-0.4  
-0.6  
-0.8  
-1  
0
0.2  
0.4  
0.6  
0.8  
1
0
0.05  
0.1  
0.15  
0.2  
0.25  
0.3  
0.35  
0.4  
0.45  
0.5  
Frequency (Fs)  
Frequency (Fs)  
Figure 25 DAC Digital Filter Frequency Response (with  
DACOSR = 1) -192kHz  
Figure 26 DAC Digital Filter Ripple (with DACOSR = 1) -  
192kHz  
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WM8590  
Production Data  
ADC FILTER RESPONSES  
0.02  
0.015  
0.01  
0
-20  
-40  
-60  
-80  
0.005  
0
-0.005  
-0.01  
-0.015  
-0.02  
0
0.05  
0.1  
0.15  
0.2  
0.25  
0.3  
0.35  
0.4  
0.45  
0.5  
0
0.5  
1
1.5  
2
2.5  
3
Frequency (Fs)  
Frequency (Fs)  
Figure 28 ADC Digital Filter Ripple  
Figure 27 ADC Digital Filter Frequency Response  
ADC HIGH PASS FILTER  
The WM8590 has a selectable digital highpass filter to remove DC offsets. The filter response is characterised by the  
following polynomial.  
1 - z-1  
H(z) =  
1 - 0.9995z-1  
0
-5  
-10  
-15  
0
0.0005  
0.001  
Frequency (Fs)  
0.0015  
0.002  
Figure 29 ADC Highpass Filter Response  
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WM8590  
DIGITAL DE-EMPHASIS CHARACTERISTICS  
0
1
0.5  
0
-2  
-4  
-0.5  
-1  
-6  
-1.5  
-2  
-8  
-2.5  
-3  
-10  
0
2
4
6
8
10  
12  
14  
16  
0
2
4
6
8
10  
12  
14  
16  
Frequency (kHz)  
Frequency (kHz)  
Figure 30 De-Emphasis Frequency Response (32kHz)  
Figure 31 De-Emphasis Error (32KHz)  
0
0.4  
0.3  
0.2  
0.1  
0
-2  
-4  
-6  
-0.1  
-0.2  
-0.3  
-0.4  
-8  
-10  
0
5
10  
15  
20  
0
5
10  
15  
20  
Frequency (kHz)  
Frequency (kHz)  
Figure 32 De-Emphasis Frequency Response (44.1KHz)  
Figure 33 De-Emphasis Error (44.1KHz)  
0
1
0.8  
0.6  
0.4  
0.2  
0
-2  
-4  
-6  
-0.2  
-0.4  
-0.6  
-0.8  
-1  
-8  
-10  
0
5
10  
15  
20  
0
5
10  
15  
20  
Frequency (kHz)  
Frequency (kHz)  
Figure 34 De-Emphasis Frequency Response (48kHz)  
Figure 35 De-Emphasis Error (48kHz)  
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Production Data  
APPLICATIONS INFORMATION  
RECOMMENDED EXTERNAL COMPONENTS  
Figure 36 Recommended External Components  
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WM8590  
USE OF ADC/DAC SYNCHRONIZER  
When operating the ADC and DAC simultaneously, the ADC/DAC synchronizer should be configured  
to optimise internal clock phasing and device performance. The synchronizer is controlled by  
registers R11 and R28 and recommended settings are described in Table 12.  
In order for the clock synchronizer to operate, DAC_MCLK and ADC_MCLK must be phase locked  
with coincident clock edges.  
CONFIGURATION  
REGISTER SETTINGS  
DAC fs  
(kHz)  
DAC MCLK  
ADC fs  
(kHz)  
ADC MCLK  
RATE  
RATE  
48  
96  
768fs  
384fs  
1152fs  
768fs  
256fs  
512fs  
512fs  
256fs  
768fs  
48  
48  
48  
48  
48  
48  
48  
48  
48  
384fs  
384fs  
384fs  
384fs  
256fs  
256fs  
256fs  
256fs  
256fs  
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
1*  
1*  
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
32  
1**  
44.1  
48  
0
1*  
0
0
48  
0
0
48  
1*  
1*  
0
0
96  
0
32  
0
Table 12 Synchronizer Configurations  
* In those modes where ADCMCLK2DAC is set, the DAC is driven by the clock signal applied to the  
ADC_MCLK pin. If the DAC is operated in Master mode, the DACRATE bits (R12 [6:4]) must be set  
to match the ADC_MCLK rate.  
** In those modes where DACMCLK2ADC is set, the ADC is driven by the clock signal applied to the  
DAC_MCLK pin. If the ADC is operated in Master mode, the ADCRATE bits (R12 [2:0]) must be set  
to match the DAC_MCLK rate.  
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WM8590  
Production Data  
PACKAGE DIMENSIONS  
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)  
DM007.E  
b
e
28  
15  
E1  
E
GAUGE  
PLANE  
Θ
14  
1
D
0.25  
L
c
A1  
L1  
A A2  
-C-  
0.10 C  
SEATING PLANE  
Dimensions  
(mm)  
NOM  
-----  
Symbols  
MIN  
-----  
0.05  
1.65  
0.22  
0.09  
9.90  
MAX  
A
A1  
A2  
b
c
D
e
E
E1  
L
2.0  
0.25  
1.85  
0.38  
0.25  
10.50  
-----  
1.75  
0.30  
-----  
10.20  
0.65 BSC  
7.80  
7.40  
5.00  
0.55  
8.20  
5.60  
0.95  
5.30  
0.75  
L1  
θ
1.25 REF  
0o  
4o  
8o  
JEDEC.95, MO-150  
REF:  
NOTES:  
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.  
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.  
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.  
D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.  
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WM8590  
IMPORTANT NOTICE  
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or  
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing  
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale  
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation  
of liability.  
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s  
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support  
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by  
government requirements.  
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used  
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical  
components in life support devices or systems without the express written approval of an officer of the company. Life  
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or  
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be  
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support  
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or  
system, or to affect its safety or effectiveness.  
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that  
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual  
property right of WM covering or relating to any combination, machine, or process in which such products or services might  
be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s  
approval, license, warranty or endorsement thereof.  
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and  
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this  
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive  
business practice, and WM is not responsible nor liable for any such use.  
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that  
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and  
deceptive business practice, and WM is not responsible nor liable for any such use.  
ADDRESS:  
Wolfson Microelectronics plc  
Westfield House  
26 Westfield Road  
Edinburgh  
EH11 2QB  
United Kingdom  
Tel :: +44 (0)131 272 7000  
Fax :: +44 (0)131 272 7001  
Email :: sales@wolfsonmicro.com  
PD Rev 4.0 January 2006  
51  
w

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