WM8711 [WOLFSON]
Internet Audio DAC with Integrated Headphone Driver; 互联网音频DAC ，集成耳机驱动器
| 型号： | WM8711 |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | Internet Audio DAC with Integrated Headphone Driver |
| 文件： | 总36页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8711
Internet Audio DAC with Integrated Headphone Driver
Product Preview, Novembert 2000, 1.2
DESCRIPTION
FEATURES
•
Audio Performance
The WM8711 is a low power stereo DAC with an integrated
headphone driver. The WM8711 is designed specifically for
portable MP3 audio and speech players. The WM8711 is
also ideal for MD, CD machines and DAT players.
-
-
-
100dB SNR (‘A’ weighted @ 48kHz) DAC
1.42 – 3.6V Digital Supply Operation
2.7 – 3.6V Analogue Supply Operation
•
•
•
DAC Sampling Frequency: 8KHz – 96KHz
2 or 3-Wire MPU Serial Control Interface
Programmable Audio Data Interface Modes
-
-
-
Stereo 24-bit multi-bit sigma delta DACs are used with
oversampling digital interpolation filters. Digital audio input
word lengths from 16-32 bits and sampling rates from 8KHz
to 96KHz are supported.
I2S, Left, Right Justified or DSP
16/20/24/32 bit Word Lengths
Master or Slave Clocking Mode
Stereo audio outputs are buffered for driving headphones
from a programmable volume control, line level outputs are
also provided along with anti-thump mute and power
up/down circuitry.
•
•
•
•
•
Stereo Audio Outputs
Output Volume and Mute Controls
Highly Efficient Headphone Driver
Playback Mode Power Consumption < 18mW
28-Pin SSOP Package
The device is controlled via a 2 or 3 wire serial interface.
The interface provides access to all features including
volume controls, mutes, de-emphasis and extensive power
management facilities. The device is available in a small 28-
pin SSOP package.
APPLICATIONS
•
•
Portable MP3 Players
CD and Minidisc Players
A USB mode is provided where all audio rates can be
derived from a single 12MHz MCLK, saving on the need for
a PLL or multiple crystals.
BLOCK DIAGRAM
(21)
(16)
(22) (23)
(24)
(14)
(15)
(8) HPVDD
CONTROL INTERFACE
(11) HPGND
WM8711
(19) RLINEIN
(10) RHPOUT
MUTE
H/P
DRIVER
VOL/
MUTE
+6 to -73dB
1 dB Steps
DAC
DAC
Σ
DACDAT (4)
DACLRC (5)
(13) ROUT
(12) LOUT
DIGITAL
FILTERS
BCLK (3)
+6 to -73dB
1 dB Steps
Σ
VOL/
MUTE
H/P
DRIVER
(9) LHPOUT
(20) LLINEIN
MUTE
CLKIN
DIVIDER
(Div x1, x2)
CLKIN
DIVIDER
(Div x1, x2)
OSC
(26) (25)
(2)
(27)
(1)
(28)
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
Product Preview data sheets contain
specifications for products in the formative
phase of development. These products may
be changed or discontinued without notice.
2000 Wolfson Microelectronics Ltd.
http://www.wolfson.co.uk
WM8711
Product Preview
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
DGND
DCVDD
XTO
DBVDD
CLKOUT
BCLK
-10 to +70oC
28-pin SSOP
2
XWM8711EDS
3
4
XTI/MCLK
SCLK
DACDAT
DACLRC
NC
5
6
SDIN
CSB
7
NC
8
MODE
LLINEIN
RLINEIN
NC
HPVDD
LHPOUT
RHPOUT
HPGND
LOUT
9
10
11
12
13
14
NC
VMID
ROUT
AGND
AVDD
PIN DESCRIPTION
PIN
NAME
DBVDD
CLKOUT
BCLK
TYPE
Supply
Digital Output
Digital Input/Output Digital Audio Bit Clock, Pull Down (see Note 1)
Digital Input
DAC Digital Audio Data Input
Digital Input/Output DAC Sample Rate Left/Right Clock, Pull Down (see Note 1)
DESCRIPTION
1
Digital Buffers VDD
Buffered Clock Output
2
3
4
DACDAT
DACLRC
5
6
NC
NC
No Connection
7
No Connection
8
HPVDD
LHPOUT
RHPOUT
HPGND
LOUT
Supply
Headphone VDD
9
Analogue Output
Analogue Output
Ground
Left Channel Headphone Output
Right Channel Headphone Output
Headphone GND
10
11
12
13
14
15
16
17
18
19
20
21
22
Analogue Output
Analogue Output
Supply
Left Channel Line Output
Right Channel Line Output
Analogue VDD
ROUT
AVDD
AGND
Ground
Analogue GND
VMID
Analogue Output
NC
Mid-rail reference decoupling point
No Connection
NC
No Connection
RLINEIN
LLINEIN
MODE
CSB
Analogue Input
Analogue Input
Digital Input
Digital Input
Right Channel Line Input (AC coupled)
Left Channel Line Input (AC coupled)
Control Interface Selection, Pull up (see Note 1)
3-Wire MPU Chip Select/ 2-Wire MPU interface address selection, active
low, Pull up (see Note 1)
23
24
25
26
27
28
SDIN
SCLK
Digital Input
Digital Input
Digital Input
Digital Output
Supply
3-Wire MPU Data Input / 2-Wire MPU Data Input
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
Crystal Input or Master Clock Input (MCLK)
Crystal Output
XTI/MCLK
XTO
DCVDD
DGND
Digital Core VDD
Ground
Digital GND
Note:
1. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power.
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
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WM8711
Product Preview
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
MIN
-0.3V
MAX
+3.63V
Digital supply voltage
Analogue supply voltage
-0.3V
+3.63V
Voltage range digital inputs
DGND -0.3V
AGND -0.3V
DVDD +0.3V
AVDD +0.3V
40MHz
Voltage range analogue inputs
Master Clock Frequency (see Note 4)
Operating temperature range, TA
Storage temperature
-10°C
-65°C
+70°C
+150°C
Package body temperature (soldering 10 seconds)
Package body temperature (soldering 2 minutes)
+240°C
+183°C
Notes:
1. Analogue and digital grounds must always be within 0.3V of each other.
2. The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage (AVDD) or
digital supply buffer voltage (DBVDD).
3. The digital supply buffer voltage (DBVDD) must always be less than or equal to the analogue supply voltage (AVDD).
4. When CLKIDIV2 = 1.
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
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WM8711
Product Preview
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supply range
Ground
DCVDD
DBVDD
1.42
2.7
3.6
3.6
3.6
V
V
AVDD, HPVDD
DGND,AGND,HPGND
IAVDD, IHPVDD
2.7
V
0
8
V
Total analogue supply current
DCVDD, DBVDD, AVDD,
HPVDD= 3.3V
mA
Digital supply current
IDCVDD, IDBVDD
DCVDD, DBVDD, AVDD,
HPVDD= 3.3V
3
mA
uA
Standby Current Consumption
10
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
VIH
VOL
.3 x DBVDD
V
V
V
Input HIGH level
.7 x DBVDD
Output LOW
0.10 x
DBVDD
Output HIGH
VOH
.9 x DBVDD
0.7
V
Power On Reset Threshold (DCVDD)
DCVDD Threshold On -> Off
Hysteresis
Vth
VIH
VOL
0.9
0.3
0.6
1.2
V
V
V
DCVDD Threshold Off -> On
Analogue Reference Levels
Reference voltage
VVMID
AVDD/2 –
50mV
AVDD/2
50K
AVDD/2 +
50mV
V
Potential divider resistance
RVMID
40K
60K
Ohms
Line Output for DAC Playback Only (Load = 10K ohms. 50pF)
0dBFs Full scale output voltage
At LINE outputs
1.0 x
AVDD/3.3
100
Vrms
dB
SNR (Note 1,2)
A-weighted,
@ fs = 48KHz
A-weighted
90
SNR (Note 1,2)
98
93
dB
@ fs = 96KHz
A-weighted,
SNR (Note 1,2)
dB
@ fs = 48KHz, AVDD
= 2.7V
Dynamic Range (Note 2)
THD
DNR
A-weighted, -60dB
full scale input
85
90
dB
1KHz, 0dBFs
1kHz, -3dBFs
1kHz 100mVpp
-88
-92
50
-80
-86
dB
dB
dB
dB
Power Supply Rejection Ratio
DAC channel separation
PSSR
20Hz to 20kHz
100mVpp
45
100
dB
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
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WM8711
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Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Stereo Headphone Output
0dB Full scale output voltage
1.0 x
AVDD/3.3
30
Vrms
Max Output Power RL = 32
ohms
PO
PO
mW
mW
Max Output Power RL = 16
ohms
40
SNR (Note 1,2)
THD
A-weighted
90
97
0.1
60
1.0
40
50
45
dB
%
1kHz, RL = 32 ohms @
PO = 10mW rms
0.1
60
dB
%
1kHz, RL = 32 ohms @
PO = 20mW rms
1.0
40
dB
dB
dB
Power Supply Rejection Ratio
PSSR
1kHz 100mVpp
20Hz to 20kHz
100mVpp
Programmable Gain Maximum
Programmable Gain Minimum
Programmable Gain Step Size
Mute attenuation
1kHz
6
-73
1
dB
1kHz
dB
dB
1kHz, 0dB
80
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’
weighted over a 20Hz to 20kHz bandwidth.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use
such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic
specification values.
3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
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WM8711
Product Preview
POWER CONSUMPTION
MODE DESCRIPTION
CURRENT CONSUMPTION
MIN
TYP
7
MAX
UNITS
mA
Playback
0
0
0
1
0
1
0
0
0
0
Playback Oscillator and
CLKOUT disabled
6
mA
Standby
0
1
1
1
1
1
1
0.05
0.01
mA
mA
Power Down
X
X
X
Table 1 Powerdown Mode Current Consumption Examples
Notes:
1. AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC. Slave Mode, fs = 48kHz,
MCLK = 256fs (12.288MHz).
2. All figures are quiescent, with no signal.
3. The power dissipation in the headphone itself not included in the above table.
MASTER CLOCK TIMING
tXTIL
MCLK
tXTIH
tXTIY
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK Duty cycle
TXTIH
TXTIL
TXTIY
18
18
ns
ns
ns
54
40:60
60:40
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
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WM8711
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DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
(Output)
tDL
DACLRC
(Output)
tDLT
tDHT
DACDAT
Figure 2 Digital Audio Data Timing - Master Mode
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
DACLRC propagation delay
from BCLK falling edge
tDL
0
10
ns
ns
ns
DACDAT setup time to
BCLCK rising edge
tDST
tDHT
10
10
DACDAT hold time from
BCLK rising edge
DIGITAL AUDIO INTERFACE – SLAVE MODE
tBCH
tBCL
BCLK
(Input)
tBCY
DACLRC
(Input)
tLRSU
tDS
tLRH
DACDAT
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, slave mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
DACLRC set-up time to
BCLK rising edge
tLRSU
DACLRC hold time from
BCLK rising edge
tLRH
tDS
10
10
ns
ns
DACDAT set-up time to
BCLK rising edge
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
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WM8711
Product Preview
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, slave mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DACDAT hold time from
BCLK rising edge
tDH
10
ns
MPU INTERFACE TIMING
tCSL
tCSH
CSB
tSCY
tCSS
tSCS
tSCH
tSCL
SCLK
SDIN
LSB
tDSU
tDHO
Figure 4 Program Register Input Timing - 3-Wire MPU Serial Control Mode
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising
edge
tSCS
60
ns
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
80
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
CSB pulse width high
CSB rising to SCLK rising
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
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WM8711
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t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t7
t1
t10
Figure 5 Program Register Input Timing – 2-Wire MPU Serial Control Mode
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
400
kHz
ns
us
ns
ns
ns
ns
ns
ns
ns
SCLK Low Pulsewidth
SCLK High Pulsewidth
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t10
600
1.3
600
600
100
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
300
300
600
900
WOLFSON MICROELECTRONICS LTD
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WM8711
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DEVICE DESCRIPTION
INTRODUCTION
The WM8711 is a low power audio DAC designed specifically for portable audio products. Its
features, performance and low power consumption make it ideal for portable MP3, CD and mini-disc
players.
The WM8711 includes line and headphone outputs from the on-board DAC, configurable digital audio
interface and a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner
for a range of industry standard microprocessors, controllers and DSPs.
The on-board digital to analogue converter (DAC) accepts digital audio from the digital audio
interface. Digital filter de-emphasis at 32kHz, 44.1kHz and 48kHz can be applied to the digital data
under software control. The DAC employs
a high quality multi-bit high-order oversampling
architecture to again deliver optimum performance with low power consumption.
The DAC outputs and Line Inputs (BYPASS) are available both at line level and through a
headphone amplifier capable of efficiently driving low impedance headphones. The headphone
output volume is adjustable in the analogue domain over a range of +6dB to –73dB and can be
muted.
The design of the WM8711 minimises power consumption without compromising performance. It
includes the ability to power off selective parts of the circuitry under software control, thus conserving
power. Separate power save modes can be configured under software control including a standby
and power off mode.
Special techniques allow the audio to be muted and the device safely placed into standby, sections
of the device powered off, volume levels adjusted without any audible clicks, pops or zipper noises.
Therefore standby and power off modes may be used dynamically under software control, whenever
playback is not required.
The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz,
44.1kHz, 48kHz, 88.2kHz and 96kHz. The WM8711 has two schemes to support the programmable
sample rates: Normal industry standard 256/384 fs sampling mode may be used. A special USB
mode is included, where all audio sampling rates can be generated from a 12.00MHz USB clock. The
digital filters used for playback are optimised for each sampling rate used.
The digital audio interface can support a range of audio data formats including I2S, DSP Mode (a
burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left justified
and MSB-First, right justified. The digital audio interface can operate in both master or slave modes.
The software control uses either a 2 or 3-wire MPU interface.
AUDIO SIGNAL PATH
DAC FILTERS
The DAC filters perform true 24 bit signal processing to convert the incoming digital audio data from
the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by
the analogue DAC. Figure 6 illustrates the DAC digital filter path.
FROM DIGITAL
DIGITAL
TO LINE
DIGITAL
MUTE
INTERPOLATION
AUDIO
INTERFACE
DE_EMPHASIS
OUTPUTS
FILTER
DEEMP
DACMU
Figure 6 DAC Filter Schematic
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
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WM8711
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The DAC digital filter can apply digital de-emphasis under software control, as shown in Table 2. The
DAC can also perform a soft mute where the audio data is digitally brought to a mute level. This
removes any abrupt step changes in the audio that might otherwise result in audible clicks in the
audio outputs.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000101
2:1
DEEMP[1:0]
00
De-emphasis Control
(Digital)
Digital Audio
Path Control
11 = 48KHz
10 = 44.1KHz
01 = 32KHz
00 = Disable
3
DACMU
1
DAC Soft Mute Control
(Digital)
1 = Enable soft mute
0 = Disable soft mute
Table 2 DAC Software Control
DAC
The WM8711 employs a multi-bit sigma delta oversampling digital to analogue converter. The
scheme for the converter is illustrated in Figure 7.
FROM DAC
DIGITAL
FILTERS
TO LINE OUTPUT
Figure 7 Multi-Bit Oversampling Sigma Delta Schematic
The DAC converts the multi-level digital audio data stream from the DAC digital filters into high
quality analogue audio.
LINE OUTPUTS
The WM8711 provides two low impedance line outputs LLINEOUT and RLINEOUT, suitable for
driving typical line loads of impedance 10K and capacitance 50pF.
The LLINEOUT and RLINEOUT outputs are only available at a line output level and are not level
adjustable in the analogue domain, having a fixed gain of 0dB. The level is fixed such that at the DAC
full scale level the output level is Vrms at AVDD = 3.3 volts. Note that the DAC full scale level tracks
directly with AVDD. The scheme is shown in Figure 8. The line output includes a low order audio low
pass filter for removing out-of band components from the sigma-delta DAC. Therefore no further
external filtering is required in most applications.
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
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WM8711
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BYPASS
FROM LINE
INPUTS
DACSEL
FROM DAC
LINEOUT
VMID
TO HEADPHONE AMP
Figure 8 Line Output Schematic
The line output is muted by either muting the DAC (analogue) or Soft Muting (digital) and disabling
the BYPASS path. Refer to the DAC section for more details. Whenever the DAC is muted or the
device placed into standby mode the DC voltage is maintained at the line outputs to prevent any
audible clicks from being present.
The software control for the line outputs is shown in Table 3.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Bypass Switch
0000100
3
BYPASS
1
Analogue
Audio Path
Control
1 = Enable Bypass
0 = Disable Bypass
DAC Select
4
DACSEL
0
1 = Select DAC
0 = Don’t select DAC
Table 3 Output Software Control
The recommended external components are shown in Figure 9.
R2
LINEOUT
C1
R1
AGND
AGND
Figure 9 Line Outputs Application Drawing
Recommended values are C1 = 470nF (10V npo type), R1 = 47KOhms, R2 = 100 Ohms
C1 forms a DC blocking capacitor to the line outputs. R1 prevents the output voltage from drifting so
protecting equipment connected to the line output. R2 forms a de-coupling resistor preventing
abnormal loads from disturbing the device. Note that poor choice of dielectric material for C1 can
have dramatic effects on the measured signal distortion at the output.
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
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HEADPHONE AMPLIFIER
The WM8711 has a stereo headphone output available on LHPOUT and RHPOUT. The output is
designed specifically for driving 16 or 32 ohm headphones with maximum efficiency and low power
consumption. The headphone output includes a high quality volume level adjustment and mute
function.
The scheme of the circuit is shown in Figure 10.
FROM
DAC VIA
LINEOUT
HPOUT
VMID
Figure 10 Headphone Amplifier Schematic
LHPOUT and RHPOUT volumes can be independently adjusted under software control using the
LHPVOL[6:0] and RHPVOL[6:0] bits respectively of the headphone output control registers. The
adjustment is logarithmic with an 80dB range in 1dB steps from +6dB to –73dB.
The headphone outputs can be separately muted by writing codes less than 0110000 to
LHPVOL[6:0] or RHPVO[6:0]L bits. Whenever the headphone outputs are muted or the device
placed into standby mode, the DC voltage is maintained at the line outputs to prevent any audible
clicks from being present.
A zero cross detect circuit is provided at the input to the headphones under the control of the LZCEN
and RZCEN bits of the headphone output control register. Using these controls the volume control
values are only updated when the input signal to the gain stage is close to the analogue ground level.
This minimises and audible clicks and zipper noise as the gain values are changed or the device
muted. Note that this circuit has no time out so if only DC levels are being applied to the gain stage
input of more than approximately 20mv, then the gain will not be updated. This zero cross function is
enabled when the LZCEN and RZCEN bit is set high during a volume register write. If there is
concern that a DC level may have blocked a volume change (one made with LZCEN or RZCEN set
high) then a subsequent volume write of the same value, but with the LZCEN or RZCEN bit set low
will force a volume update, regardless of the DC level.
LHPOUT and RHPOUT volume and zero-cross setting can be changed independently. Alternatively,
the user can lock the two channels together, allowing both to be updated simultaneously, halving the
number of serial writes required, provided that the same gain is needed for both channels. This is
achieved through writing to the HPBOTH bit of the control register. Setting LRHPBOTH whilst writing
to LHPVOL and LZCEN will simultaneously update the Right Headphone controls similarly. The
corresponding effect on updating RLHPBOTH is also achieved.
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The software control is given in Table 4.
REGISTER
ADDRESS
BIT
6:0
LABEL
DEFAULT
DESCRIPTION
0000010
LHPVOL[6:0]
1111001
( 0dB )
Left Channel Headphone Output
Volume Control
Left
Headphone
Out
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
7
8
LZCEN
1
0
Left Channel Zero Cross detect
Enable
1 = Enable
0 = Disable
LRHPBOTH
Left to Right Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
LHPVOL[6:0] and LZCEN to
RHPVOL[6:0] and RZCEN
0 = Disable Simultaneous Load
0000011
6:0
RHPVOL[7:0]
1111001
( 0dB )
Right Channel Headphone Output
Volume Control
Right
Headphone
Out
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
7
8
RZCEN
1
0
Right Channel Zero Cross Detect
Enable
1 = Enable
0 = Disable
RLHPBOTH
Right to Left Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
RHPVOL[6:0] and RZCEN to
LHPVOL[6:0] and LZCEN
0 = Disable Simultaneous Load
Table 4 Headphone Output Software Control
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The recommended external components required to complete the application are shown in Figure 11.
HPOUT
C1
AGND
R1
AGND
Figure 11 Headphone Output Application Drawing
Recommended values are C1 = 220uF (10V electrolytic), R1 = 47KOhms
C1 forms a DC blocking capacitor to isolate the dc of the HPOUT from the headphones. R1 form a
pull down resistor to discharge C1 to prevent the voltage at the connection to the headphones from
rising to a level that may damage the headphones. L1 (optional) forms a phase shifting network with
the headphone load aiding overall performance, and increasing the protection of the WM8711
headphone amplifier from potentially destructive externally applied electrostatic discharge events.
DEVICE OPERATION
DEVICE RESETTING
The WM8711 contains a power on reset circuit that resets the internal state of the device to a known
condition. The power on reset is applied as DCVDD powers on and released only after the voltage
level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on
threshold voltage then the power on reset is re-applied. The threshold voltages and associated
hysteresis are shown in the Electrical Characteristics table.
The user also has the ability to reset the device to a known state under software control as shown in
the table below.
REGISTER
ADDRESS
BIT
LABEL
RESET
DEFAULT
DESCRIPTION
0001111
Reset Register
8:0
not reset
Reset Register
Writing 00000000 to register resets
device
Table 5 Software Control of Reset
When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and
released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the
ACK signal (approximately 1 SCLK period, refer to Figure 20).
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. To allow WM8711 to be used in a centrally clocked system, the WM8711 is capable of
either generating this system clock itself or receiving it from an external source as will be discussed.
For applications where it is desirable that the WM8711 is the system clock source, then clock
generation is achieved through the use of a suitable crystal connected between the XTI/MCLK input
and XTO output pins (see CRYSTAL OSCILLATOR section).
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For applications where a component other than the WM8711 will generate the reference clock, the
external system Master Clock can be applied directly through the XTI/MCLK input pin with no
software configuration necessary. Note that in this situation, the oscillator circuit of the WM8711 can
be safely powered down to conserve power (see POWER DOWN section)
CORE CLOCK
The WM8711 DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by
software as shown in Table 6 below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001000
6
CLKIDIV2
0
Core Clock divider select
Sampling
Control
1 = Core Clock is MCLK divides by 2
0 = Core Clock is MCLK
Table 6 Software Control of Core Clock
Having a programmable MCLK divider allows the device to be used in applications where higher
frequency master Clocks are available. For example the device can support 512Fs master clocks
whilst fundamentally operating in a 256Fs mode.
CRYSTAL OSCILLATOR
The WM8711 includes a crystal oscillator circuit that allows the audio system’s reference clock to be
generated on the device. This is available to the rest of the audio system in buffered form on
CLKOUT. The crystal oscillator is a low radiation type, designed for low EMI. A typical application
circuit is shown Figure 12.
XTI/MCLK
XTO
Cp
Cp
DGND
DGND
Figure 12 Crystal Oscillator Application Circuit
For crystal frequencies in the 12MHz range, a Cp of 10pF is recommended. For crystal frequencies
in the 18MHz range, 15pF Cp is recommended.
The WM8711 crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a
requirement for high quality audio DACs, regardless of the converter architecture. The WM8711
architecture is less susceptible than most converter techniques but still requires clocks with less than
approximately 1ns of jitter to maintain performance. In applications where there is more than one
source for the master clock, it is recommended that the clock is generated by the WM8711 to
minimise such problems.
CLOCKOUT
The Core Clock is internally buffered and made available externally to the audio system on the
CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for
driving external loads.
There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will
inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to
Electrical Characteristics.
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CLKOUT can also be divided by 2 under software control, refer to Table 7. Note that if CLKOUT is
not required then the CLKOUT buffer on the WM8711 can be safely powered down to conserve
power (see POWER DOWN section). If the system architect has the choice between using FCLKOUT
=
FMCLK or FCLKOUT = FMCLK/2 in the interface, the latter is recommended to conserve power. When the
divide by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical
Characteristics for timing information.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001000
7
CLKODIV2
0
CLKOUT divider select
Sampling
Control
1 = CLOCKOUT is Core Clock
divides by 2
0 = CLOCKOUT is Core Clock
Table 7 Programming CLKOUT
CLKOUT is disabled and set low whenever the device is in reset.
DIGITAL AUDIO INTERFACES
WM8711 may be operated in either one of the 4 offered audio interface modes. These are:
•
•
•
•
Right justified
Left justified
I2S
DSP mode
All four of these modes are MSB first and operate with data 16 to 32 bits, except in right justified
mode where 32 bit data is not supported.
The digital audio interface receives the digital audio data for the internal DAC digital filters on the
DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters
with left and right channels multiplexed together. DACLRC is an alignment clock that controls
whether Left or Right channel data is present on DATDAT. DACDAT and DACLRC are synchronous
with the BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always
an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in master
or slave mode. Refer to the MASTER/SLAVE OPERATION section
There are four digital audio interface formats accommodated by the WM8711. These are shown in
the figures below. Refer to the Electrical Characteristic section for timing information.
Left Justified mode is where the MSB is available on the first rising edge of BCLK following a
DACLRC transition.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC
BCLK
DACDAT
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Figure 13 Left Justified Mode
I2S mode is where the MSB is available on the 2nd rising edge of BCLK following a LRCLK
transition.
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1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC
BCLK
1 BCLK
1 BCLK
DACDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 14 I2S Mode
Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a LRCLK
transition, yet MSB is still transmitted first.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC
BCLK
DACDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 15 Right Justified Mode
DSP mode is where the left channel MSB is available on either the 1st or 2nd rising edge of BCLK
(selectable by LRP) following an LRCLK transition high. Right channel data immediately follows left
channel data.
1/fs
1 BCLK
DACLRC
BCLK
RIGHT CHANNEL
LEFT CHANNEL
DACDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
Input Word Length (IWL)
Note: Input word length is defined by the IWL register, LRP = 1
Figure 16 DSP Mode
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In all modes DACLRC must always change on the falling edge of BCLK, refer to Figure 13, Figure
14, Figure 15 and Figure 16. Operating the digital audio interface in DSP mode allows ease of use
for supporting the various sample rates and word lengths. The only requirement is that all data is
transferred within the correct number of BCLK cycles to suit the chosen word length.
In order for the digital audio interface to offer similar support in the three other modes (Left Justified,
I2S and Right Justified), the DACLRC and BCLK frequencies, continuity and mark-space ratios need
more careful consideration.
In Slave mode, DACLRC inputs are not required to have a 50:50 mark-space ratio. BCLK input need
not be continuous. It is however required that there are sufficient BCLK cycles for each DACLRC
transition to clock the chosen data word length. The non-50:50 requirement on the LRC is of use in
some situations such as with a USB 12MHZ clock. Here simply dividing down a 12MHz clock within
the DSP to generate LRC and BCLK will not generate the appropriate DACLRC since it will no longer
change on the falling edge of BCLK. For example, with 12MHz/32k fs mode there are 375 MCLK per
LRC. In these situations DACLRC can be made non 50:50.
In Master mode, DACLRC will be output with a 50:50 mark-space ratio with BCLK output at 64fs. The
exception is in 96/88.2k mode where BCLK is MCLK and in USB mode where BCLK is always
12MHz. So for example in 12MHz/32k fs mode there are 375 master clocks per LRC period.
Therefore the DACLRC output will have a mark space ratio of 187:188.
The DAC digital audio interface modes are software configurable as indicated in Table 8. Note that
dynamically changing the software format may result in erroneous operation of the interfaces and is
therefore not recommended.
The length of the digital audio data is programmable at 16/20/24 or 32 bits. Refer to the software
control table below. The data is signed 2’s complement. The DAC digital filters process data using 24
bits. If the DAC is programmed to receive 16 or 20 bit data, the WM8711 packs the LSBs with zeros.
If the DAC is programmed to receive 32 bit data, then it strips the LSBs.
The DAC outputs can be swapped under software control using LRP and LRSWAP as shown in
Table 8. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses
the order of that a Left sample goes to the right DAC output and a Right sample goes to the left DAC
output. LRP swaps the phasing so that a Right/Left sampled pair is expected and preserves the
correct channel phase difference, except in DSP mode, where LRP controls the positioning of the
MSB relative to the rising edge of DACLRC.
To accommodate system timing requirements the interpretation of BCLK maybe inverted, this is
controlled via the software shown in Table 8. This is especially appropriate for DSP mode.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000111
1:0
FORMAT[1:0]
10
Audio Data Format Select
Digital Audio
Interface Format
11 = DSP Mode, frame sync + 2 data
packed words
10 = I2S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
3:2
IWL[1:0]
10
Input Audio Data Bit Length Select
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
4
LRP
0
DACLRC phase control (in left, right
or I2S modes)
1 = Right Channel DAC data when
DACLRC high
0 = Right Channel DAC data when
DACLRC low
(opposite phasing in I2S mode)
or
DSP mode A/B select ( in DSP mode
only)
1 = MSB is available on 2nd BCLK
rising edge after DACLRC rising
edge
0 = MSB is available on 1st BCLK
rising edge after DACLRC rising
edge
5
6
7
LRSWAP
MS
0
0
0
DAC Left Right Clock Swap
1 = Right Channel DAC Data Left
0 = Right Channel DAC Data Right
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Bit Clock Invert
BCLKINV
1 = Invert BCLK
0 = Don’t invert BCLK
Table 8 Digital Audio Interface Control
Note: If right justified 32 bit mode is selected then the WM8711 defaults to 24 bits.
MASTER AND SLAVE MODE OPERATION
The WM8711 can be configured as either a master or slave mode device. As a master mode device
the WM8711 controls sequencing of the data and clocks on the digital audio interface. As a slave
device the WM8711 responds with data to the clocks it receives over the digital audio interface. The
mode is set with the MS bit of the control register as shown in Table 9.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000111
6
MS
0
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Digital Audio Interface
Format
Table 9 Programming Master/Slave Modes
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As a master mode device the WM8711 controls the sequencing of data transfer (DACDAT) and
output of clocks (BCLK, DACLRC) over the digital audio interface. It uses the timing generated from
the MCLK input as the reference for the clock and data transitions. This is illustrated in Figure 17.
DACDAT is always an input to the WM8711 independent of master or slave mode.
BCLK
DSP
DECODER
WM8711
DAC
DACLRC
DACDAT
Figure 17 Master Mode
As a slave device the WM8711 sequences the data transfer (DACDAT) over the digital audio
interface in response to the external applied clocks (BCLK, DACLRC). This is illustrated in Figure 18.
BCLK
DSP
DECODER
WM8711
DAC
DACLRC
DACDAT
Figure 18 Slave Mode
Note that the WM8711 relies on controlled phase relationships between audio interface BCLK,
DACLRC and the master MCLK or CLKOUT. To avoid any timing hazards, refer to the timing section
for detailed information.
AUDIO DATA SAMPLING RATES
The WM8711 provides for two modes of operation (normal and USB) to generate the required DAC
sampling rates. Normal and USB modes are programmed under software control according to the
table below.
In Normal mode, the user controls the sample rate by using an appropriate MCLK frequency and the
sample rate control register setting. The WM8711 can support sample rates from 8ks/s up to 96ks/s.
In USB mode, the user must use a fixed MLCK frequency of 12MHz to generate sample rates from
8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus) clock is at
12MHz and the WM8711 can be directly used within such systems. WM8711 can generate all the
normal audio sample rates from this one Master Clock frequency, removing the need for different
master clocks or PLL circuits.
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REGISTER
ADDRESS
BIT
LABEL
USB/
DEFAULT
DESCRIPTION
Mode Select
0001000
0
0
NORMAL
Sampling
Control
1 = USB mode (250/272fs)
0 = Normal mode (256/384fs)
Base Over-Sampling Rate
1
BOSR
0
USB Mode
0 = 250fs
1 = 272fs
Normal Mode
0 = 256fs
1 = 384fs
5:2
SR[3:0]
0000
DAC sample rate control;
See USB Mode and Normal Mode
Sample Rate sections for operation
Table 10 Sample Rate Control
NORMAL MODE SAMPLE RATES
In normal mode MCLK is set up according to the desired sample rates of the DAC. For DAC
sampling rates of 8, 32, 48 or 96KHz, MCLK frequencies of either 12.288MHz (256Fs) or 18.432MHz
(384Fs) can be used. DAC sampling rates of 8, 44.1 or 88.2KHz from MCLK frequencies of either
11.2896MHz (256Fs) or 16.9344MHz (384Fs) can be used.
The table below should be used to set up the device to work with the various sample rate
combinations. Refer to Digital Filter Characteristics section for an explanation of the different filter
types.
SAMPLING
RATE
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
DAC
KHz
48
MHz
BOSR
SR3
0
SR2
0
SR1
0
SR0
0
12.288
18.432
12.288
18.432
12.288
18.432
12.288
18.432
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
2
1
1
2
0
0
0
0
8
32
0
0
0
1
0
0
0
1
0
1
1
0
0
1
1
0
96
0
1
1
1
0
1
1
1
44.1
1
0
0
0
1
0
0
0
8
1
0
0
1
(Note 1)
88.2
1
0
0
1
1
1
1
1
1
1
1
1
Table 11 Normal Mode Sample Rate Look-up Table
Notes:
1. 8k not exact, actual = 8.018kHz
2. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8711 digital signal
processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at
256Fs, with BOSR = 1, the base over-sampling rate is at 384Fs. This can be used to determine the
actual audio data rate required by the DAC.
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The exact sample rates achieved are defined by the relationships in Table 12 below.
TARGET
ACTUAL SAMPLING RATE
SAMPLING
RATE
BOSR=0
(256FS)
BOSR=1
(384FS)
MCLK=16.9344
MCLK=12.288
KHz
MCLK=11.2896
KHz
MCLK=18.432
KHz
KHz
KHz
8.018
8
8
8.018
8
12.288MHz/256 x 1/6
32
11.2896MHz/256 x 2/11
not available
18.432MHz/384 x 1/6
32
16.9344MHz/384 x 2/11
not available
32
44.1
48
12.288MHz/256 x 2/3
not available
18.432MHz/384x 2/3
not available
44.1
44.1
11.2896MHz/256
not available
16.9344MHz /384
not available
48
48
12.288MHz/256
not available
18.432MHz/384
not available
88.2
96
88.2
88.2
11.2896MHz/384 x 2
not available
16.9344MHz /384 x 2
not available
96
96
12.288MHz/256 x 2
18.432MHz/384 x 2
Table 12 Normal Mode Actual Sample Rates
128/192FS NORMAL MODE
The Normal Mode sample rates are designed for standard 256Fs and 384Fs MCLK rates. However
the WM8711 is also capable of being clocked from a 128/192Fs MCLK for application over limited
sampling rates as shown in the table below.
SAMPLING
RATE
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
ADC
DAC
KHz
48
KHz
MHz
6.144
9.216
5.6448
8.4672
BOSR
SR3
SR2
SR1
SR0
48
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
44.1
44.1
Table 13 128/192Fs Normal Mode Sample Rate Look-up Table
512/768FS NORMAL MODE
512 Fs and 768 Fs MCLK rates can be accommodated by using the CLKIDIV2 bit. The core clock to
the DSP will be divided by 2 so an external 512/768 MCLK will become 256/384 Fs internally and the
device otherwise operates as in Table 10 but with MCLK at twice the specified rate.
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USB MODE SAMPLE RATES
In USB mode the MCLK input is 12MHz only.
SAMPLING
RATE
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
DAC
KHz
48
MHz
BOSR
SR3
SR2
SR1
SR0
12.000
0
0
0
0
0
0
1
0
1
0
3
2
44.1
12.000
12.000
12.000
12.000
12.000
12.000
1
0
1
0
0
1
1
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
0
1
1
(Note 2)
8
8
(Note 1)
32
96
88.2
(Note 3)
Table 14 USB Mode Sample Rate Look-Up Table
Notes:
1. 8k not exact, actual = 8.021kHz
2. 44.1k not exact, actual = 44.118kHz
3. 88.1k not exact, actual = 88.235kHz
4. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8711 digital signal
processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB mode,
with BOSR = 0, the base over-sampling rate is defined at 250Fs, with BOSR = 1, the base over-
sampling rate is defined at 272Fs. This can be used to determine the actual audio sampling rate
required by the DAC.
The exact sample rates supported for all combinations are defined by the relationships in Table 15
below.
TARGET
ACTUAL SAMPLING RATE
SAMPLING
RATE
BOSR=0
BOSR=1
(272FS)
( 250FS)
KHz
KHz
KHz
8
8
8.021
12MHz/(250 x 48/8)
32
12MHz/(272 x 11/2)
not available
32
44.1
48
12MHz/(250 x 48/32)
not available
44.117
12MHz/272
48
not available
12MHz/250
88.2
96
not available
88.235
12MHz/136
96
not available
12MHz/125
Table 15 USB Mode Actual Sample Rates
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ACTIVATING DSP AND DIGITAL AUDIO INTERFACE
To prevent any communication problems from arising across the Digital Audio Interface is disabled
(tristate with weak 100k pulldown) at power on. Once the Audio Interface and the Sampling Control
has been programmed it is activated by setting the ACTIVE bit under Software Control.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001001
Active Control
0
ACTIVE
0
Activate Interface
1 = Active
0 = Inactive
Table 16 Activating DSP and Digital Audio Interface
It is recommended that between changing any content of Digital Audio Interface or Sampling Control
Register that the active bit is reset then set.
SOFTWARE CONTROL INTERFACE
The software control interface may be operated using either a 3-wire or 2-wire MPU interface.
Selection of interface format is achieved by setting the state of the MODE pin.
In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and
CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is
used for the serial clock. In 2-wire mode, the state of CSB pin allows the user to select one of two
addresses.
SELECTION OF SERIAL CONTROL MODE
The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved
by setting the state of the MODE pin.
MODE
INTERFACE
FORMAT
0
1
2 wire
3 wire
Table 17 Control Interface Mode Selection
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
The WM8711 can be controlled using a 3-wire serial interface. SDIN is used for the program data,
SCLK is used to clock in the program data and CSB is use to latch in the program data. The 3-wire
interface protocol is shown in Figure 19.
CSB
SCLK
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
SDIN
Figure 19 3-Wire Serial Interface
Notes:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
2-WIRE SERIAL CONTROL MODE
The WM8711 supports a 2-wire MPU serial interface. The device operates as a slave device only.
The WM8711 has one of two slave addresses that are selected by setting the state of pin 10, (CSB).
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WM8711
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ACK
ACK
ACK
DATA B15-8
R ADDR
R/W
DATA B7-0
SDIN
SCLK
START
STOP
Figure 20 2-Wire Serial Interface
Notes:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
CSB STATE
ADDRESS
(DEFAULT = LOW)
0
1
0011010
0011011
Table 18 2-Wire MPU Interface Address Selection
To control the WM8711 on the 2-wire bus the master control device must initiate a data transfer by
establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high.
This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond
to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB
first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of
two available addresses for this device (see Table 18). If the correct address is received and the R/W
bit is ‘0’, indicating a write, then the WM8711 will respond by pulling SDIN low on the next clock pulse
(ACK). The WM8711 is a write only device and will only respond to the R/W bit indicating a write. If
the address is not recognised the device will return to the idle condition and wait for a new start
condition and valid address.
Once the WM8711 has acknowledged a correct address, the controller will send eight data bits (bits
B[15]-B[8]). WM8711 will then acknowledge the sent data by pulling SDIN low for one clock pulse.
The controller will then send the remaining eight data bits (bits B[7]-B[0]) and the WM8711 will then
acknowledge again by pulling SDIN low.
A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a
start or stop condition is detected out of sequence at any point in the data transfer then the device
will jump to the idle condition.
After receiving a complete address and data sequence the WM8711 returns to the idle state and
waits for another start condition. Each write to a register requires the complete sequence of start
condition, device address and R/W bit followed by the 16 register address and data bits.
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WM8711
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POWER DOWN MODES
The WM8711 contains power conservation modes in which various circuit blocks may be safely
powered down in order to conserve power. This is software programmable as shown in the table
below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000110
0
3
4
5
6
7
LINEINPD
1
Line Input Power Down
1 = Enable Power Down
0 = Disable Power Down
DAC Power Down
Power Down
Control
DACPD
1
1
0
0
1
1 = Enable Power Down
0 = Disable Power Down
Line Output Power Down
1 = Enable Power Down
0 = Disable Power Down
Oscillator Power Down
1 = Enable Power Down
0 = Disable Power Down
CLKOUT Power Down
1 = Enable Power Down
0 = Disable Power Down
Power Off Device
OUTPD
OSCPD
CLKOUTPD
POWEROFF
1 = Device Power Off
0 = Device Power On
Table 19 Power Conservation Modes Software Control
Note:
1. When writing to register 0000110 bits 1 and 2 should be set to 1.
The power down control can be used to either a) permanently disable functions when not required in
certain applications or b) to dynamically power up and down functions depending on the operating
mode, e.g.: during playback or record. Please follow the special instructions below if dynamic
implementations are being used.
DACPD: Powers down the DAC and DAC Digital Filters. If this is done dynamically then audible pops
will result unless the following guidelines are followed. In order to prevent pops, the DAC should first
be soft-muted (DACMU), the output should then be de-selected from the line and headphone output
(DACSEL), then the DAC powered down (DACPD). This is of use when the device enters Pause or
Stop modes. During DACPD the digital audio interface is remains active.
OUTPD: Powers down the Line Headphone Output. If this is done dynamically then audible pops
may result unless the DAC is first soft-muted (DACMU). This is of use when the device enters
Record, Pause or Stop modes.
The device can be put into a standby mode (STANDBY) by powering down all the audio circuitry
under software control as shown in Table 20.
DESCRIPTION
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
STANDBY, but with Crystal Oscillator OS and
CLKOUT available
STANDBY, but with Crystal Oscillator OS
available, CLKOUT not-available
STANDBY, Crystal oscillator and CLKOUT not-
available.
Table 20 Standby Mode
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In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue
circuitry remain active. The active analogue includes the analogue VMID reference so that the
analogue line outputs and headphone outputs remain biased to VMID. This reduces any audible
effects caused by DC glitches when entering or leaving STANDBY mode.
The device can be powered off by writing to the POWEROFF bit of the Power Down register. In
POWEROFF mode the Control Interface and a small portion of the digital remain active. The
analogue VMID reference is disabled. Refer to Table 21.
DESCRIPTION
1
1
1
0
1
1
0
0
1
X
X
X
1
1
1
1
1
X
POWEROFF, but with Crystal Oscillator OS and
CLKOUT available
POWEROFF, but with Crystal Oscillator OS
available, CLKOUT not-available
POWEROFF, Crystal oscillator and CLKOUT
not-available.
Table 21 Poweroff Mode
REGISTER MAP
The complete register map is shown in Table 22. The detailed description can be found in the
relevant text of the device description. There are 8 registers with 9 bits per register. These can be
controlled using either the 2 wire or 3 wire MPU interface.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000010
6:0
LHPVOL
[6:0]
1111001
( 0dB )
Left Channel Headphone Output
Volume Control
Left Headphone
Out
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
7
8
LZCEN
1
0
Left Channel Zero Cross detect
Enable
1 = Enable
0 = Disable
LRHPBOTH
Left to Right Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
LHPVOL[6:0] and LZCEN to
RHPVOL[6:0] and RZCEN
0 = Disable Simultaneous Load
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DESCRIPTION
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
0000011
6:0
RHPVOL
[6:0]
1111001
( 0dB )
Right Channel Headphone Output
Volume Control
Right
Headphone Out
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
7
8
RZCEN
1
0
Right Channel Zero Cross detect
Enable
1 = Enable
0 = Disable
RLHPBOTH
Right to Left Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
RHPVOL[60] and RZCEN to
LHPVOL[6:0] and LZCEN
0 = Disable Simultaneous Load
Bypass Switch
0000100
3
BYPASS
1
Audio Path
Control
1 = Enable Bypass
0 = Disable Bypass
DAC Select (Analogue)
1 =Select DAC
4
DACSEL
0
0 = Don’t select DAC
De-emphasis Control (Digital)
11 = 48KHz
0000101
2:1
DEEMP[1:0]
00
Digital Audio
Path Control
10 = 44.1KHz
01 = 32KHz
00 = Disable
3
0
3
4
5
6
7
DACMU
1
1
1
1
0
0
1
DAC Soft Mute Control (Digital)
1 = Enable soft mute
0 = Disable soft mute
0000110
LINEINPD
DACPD
Line Input Power Down
1 = Enable Power Down
0 = Disable Power Down
DAC Power Down
Power Down
Control
1 = Enable Power Down
0 = Disable Power Down
Outputs Power Down
OUTPD
1 = Enable Power Down
0 = Disable Power Down
Oscillator Power Down
1 = Enable Power Down
0 = Disable Power Down
CLKOUT Power Down
1 = Enable Power Down
0 = Disable Power Down
POWEROFF mode
OSCPD
CLKOUTPD
POWEROFF
1 = Enable POWEROFF
0 = Disable POWEROFF
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DESCRIPTION
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
0000111
1:0
FORMAT[1:0]
10
Audio Data Format Select
Digital Audio
Interface Format
11 = DSP Mode, frame sync + 2 data
packed words
10 = I2S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
3:2
IWL[1:0]
10
Input Audio Data Bit Length Select
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
4
LRP
0
DACLRC phase control (in left, right
or I2S modes)
1 = Right Channel DAC data when
DACLRC high
0 = Right Channel DAC data when
DACLRC low
(opposite phasing in I2S mode)
or
DSP mode A/B select ( in DSP mode
only)
1 = MSB is available on 2nd BCLK
rising edge after DACLRC rising
edge
0 = MSB is available on 1st BCLK
rising edge after DACLRC rising
edge
5
6
7
0
1
LRSWAP
MS
0
0
0
0
0
DAC Left Right Clock Swap
1 = Right Channel DAC Data Left
0 = Right Channel DAC Data Right
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Bit Clock Invert
BCLKINV
1 = Invert BCLK
0 = Don’t invert BCLK
0001000
USB/
NORMAL
Mode Select
Sampling
Control
1 = USB mode (250/272fs)
0 = Normal mode (256/384fs)
Base Over-Sampling Rate
BOSR
USB Mode
0 = 250fs
1 = 272fs
Normal Mode
0 = 256fs
1 = 384fs
5:2
6
SR[3:0]
0000
0
DAC sample rate control;
See USB Mode and Normal Mode
Sample Rate sections for operation
CLKIDIV2
Core Clock divider select
1 = Core Clock is MCLK divide by 2
0 = Core Clock is MCLK
7
CLKODIV2
0
CLKOUT divider select
1 = CLOCKOUT is MCLK divide by 2
0 = CLOCKOUT is MCLK
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WM8711
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DESCRIPTION
Activate Interface
REGISTER
ADDRESS
BIT
LABEL
ACTIVE
DEFAULT
0001001
0
0
Active Control
1 = Active
0 = Inactive
Reset Register
0001111
8:0
0
RESET
not reset
0
Reset Register
Writing 00000000 to register resets
device
1110000
TESTFAIL
SAFE
Test Mode Failsafe Bit
1 = Test Mode Allowed
0 = Test Mode Locked Out
Analogue Test Register 1
Test Failsafe
1110001
8:0
8:0
8:0
8:0
ATEST1[8:0]
ATEST2[8:0]
DTEST1[8:0]
DTEST2[8:0]
0
0
0
0
Analogue Test
Register 1
1110010
Analogue Test Register 2
Digital Test Register 1
Digital Test Register 2
Analogue Test
Register 2
11100011
Digital Test
Register 1
11100100
Digital Test
Register 2
Table 22 Register Map Description
Note:
All other bits not explicitly defined in the register table should be set to zero unless specified
otherwise (see powerdown section).
DIGITAL FILTER CHARACTERISTICS
The DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2 and 3.
The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in
the proceeding pages.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.416fs
+/-0.03
UNIT
DAC Filter Type 0 (USB mode, 250fs operation)
Passband
+/- 0.03dB
-6dB
0
0.5fs
Passband Ripple
Stopband
dB
dB
0.584fs
-50
Stopband Attenuation
f > 0.584fs
DAC Filter Type 1 (USB mode, 272fs or Normal mode operation)
Passband
+/- 0.03dB
-6dB
0
0.4535fs
+/- 0.03
0.5fs
Passband Ripple
Stopband
dB
dB
0.5465fs
-50
Stopband Attenuation
f > 0.5465fs
Table 23 Digital Filter Characteristics
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DAC FILTER RESPONSES
0.04
0.03
0.02
0.01
0
0
-20
-40
-60
-0.01
-0.02
-0.03
-0.04
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.4
0.2
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 21 DAC Digital Filter Frequency Response–Type 0
Figure 22 DAC Digital Filter Ripple–Type 0
0.04
0.03
0.02
0.01
0
0
-20
-40
-60
-0.01
-0.02
-0.03
-0.04
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 23 DAC Digital Filter Frequency Response–Type 1
Figure 24 DAC Digital Filter Ripple–Type 1
0.02
0.01
0
0
-20
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.25
Frequency (Fs)
Frequency (Fs)
Figure 25 DAC Digital Filter Frequency Response–Type 2
Figure 26 DAC Digital Filter Ripple–Type 2
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WM8711
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0
0.05
0
-20
-40
-60
-80
-0.05
-0.1
-0.15
-0.2
-0.25
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
Frequency (Fs)
Frequency (Fs)
Figure 27 DAC Digital Filter Frequency Response–Type 3
Figure 28 DAC Digital Filter Ripple–Type 3
DIGITAL DE-EMPHASIS CHARACTERISTICS
0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
2000
4000
6000
8000
10000 12000 14000 16000
0
2000
4000
6000
8000
10000 12000 14000 16000
Frequency (Fs)
Frequency (Fs)
Figure 29 De-Emphasis Frequency Response (32kHz)
Figure 30 De-Emphasis Error (32kHz)
0
-2
0.4
0.3
0.2
0.1
0
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
5000
10000
Frequency (Fs)
15000
20000
0
5000
10000
Frequency (Fs)
15000
20000
Figure 31 De-Emphasis Frequency Response (44.1kHz)
Figure 32 De-Emphasis Error (44.1kHz)
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WM8711
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0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-8
-0.1
-0.2
-0.3
-0.4
-10
0
5000
10000
15000
20000
0
5000
10000
15000
20000
Frequency (Fs)
Frequency (Fs)
Figure 33 De-Emphasis Frequency Response (48kHz)
Figure 34 De-Emphasis Error (48kHz)
WOLFSON MICROELECTRONICS LTD
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WM8711
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RECOMMENDED EXTERNAL COMPONENTS
3.3V
3.3V
+
1
14
15
DBVDD
AVDD
AGND
10µ
F
0.1µF
0.1
µ
F
F
10µF
28
DGND
10
µF
0.1
µF
3.3V
1.5V - 3.3V
8
27
+
10µF
HPVDD
HPGND
DCVDD
LLINEIN
0.1µ
+
5KΩ
11
20
5K
Ω
470nF
47pF
+
12
100Ω
LOUT
ROUT
+
5K
Ω
470nF
47k
Ω
19
RLINEIN
5K
Ω
470nF
47pF
+
100
Ω
13
WM8711
DAC
470nF
47kΩ
5
4
3
DACLRC
DACDAT
BCLK
Audio Serial Data I/F
+
9
LHPOUT
RHPOUT
220
µ
F
47kΩ
3.3V
3-wire Interface
10kΩ
+
10
21
22
2-wire Interface
DGND
MODE
CSB
SDIN
SCLK
3-wire or 2-wire
MPU Interface
23
24
220µ
F
47kΩ
2
CLKOUT
VMID
100Ω
16
+
0.1µF
10µF
XTI/MCLK
XTO
26
25
15pF
15pF
Figure 35 External Components Diagram
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
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WM8711
Product Preview
PACKAGE DIMENSIONS
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)
DM007.C
b
e
28
15
E1
E
GAUGE
PLANE
Θ
14
1
D
0.25
c
L
A1
A A2
-C-
0.10 C
SEATING PLANE
Dimensions
(mm)
NOM
-----
Symbols
MIN
-----
MAX
2.0
-----
1.85
0.38
0.25
10.50
A
A1
A2
b
c
D
e
E
E1
L
0.05
1.62
0.22
0.09
9.90
-----
1.75
-----
-----
10.20
0.65 BSC
7.80
7.40
5.00
0.55
0o
8.20
5.60
0.95
8o
5.30
0.75
4o
θ
REF:
JEDEC.95, MO-150
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 November 2000
36
相关型号：
WM8711CBLGEFL/RV
Consumer Circuit, CMOS, PQCC24, 4 X 4 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, MO-220VGGD-8, QFN-24
CIRRUS
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