WM8714GED/RV [WOLFSON]
24-bit, 96kHz Stereo DAC; 24位， 96kHz的立体声DAC
| 型号： | WM8714GED/RV |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | 24-bit, 96kHz Stereo DAC |
| 文件： | 总17页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8714
w
24-bit, 96kHz Stereo DAC
DESCRIPTION
FEATURES
•
•
Stereo DAC
The WM8714 is a high performance stereo DAC designed
for audio applications such as DVD, home theatre systems,
and digital TV. The WM8714 supports data input word
lengths from 16 to 24-bits and sampling rates up to 96kHz.
The WM8714 consists of a serial interface port, digital
interpolation filters, multi-bit sigma delta modulators and
stereo DAC in a 14-pin SOIC package.
Audio Performance
-
-
95dB SNR (‘A’ weighted @ 48kHz) DAC
-90dB THD
•
•
DAC Sampling Frequency: 8kHz – 96kHz
Pin Selectable Audio Data Interface Format
-
I2S, Right Justified or DSP
3 - 5V Supply Operation
The WM8714 has a hardware control interface for selection
of audio data interface format, mute and de-emphasis. The
WM8714 supports I2S, and right Justified audio data
interfaces.
•
•
•
14-pin SOIC Package
Pin Compatible with WM8725
The WM8714 is an ideal device to interface to AC-3,
DTS, and MPEG audio decoders for surround sound
applications, or for use in DVD players.
APPLICATIONS
•
•
•
DVD Players
Digital TV
Digital Set Top Boxes
BLOCK DIAGRAM
FORMAT MUTE DEEMPH
CONTROL INTERFACE
W
WM8714
SIGMA
DELTA
MODULATOR
LOW
PASS
FILTER
RIGHT
DAC
MUTE
MUTE
VOUTR
VOUTL
BCKIN
LRCIN
SERIAL
INTERFACE
DIGITAL FILTERS
SIGMA
DELTA
MODULATOR
DIN
LOW
PASS
FILTER
LEFT
DAC
CAP
MCLK
VDD GND
Production Data, November 2004, Rev 4.0
Copyright 2004 Wolfson Microelectronics plc.
WOLFSON MICROELECTRONICS plc
w : www.wolfsonmicro.com
WM8714
Production Data
TABLE OF CONTENTS
DESCRIPTION ............................................................................................................1
FEATURES..................................................................................................................1
APPLICATIONS ..........................................................................................................1
BLOCK DIAGRAM ......................................................................................................1
PIN CONFIGURATION................................................................................................3
ORDERING INFORMATION .......................................................................................3
PIN DESCRIPTION .....................................................................................................4
ABSOLUTE MAXIMUM RATINGS..............................................................................5
DC ELECTRICAL CHARACTERISTICS .....................................................................6
ELECTRICAL CHARACTERISTICS ...........................................................................6
TERMINOLOGY................................................................................................................. 7
MASTER CLOCK TIMING ................................................................................................. 8
DIGITAL AUDIO INTERFACE............................................................................................ 8
DEVICE DESCRIPTION..............................................................................................9
GENERAL INTRODUCTION.............................................................................................. 9
DAC CIRCUIT DESCRIPTION ........................................................................................... 9
CLOCKING SCHEMES.....................................................................................................10
DIGITAL AUDIO INTERFACE...........................................................................................10
AUDIO DATA SAMPLING RATES....................................................................................11
DIGITAL FILTER CHARACTERISTICS ............................................................................13
RECOMMENDED EXTERNAL COMPONENTS................................................................14
RECOMMENDED EXTERNAL COMPONENTS VALUES ................................................14
RECOMMENDED ANALOGUE LOW PASS FILTER (OPTIONAL) .........................15
PCB LAYOUT ...................................................................................................................15
PACKAGE DRAWING...............................................................................................16
IMPORTANT NOTICE...............................................................................................17
ADDRESS:........................................................................................................................17
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PIN CONFIGURATION
LRCIN
DIN
1
2
3
4
5
6
7
14
13
12
11
10
9
MCLK
FORMAT
DEEMPH
NC
BCKIN
NC
WM8714
CAP
MUTE
VOUTL
VDD
VOUTR
GND
8
ORDERING INFORMATION
TEMPERATURE
MOISTURE
SENSITIVITY LEVEL
PEAK SOLDERING
DEVICE
RANGE
PACKAGE
TEMPERATURE
240oC
WM8714ED
-25 to +85oC
14-pin SOIC
14-pin SOIC
(tape and reel)
14-pin SOIC
(lead free)
MSL1
MSL1
WM8714ED/R
-25 to +85oC
240oC
260 oC
260 oC
MSL2
MSL2
WM8714GED/V
WM8714GED/RV
-25 to +85oC
-25 to +85oC
14-pin SOIC
(lead free, tape and reel)
Note:
Reel quantity = 3,000
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PIN DESCRIPTION
PIN
1
NAME
LRCIN
TYPE
Digital input
DESCRIPTION
Sample rate clock input
Serial audio data input
Bit clock input
2
DIN
Digital input
Digital input
No connect
Analogue output
Analogue output
Supply
3
BCKIN
NC
4
No internal connection
5
CAP
Analogue internal reference
Right channel DAC output
Negative supply
6
VOUTR
GND
7
8
VDD
Supply
Positive supply
9
VOUTL
MUTE
Analogue output
Digital input
Left channel DAC output
Soft mute control, Internal pull down
High = Mute ON
10
Low = Mute OFF
11
12
NC
No connect
Digital input
No internal connection
De-emphasis select, Internal pull up
High = de-emphasis ON
Low = de-emphasis OFF
Data input format select, Internal pull up
Low = 16-bit right justified
High = 16-24-bit I2S
DEEMPH
13
14
FORMAT
MCLK
Digital input
Digital input
System clock input
Note:
1. Digital input pins have Schmitt trigger input buffers.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
-0.3V
MAX
+7V
Supply voltage
Voltage range digital inputs
Master Clock Frequency
Operating temperature range, TA
Storage temperature after soldering
GND -0.3V
VDD +0.3V
37MHz
+85°C
-25°C
-65°C
+150°C
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DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply range
SYMBOL
VDD
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
2.7
5.5
Ground
GND
0
0
V
Difference DGND to AGND
Supply current
Supply current
-0.3
+0.3
25
V
VDD = 5V
15
12
mA
mA
VDD = 3.3V
ELECTRICAL CHARACTERISTICS
Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
0.8
UNIT
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
VIH
V
V
V
V
Input HIGH level
2.0
Output LOW
VOL
VOH
I
OL = 2mA
AGND + 0.3V
Output HIGH
I
OH = 2mA
AVDD - 0.3V
Analogue Reference Levels
Reference voltage (CAP)
VDD/2 -
50mV
80k
VDD/2
100k
VDD/2 +
50mV
120k
V
Potential divider resistance
RVMID
VDD to CAP and CAP
to GND
Ω
DAC Output (Load = 10k ohms. 50pF)
0dBFs Full scale output voltage
At DAC outputs
1.1 x
VDD/5
95
Vrms
dB
SNR (Note 1,2,3)
SNR (Note 1,2,3)
SNR (Note 1,2,3)
A-weighted,
@ fs = 48kHz
A-weighted
@ fs = 96kHz
A-weighted,
90
93
97
dB
dB
@ fs = 48kHz
AVDD, DVDD = 3.3V
A-weighted
@ fs = 96kHz
AVDD, DVDD = 3.3V
SNR (Note 1,2,3)
SNR (Note 1,2,3)
95
92
dB
dB
Non A-weighted @ fs =
48kHz
THD (Note 3)
1kHz, 0dBFs
-90
95
-74
dB
dB
Dynamic Range (Note 2)
1kHz, THD+N @
-60dBFs
90
DAC channel separation
95
dB
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Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Output Levels
Output level
Load = 10kΩ,
1.1
VRMS
VRMS
0dBFS
Load = 10kΩ,
0dBFS,
0.72
(VDD = 3.3V)
Gain mismatch
channel-to-channel
1
1
%FSR
kΩ
Minimum resistance load
To midrail or a.c.
coupled
To midrail or a.c.
coupled
1
kΩ
(VDD = 3.3V)
Maximum capacitance load
Output d.c. level
5V or 3.3V
100
pF
V
VDD/2
Power On Reset (POR)
POR threshold
1.8
V
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured A-weighted
over a 20Hz to 20kHz bandwidth.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a
filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification
values.
3. CAP pin decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no
signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a
THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the
other. Normally measured by sending a full scale signal down one channel and measuring the other.
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MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK Master clock pulse width high
MCLK Master clock pulse width low
MCLK Master clock cycle time
MCLK Duty cycle
tMCLKH
tMCLKL
tMCLKY
8
8
ns
ns
ns
20
40:60
60:40
DIGITAL AUDIO INTERFACE
tBCH
tBCL
BCKIN
LRCIN
DIN
tBCY
tLRSU
tDS
tLRH
tDH
Figure 2 Digital Audio Data Timing
Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN cycle time
tBCY
tBCH
tBCL
40
16
16
8
ns
ns
ns
ns
BCKIN pulse width high
BCKIN pulse width low
LRCIN set-up time to
BCKIN rising edge
tLRSU
LRCIN hold time from
BCKIN rising edge
tLRH
tDS
8
8
8
ns
ns
ns
DIN set-up time to BCKIN
rising edge
DIN hold time from BCKIN
rising edge
tDH
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DEVICE DESCRIPTION
GENERAL INTRODUCTION
The WM8714 is a high performance DAC designed for digital consumer audio applications. The
range of features make it ideally suited for use in DVD players, AV receivers and other consumer
audio equipment.
The WM8714 is a complete 2-channel stereo audio digital-to-analogue converter, including digital
interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC
and output smoothing filters. It is fully compatible and an ideal partner for a range of industry
standard DSPs and audio controllers. A novel multi bit sigma-delta DAC design is used, utilising a
128x oversampling rate, to optimise signal to noise performance and offer increased clock jitter
tolerance. (In ‘high-rate’ operation, the oversampling ratio is 64x for system clocks of 128fs or
192fs)
Control of internal functionality of the device is provided by hardware control (pin programmed).
Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between
clock rates being automatically controlled. Sample rates (fs) from less than 8ks/s to 96ks/s are
allowed, provided the appropriate system clock is input.
The audio data interface supports 16-bit right justified or 16-24-bit I2S (Philips left justified, one bit
delayed) interface formats.
Single 2.7-5.5V supplies may be used, the output amplitude scaling with absolute supply level.
Low supply voltage operation and low current consumption combined with the low pin count small
package make the WM8714 attractive for many consumer applications.
The device is packaged in a small 14-pin SOIC.
DAC CIRCUIT DESCRIPTION
The WM8714 DAC is designed to allow playback of 24-bit PCM audio or similar data with high
resolution and low noise and distortion. The two DACs on the WM8714 are implemented using
sigma-delta oversampled conversion techniques. These require that the PCM samples are
digitally filtered and interpolated to generate a set of samples at a much higher rate than the up to
96ks/s input rate. This sample stream is then digitally modulated to generate a digital pulse
stream that is then converted to analogue signals in a switched capacitor DAC. The advantage of
this technique is that the DAC is linearised using noise shaping techniques, allowing the 24-bit
resolution to be met using non-critical analogue components. A further advantage is that the high
sample rate at the DAC output means that smoothing filters on the output of the DAC need only
have fairly crude characteristics in order to remove the characteristic steps, or images on the
output of the DAC. To ensure that generation of tones characteristic to sigma-delta converters is
not a problem, dithering is used in the digital modulator along with a higher order modulator. The
multi-bit switched capacitor technique used in the DAC reduces sensitivity to clock jitter, and
dramatically reduces out of band noise compared to switched current or single bit techniques
used in other implementations.
The voltage on the CAP pin is used as the reference for the DACs. Therefore the amplitude of the
signals at the DAC outputs will scale with the amplitude of the voltage at the CAP pin. An external
reference could be used to drive into the CAP pin if desired, with a value typically of about midrail
ideal for optimum performance.
The outputs of the 2 DACs are buffered out of the device by buffer amplifiers. These amplifiers
will source load currents of several mA and sink current up to 1.5mA allowing significant loads to
be driven. The output source is active and the sink is Class A, i.e. fixed value, so greater loads
might be driven if an external ‘pull-down’ resistor is connected at the output.
Typically an external low pass filter circuit will be used to remove residual out of band noise
characteristic of delta sigma converters. However, the advanced multi-bit DAC used in WM8714
produces far less out of band noise than single bit traditional sigma delta DACs, and so in many
applications this filter may be removed, or replaced with a simple RC pole.
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CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock
to which all audio data processing is synchronised. This clock is often referred to as the audio
system’s Master Clock. The external master clock can be applied directly through the MCLK input
pin with no configuration necessary for sample rate selection.
Note that on the WM8714, MCLK is used to derive clocks for the DAC path. The DAC path
consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In
a system where there are a number of possible sources for the reference clock it is recommended
that the clock source with the lowest jitter be used to optimise the performance of the DAC.
DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Two interface
formats are supported:
•
•
Right Justified mode
I2S mode
All formats send the MSB first. The data format is selected with the FORMAT pin. When
FORMAT is LOW, right justified data format is selected and word lengths up to 16-bits may be
used. When the FORMAT pin is HIGH, I2S format is selected and word length of any value up to
24-bits may be used. (If the word length shorter than 24-bits is used, the unused bits will be
padded with zeros).
‘Packed’ mode (i.e. only 32 or 48 clocks per LRCLK period) operation is also supported in both
I2S (16-24 bits) and right justified formats, (16 wordlength). If a ‘packed’ format of 16-bit word
length is applied (16 BITCLKS per LRCLK half period), the device auto-detects this mode and
switches to 16-bit data length.
I2S MODE
The WM8714 supports word lengths of 16-24 bits in I2S mode.
In I2S mode, the digital audio interface receives data on the DIN input. Audio Data is time
multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used
as a timing reference to indicate the beginning or end of the data words.
In I2S modes, the minimum number of BCKINs per LRCIN period is 2 times the selected word
length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word
length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements
are met.
In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
1 BCKIN
1 BCKIN
DIN
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 3 I2S Mode Timing Diagram
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RIGHT JUSTIFIED MODE
The WM8714 supports word lengths of 16-bits in right justified mode.
In right justified mode, the digital audio interface receives data on the DIN input. Audio Data is
time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also
used as a timing reference to indicate the beginning or end of the data words.
In right justified mode, the minimum number of BCKINs per LRCIN period is 2 times the selected
word length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of
word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above
requirements are met.
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left samples and low during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1
2
3
1
2
3
14 15
14 15
16
16
MSB
LSB
MSB
LSB
Figure 4 Right Justified Mode Timing Diagram
AUDIO DATA SAMPLING RATES
The master clock for WM8714 supports audio sampling rates from 256fs and 384fs, where fs is
the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, and 96kHz. The master
clock is used to operate the digital filters and the noise shaping circuits.
The WM8714 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there
is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The
master clock should be synchronised with LRCIN, although the WM8714 is tolerant of phase
differences or jitter on this clock.
SAMPLING
RATE
MASTER CLOCK
FREQUENCY (MHZ)
(MCLK)
(LRCIN)
256fs
384fs
32kHz
44.1kHz
48kHz
8.192
11.2896
12.288
24.5761
12.288
16.9340
18.432
36.8641
96kHz
Table 1 Master Clock Frequencies Versus Sampling Rate
Notes:
1. 96kHz sample rate at either 256fs or 384fs are only supported with 5V supplies.
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HARDWARE CONTROL MODES
The WM8714 is hardware programmable providing the user with options to select input audio data
format, de-emphasis and mute.
MUTE OPERATION
Pin 10 (MUTE) controls selection of MUTE directly, and can be used to enable and disable the
mute.
MUTE PIN
DESCRIPTION
0
1
Normal Operation, MUTE off
Mute DAC channels
Table 2 Mute Control
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
0.001
0.002
0.003
0.004
0.005
0.006
Time(s)
Figure 5 Application and Release of MUTE
The MUTE pin is an input to select mute or not mute. MUTE is active high; taking the pin high
causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking
MUTE low again allows data into the filter. Refer to figure 5.
INPUT AUDIO FORMAT SELECTION
FORMAT (pin 13) controls the data input format.
FORMAT
INPUT DATA MODE
16 right justified
16 - 24-bit I2S
0
1
Table 3 Input Audio Format Selection
Notes:
1. In 16-24 bit I2S mode, any width of 24 bits or more is supported provided that LRCIN is high
for a minimum of 24 BCKINs and low for a minimum of 24 BCKINs, unless Note 2.
2. If exactly 16 BCKIN cycles occur in both the low and high period of LRCIN the WM8714 will
assume the data is 16-bit and accept the data accordingly.
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DE-EMPHASIS CONTROL
DEEMPH (pin 12) is an input control for selection of de-emphasis filtering to be applied.
DEEMPH
DE-EMPHASIS
0
Off
On
1
Table 4 De-emphasis Control
DIGITAL FILTER CHARACTERISTICS
PARAMETER
Passband Edge
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
-3dB
0.487fs
Passband Ripple
f < 0.444fs
f > 0.555fs
±0.25
dB
dB
Stopband Attenuation
-40
Table 5 Digital Filter Characteristics
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RECOMMENDED EXTERNAL COMPONENTS
VDD
8
VDD
+
C1
C2
7
GND
AGND
13
12
10
FORMAT
DEEMPH
MUTE
Hardware Control
C3
C4
6
9
VOUTR
VOUTL
AC-Coupled
VOUTR/L
to External LPF
WM8714
1
LRCIN
MCLK
14
3
2
Audio Serial Data I/F
BCKIN
DIN
5
CAP
+
C5
C6
AGND
Notes:
1. GND should be connected as close to the WM8714 as possible.
2. C2, C5 should be positioned as close to the WM8714 as possible.
3. Capacitor types should be carefully chosen. Capacitors with very low ESR are
recommended for optimum performance.
Figure 65 External Component Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1
C2
10µF
0.1µF
10µF
0.1µF
10µF
De-coupling for VDD
De-coupling for VDD
C3 and C4
C5
Output AC coupling caps to remove midrail DC level from outputs
Reference de-coupling capacitors for CAP pin
C6
Table 6 External Components Description
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RECOMMENDED ANALOGUE LOW PASS FILTER (OPTIONAL)
4.7kΩ
4.7k
Ω
+VS
_
51
Ω
10uF
1.8kΩ
7.5KΩ
+
+
-VS
1.0nF
680pF
47kΩ
Figure 7 Recommended 2nd Order Low Pass Filter (Optional)
An external low pass filter is recommended (see Figure 7) if the device is driving a wideband
amplifier. In some applications, a passive RC filter may be adequate.
PCB LAYOUT
1. Place all supply decoupling capacitors as close as possible to their respective supply pins
and provide a low impedance path from the capacitors to the appropriate ground.
2. Separate analogue and digital ground planes should be situated under respective analogue
and digital device pins.
3. Digital input signals should be screened from each other and from other sources of noise to
avoid cross-talk and interference. They should also run over the digital ground plane to avoid
introducing unwanted noise into the analogue ground plane.
4. Analogue output signal tracks should be kept as short as possible and over the analogue
ground plane reducing the possibility of losing signal quality.
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PACKAGE DRAWING
DM001.C
D: 14 PIN SOIC 3.9mm Wide Body
e
B
14
8
H
E
1
7
D
L
h x 45o
A1
SEATING PLANE
-C-
α
C
A
0.10 (0.004)
Dimensions
(MM)
Dimensions
(Inches)
Symbols
MIN
MAX
1.75
0.25
0.51
0.25
8.75
4.00
MIN
MAX
A
A1
B
C
D
E
1.35
0.10
0.33
0.19
8.55
3.80
0.0532
0.0040
0.0130
0.0075
0.3367
0.1497
0.0688
0.0098
0.0200
0.0098
0.3444
0.1574
e
1.27 BSC
0.05 BSC
H
h
L
5.80
0.25
0.40
0o
6.20
0.50
1.27
8o
0.2284
0.0099
0.0160
0o
0.2440
0.0196
0.0500
8o
α
REF:
JEDEC.95, MS-012
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
PD Rev 4.0 November 2004
16
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WM8714
Production Data
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service
without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that
information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time
of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard
warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those mandated by government
requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by
the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in
life support devices or systems without the express written approval of an officer of the company. Life support devices or
systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure
to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a
significant injury to the user. A critical component is any component of a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any
license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of WM covering or relating to any combination, machine, or process in which such products or services might be or are
used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval,
license, warranty or endorsement thereof.
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practice, and WM is not responsible nor liable for any such use.
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or
service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
PD Rev 4.0 November 2004
w
17
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