WM8720SEDS/R [WOLFSON]
24-bit, 96kHz Stereo DAC with Volume Control; 24位， 96kHz的立体声DAC，具有音量控制
| 型号： | WM8720SEDS/R |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | 24-bit, 96kHz Stereo DAC with Volume Control |
| 文件： | 总17页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8720
w
24-bit, 96kHz Stereo DAC with Volume Control
DESCRIPTION
FEATURES
•
Performance:
The WM8720 is a high performance stereo DAC designed
for audio applications such as CD, DVD, home theatre
systems, set top boxes and digital TV. The WM8720
supports data input word lengths from 16 to 24-bits and
sampling rates up to 96kHz. The WM8720 consists of a
serial interface port, digital interpolation filter, multi-bit
sigma delta modulator and stereo DAC in a small 20-pin
SSOP package. The WM8720 also includes a digitally
controllable mute and attenuator function on each channel.
-
-
102dB SNR (‘A’ weighted @48kHz),
THD: -95dB @ 0dB FS
•
•
•
•
5V or 3.3V supply operation
Sampling frequency: 8kHz to 96kHz
Input data word: 16 to 24-bit
Hardware or SPI compatible serial port control modes:
-
-
Hardware mode: system clock, reset, mute,
de-emphasis
Serial control mode: mute, de-emphasis, digital
attenuation (256 steps), zero mute, phase reversal,
power down
The WM8720 supports a variety of connection schemes for
audio DAC control. The SPI-compatible serial control port
provides access to a wide range of features including on-
chip mute, attenuation and phase reversal. A hardware
controllable interface is also available.
APPLICATIONS
•
•
•
•
CD, DVD audio
Home theatre systems
Set top boxes
The programmable data input port supports a variety of
glueless interfaces to popular DSPs, audio decoders and
S/PDIF and AES/EBU receivers.
Digital TV
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
Production Data, February 2005, Rev 4.0
Copyright 2005 Wolfson Microelectronics plc.
www.wolfsonmicro.com
WM8720
Production Data
PIN CONFIGURATION
PWDN
SCKI
1
2
3
4
5
6
7
20
19
18
17
16
15
14
DGND
DVDD
MODE
MUTE
LRCIN
DIN
TEST
ML/I2S
MC/IWL
MD/DM
RSTB
BCKIN
ZERO
VOUTR
AGND
8
13
12
11
CAP
9
VOUTL
AVDD
10
ORDERING INFORMATION
TEMPERATURE
MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
TEMPERATURE
DEVICE
RANGE
PACKAGE
MSL1
MSL1
240oC
WM8720EDS
-25 to +85oC
20-pin SSOP
20-pin SSOP
WM8720EDS/R
-25 to +85oC
240oC
(tape and reel)
20-pin SSOP
WM8720SEDS
-25 to +85oC
-25 to +85oC
MSL1
MSL1
260oC
260oC
(Pb free)
20-pin SSOP
WM8720SEDS/R
(Pb free, tape and reel)
Note:
Reel quantity = 2,000
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PIN DESCRIPTION
PIN
1
NAME
PWDN
SCKI
TYPE
DESCRIPTION
Digital input
Digital input
Digital output
Digital input
Powerdown control; low is ON, high is POWER OFF. Internal pull-down.
2
System clock input (256 or 384fs).
Reserved.
3
TEST
4
ML/I2S
Latch enable (software mode) or input format selection (hardware mode).
Internal pull-up.
5
6
MC/IWL
MD/DM
Digital input
Digital input
Serial control data clock input (software mode) or input word length
selection (hardware mode). Internal pull-up.
Serial control data input (software mode) or de-emphasis selection
(hardware mode). Internal pull-up.
7
8
RSTB
ZERO
Digital input
Reset input – active low. Internal pull-up.
Digital output
Infinite zero detect – active low. Open drain type output with active
pull-down.
9
VOUTR
AGND
AVDD
VOUTL
CAP
Analogue output
Supply
Right channel DAC output.
Analogue ground supply.
Analogue positive supply.
Left channel DAC output.
Analogue internal reference.
Audio data bit clock input.
Serial audio data input.
10
11
12
13
14
15
16
17
Supply
Analogue output
Analogue output
Digital input
Digital input
Digital input
Digital IO
BCKIN
DIN
LRCIN
MUTE
Sample rate clock input.
Mute control pin, input or automute output.
Low is not mute, high is mute, Z is automute.
18
MODE
Digital input
Mode select pin. Low is software mode, high is hardware control.
Internal pull-down.
19
20
DVDD
DGND
Supply
Supply
Digital positive supply.
Digital ground supply.
Note:
Digital input pins have Schmitt trigger input buffers.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
MAX
+7V
Supply voltage
Reference input
-0.3V
VDD + 0.3V
-25oC
-65oC
+85oC
+150oC
Operating temperature range, TA
Storage temperature after soldering
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Digital supply range
Analogue supply range
Ground
SYMBOL
DVDD
TEST CONDITIONS
MIN
-10%
-10%
TYP
MAX
+10%
+10%
UNIT
3.3 to 5
V
AVDD
3.3 to 5
V
AGND, DGND
0
0
V
Difference DGND to AGND
Analogue supply current
Digital supply current
Analogue supply current
Digital supply current
Standby analogue current
Standby digital current
-0.3
+0.3
V
AVDD = 5V
DVDD = 5V
AVDD = 3.3V
DVDD = 3.3V
AVDD = 5V
DVDD = 5V
17
6
mA
mA
mA
mA
mA
µA
16
3
1.7
30
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ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC Circuit Specifications
SNR (Note 1)
AVDD, DVDD = 5V
AVDD, DVDD = 3.3V
0dB FS
95
101
100
-96
dB
dB
dB
dB
THD
-85
Dynamic range
Passband
THD+N @ -60dB FS
±0.25dB
95
101
0.4535
fs
fs
Stopband
-3dB
0.491
Pass band ripple
Out of band rejection
Channel Separation
0.25
-40
98
dB
dB
dB
Gain mismatch
0dB FS
0.5
5
%FSR
channel-to-channel
Digital Logic Levels
Input LOW level
VIL
VIH
0.8
V
V
Input HIGH level
2.0
Output LOW level
Output HIGH level
Analogue Output Levels
Output level
VOL
VOH
IOL = 2mA
IOH = 2mA
AVSS + 0.3V
AVDD - 0.3V
Into 10kΩ, full scale 0dB,
1.1
0.72
1
VRMS
VRMS
kΩ
(5V supply)
Into 10kΩ, full scale 0dB,
(3.3V supply)
Minimum resistance load
To midrail or AC coupled
(5V supply)
To midrail or AC coupled
(3.3V supply)
1
kΩ
Maximum capacitance
load
5V or 3.3V
100
pF
V
Output DC level
AVDD/2
Reference Levels
Potential divider
resistance
90
kΩ
AVDD to CAP and CAP to AGND
Voltage at CAP
POR
AVDD/2
POR threshold
2.0
V
TERMINOLOGY
1. Signal-to-noise ratio (dB) (SNR) is a measure of the difference in level between the full-scale output and the output
with no signal applied.
2. Dynamic range (dB) (DNR) is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (eg THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) is a ratio of the r.m.s. values, of (Noise + Distortion)/Signal.
4. Stop band attenuation (dB) is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) (also known as Cross-Talk) is a measure of the amount one channel is isolated from the
other. Normally measured by sending a full-scale signal down one channel and measuring the other.
6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
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Production Data
LRCIN
tBCH
tBCL
tLB
BCKIN
DIN
tBCY
tBL
tDS
tDH
Figure 1 Audio Data Input Timing
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN pulse cycle time
BCKIN pulse width high
BCKIN pulse width low
tBCY
tBCH
tBCL
tBL
100
40
ns
ns
ns
ns
40
BCKIN rising edge to
LRCIN edge
20
LRCIN rising edge to
BCKIN rising edge
tLB
20
ns
DIN setup time
DIN hold time
tDS
tDH
20
20
ns
ns
tSCKIL
SCKI
tSCKIH
tSCKY
Figure 2 System Clock Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
System clock pulse width high
System clock pulse width low
System clock cycle time
tSCKIH
tSCKIL
tSCKY
10
10
27
ns
ns
ns
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Production Data
tMLS
tMLL
tMLH
ML/12S
MC/IWL
MD/DM
tMCH
tMCL
tMCY
tMDS
tMDH
Figure 3 Program Register Input Timing
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
MC/IWL pulse cycle time
MC/IWL pulse width low
MD/DM pulse width high
MD/DM set-up time
tMCY
tMCL
tMCH
tMDS
tMDH
tMLL
tMLS
tMLH
100
40
40
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
MC/IWL hold time
ML/I2S pulse width low
ML/I2S set-up time
ML/I2S hold time
Notes:
1.
Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured “A”
weighted over a 20Hz to 20kHz bandwidth.
2.
All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher
THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low
pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.
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DEVICE DESCRIPTION
WM8720 is a complete stereo audio digital-to-analogue converter, including digital interpolation filter,
multibit sigma delta with dither, switched capacitor multibit stereo DAC and output smoothing filters.
Control of internal functionality of the device is by either hardware control (pin programmed) or
software control (serial interface). The MODE pin selects between hardware and software control. In
software control mode, an SPI type interface is used. This interface may be asynchronous to the
audio data interface. Control data will be re-synchronized to the audio processing internally.
Operation using system clock of 256fs or 384fs is provided. Selection between clock rates is being
automatically controlled in hardware mode, or serial controlled when in software mode. Sample rates
(fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate system clock is input.
The data interface supports normal (Japanese right justified) and I2S (Philips left justified, one bit
delayed) interface formats, in both ‘packed’ and unpacked forms. When in hardware mode, the three
serial interface pins become control pins to allow selection of input data format type (I2S or normal),
input word length (16, 18, 20, or 24-bit) and de-emphasis function.
SYSTEM CLOCK
The system clock for WM8720 must be either 256fs or 384fs, where fs is the audio sampling
frequency (LRCIN) typically 32kHz, 44.1kHz, 48 or 96kHz. The system clock is used to operate the
digital filters and the noise shaping circuits.
WM8720 has a system clock detection circuitry that automatically determines what the system clock
frequency relative to the sampling rate is (to within ±8 system clocks). If greater than 8 clocks error,
then the interface shuts down the DAC and mutes the output. The system clock should be
synchronised with LRCIN, but WM8720 is tolerant of phase differences or jitter on this clock. Severe
distortion in the phase difference between LRCIN and the system clock will be detected, and cause
the device to automatically resynchronise. If the externally applied LRCIN slips in phase by more
than half the internal LRCIN period, which is derived from master clock, then the interface
resynchronises. Such a case would, for example, occur if repeated LRCIN clocks were received with
only 252 systems clocks per period. In this case the interface would resynchronise every 64 LRCIN
periods. During resynchronisation, the device will either repeat the previous sample, or drop the next
sample, depending on the nature of the phase slip. This will ensure no discernible “click “ at the
analogue outputs during resynchronisation. Table 1 shows the typical system clock frequency inputs
for the WM8720.
SYSTEM CLOCK FREQUENCY (MHZ)
SAMPLING RATE (LRCIN)
256fs
8.192
384fs
12.288
16.9340
18.432
36.864
32kHz
44.1kHz
48kHz
11.2896
12.288
24.576
96kHz
Table 1 System Clock Frequencies Versus Sampling Rate
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Production Data
AUDIO DATA INTERFACE
The Serial Data interface to WM8720 is fully compatible with both normal (MSB first, right-justified) or
I2S interfaces. Data may be ‘packed’ (number of serial bit clocks per LRCIN period is exactly 2 times
the number of data bits, i.e. normally 32 in 16-bit mode) or unpacked (more than 32 bit clocks per
LRCIN period).
The WM8720 will automatically detect 16-bit packed data being sent to the device in normal mode,
and accept the data in this input format accordingly.
I2S MODE
DESCRIPTION
0
Normal format (MSB-first, right justified)
I2S format (Philips serial data protocol )
1
Table 2 Serial Interface Formats
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
1
2
3
1
2
3
n-2 n-1
n
n-2 n-1 n
DIN
MSB
MSB
LSB
LSB
Figure 4 Normal Data Input Timing
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
DIN
LSB
MSB
LSB
MSB
Figure 5 I2S Data Input Timing
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MODES OF OPERATION
Control of the various modes of operation is either by software control over the serial interface, or
by hard-wired pin control. Selection of software or hardware mode is via MODE pin. The following
functions may be controlled either via the serial control interface or by hard wiring of the
appropriate pins.
FUNCTION
SOFTWARE CONTROL
DEFAULT VALUE
HARDWARE CONTROL
BEHAVIOUR
PIN 18: MODE = 0
PIN 18: MODE = 1
OPTIONS
Input audio
data format
Normal format
I2S format
I2S = 0 (default)
I2S = 1
Pin 4, 5: ML/ I2S, MC/IWL =
00 or 01 or 10
Pin 4, 5: ML/I2S, MC/IWL = 11
Pin 4, 5: ML/I2S, MC/IWL = 00
Input word length
16
18
20
24
IW[1:0] = 00 (default)
IW[1:0] = 11
Pin 4, 5: ML/I2S, MC/IWL = 11
(I2S only)
IW[1:0] = 01
Pin 4, 5: ML/I2S, MC/IWL = 01
Pin 4, 5: ML/I2S, MC/IWL = 10
Pin 6: MD/DM = 1
IW[1:0] = 10
De-emphasis selection
Mute
On
Off
DE = 1
DE = 0 (default)
Pin 6: MD/DM = 0
On
Off
MU = 1
Pin 17: MUTE = 1
Pin 17: MUTE = 0
MU = 0 (default)
Power down control
Input LRCIN polarity
WM8720 on
WM8720 off
Available from Pin 1: PWDN
Pin 1: PWDN = 0
Pin 1: PWDN = 1
Lch/Rch = High/low
Lch/Rch = Low/high
LRP = 0 (default)
LRP = 1
Not available in hardware mode,
default value set
Volume control
Lch, Rch individually
Lch, Rch common
ATC = 0; 0dB (default)
ATC = 1
Not available in hardware mode,
default 0dB
Infinite zero detect
On
Off
IZD = 1
Automute function controlled
from MUTE pin
IZD = 0 (default)
Low = not mute
Z = automute enable
High = muted
Operation enable (OPE)
DAC output control
Enabled
Disabled
OPE = 0 (default)
OPE = 1
See Table 11
for all options
Default is PL[3:0] = 1001,
stereo mode
Not available in hardware mode
Table 3 Control Function Summary
HARDWARE CONTROL MODES
When the MODE pin is held high the following hardware modes of operation are available.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes pin 17 (MUTE) controls selection of mute directly, and can be
used to enable and disable the automute function, or as an output of the automuted signal.
IZD (Register Bit)
AUTOMUTED
(Internal Signal)
10kΩ
MUTE
PIN
SOFTMUTE
(Internal Signal)
MU (Register Bit)
Figure 6 Mute Circuit Operation
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The MUTE pin behaves as a bi-directional function, that is, as an input to select mute or NOT-mute,
or as an output indication of automute operation. MUTE is active high; taking the pin high causes the
filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again
allows data into the filter.
The automute function detects a series of zero value audio samples of 1024 samples long being
applied to both left and right channels. After such an event, a latch is set whose output (automuted)
is wire OR’ed through a 10kohm resistor to the MUTE pin. Thus if the MUTE pin is not being driven,
the automute function will assert MUTE.
If MUTE is tied low, automute is overridden and will not mute. If MUTE is driven from a source
follower, or diode, then both mute and automute functions are available. If MUTE is not driven,
automute appears as a weak output (10k source impedance) so can be used to drive external
mute circuits.
The automute signal is AND’ed with IZD, this qualified mute signal then being OR’ed into the
SOFTMUTE control. Therefore, in software mode, automute operation may be controlled with IZD
control bit.
I2S INPUT FORMAT SELECTION AND IWL INPUT FORMAT SELECTION
In hardware mode, pins 4 and 5 become input controls for selection of input data format type, and
input data word length, see Table 4. I2S mode is designed to support any word length provided
enough bit clocks are sent.
ML/I2S – PIN 4
MC/IWL – PIN 5
INPUT DATA MODE
16-bit normal
20-bit normal
24-bit normal
I2S mode
0
0
1
1
0
1
0
1
Table 4 Control of Input Data Format Type and Input Data Word Length
DM DE-EMPHASIS
In hardware mode, pin 6 becomes an input control for selection of de-emphasis filtering to be
applied. See Figure 8.
DM
0
1
De-emphasis off
De-emphasis on
DM
Table 5 De-emphasis Control
PWDN POWERDOWN CONTROL
In both hardware and software modes, this pin selects powerdown of the entire device when taken
high.
PWDN
PWDN
0
1
Device powered up
Device powered down
Table 6 Powerdown Control
SOFTWARE CONTROL INTERFACE
The WM8720 can be controlled using a 3-wire serial interface. MD/DM (pin 6) is used for the program
data, MC/IWL (pin 5) is used to clock in the program data and ML/I2S (pin 4) is use to latch in the
program data. The 3-wire interface protocol is shown in Figure 7.
ML/I2S
MC/IWL
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MD/DM
Figure 7 3-Wire Serial Interface
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REGISTER MAP
WM8720 controls the special functions using 4 program registers, which are 16-bits long. These
registers are all loaded through input pin MD/DM. After the 16 data bits are clocked in, ML/I2S/IWL is
used to latch in the data to the appropriate register. Table 7 shows the complete mapping of the
4 registers.
B15
B14
B13
B12
B11
B10
A1
A1
A1
A1
B9
A0
A0
A0
A0
B8
LDL
LDR
PL3
IZD
B7
AL7
AR7
PL2
SF1
B6
AL6
AR6
PL1
SF0
B5
AL5
AR5
PL0
-
B4
AL4
AR4
IW1
-
B3
AL3
AR3
B2
AL2
AR2
B1
AL1
AR1
DE
B0
AL0
AR0
MU
I2S
M0
M1
M2
M3
--
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IW0 OPE
-
-
ATC LRP
Table 7 Mapping of Program Registers
REGISTER NAME
Register 0 (M0)
A[1:0] = 00
BIT NAME
AL[7:0]
LDL
DEFAULT
DESCRIPTION
DAC attenuation data for left channel
Attenuation data load control for left channel
1111 1111
0
Register 1 (M1)
A[1:0] = 01
AR[7:0]
LDR
1111 1111
DAC attenuation data for right channel
Attenuation data load control for right channel
0
0
Register 2 (M2)
A[1:0] = 10
MU
Left and right DACs soft mute control
De-emphasis control
DE
0
Left and right DACs operation control
Input audio word resolution
DAC output control
OPE
0
IW[1:0]
PL[3:0]
I2S
00
1001
0
Register 3 (M3)
A[1:0] = 11
Audio data format select
Polarity of LRCIN (pin 7) select
Attenuator control
Sampling rate select
LRP
0
ATC
0
SF[1:0]
IZD
00
0
Infinite zero detection circuit control and automute control
Table 8 Internal Register Mapping
DAC OUTPUT ATTENUATION
Register 0 (A[1:0] = 00) is used to control left channel attenuation. Bits 0-7 (AL[7:0]) are used to
determine the attenuation level Table 9. The level of attenuation is given by:
Attenuation = [20.log10 (Attenuation_Data/256)] dB ................................................................................................... Eqn. 1
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AX[7:0]
ATTENUATION LEVEL
00(hex)
- ∞dB (mute)
01(hex)
-48.16dB
:
:
:
:
:
:
Fe(hex)
FF(hex)
-0.07dB
0dB
Table 9 Attenuation Control Levels
Bit 8 in register 0 (LDL) is used to control the loading of attenuation data in AL[7:0]. When LDL is set
to 0, attenuation data will be loaded into AL[7:0], but it will not affect the attenuation level until LDL is
set to 1. LDR in register 1 has the same function for right channel attenuation.
Register 1 (A[1:0] = 01) is used to control right channel attenuation in a similar manner.
Bit 2 in register 3 (A1[1:0] = 11) is used to control the attenuator (ATC). When ATC is high, the
attenuation data loaded in program register 0 is used for both the left and the right channels. When
ATC is low, the attenuation data for each register is applied separately to left and right channels.
LEFT AND RIGHT DACS SOFT MUTE CONTROL
Soft mute is controlled by setting bit MU, register 2:bit 0. A high level on MU (MU = 1) will cause the
output to be muted, the effect of which is to ramp the signal down in the digital domain so that there
is no discernible click. This can be seen in Figure 6 Mute Circuit Operation.
DE-EMPHASIS CONTROL
Bit 1 (DE) in register 2 is used to control digital de-emphasis. A low level on bit 1 (DE = 0) disables
de-emphasis whilst a high level enables de-emphasis (DE = 1). De-emphasis applied to the filters
shapes the frequency response of the digital filter according to the input sample frequency.
LEFT AND RIGHT DACS OPERATION CONTROL
Bit 2 (OPE) in register 2 is used for operation control. With OPE = 0 (default) the device functions
normally. With OPE = 1 the device is disabled and the outputs are held at midrail. Current
consumption of the digital section is minimized, but analogue sections remain active in order to
preserve DC levels.
INPUT AUDIO WORD RESOLUTION
WM8720 allows maximum flexibility over the control of the audio data interface, allowing selection of
format type, word length, and sample rates. Bits 3 and 4 of register 2 (IW[1:0]) are used to determine
the input word resolution. WM8720 supports 16-bit, 18-bit, 20-bit and 24-bit formats as described in
Table 10.
BIT 4 (IW1)
BIT 3 (IW0)
INPUT RESOLUTION
16-bit data word
20-bit data word
24-bit data word
18-bit data word
0
0
1
0
1
0
1
1
Table 10 Input Data Resolution
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DAC OUTPUT CONTROL
Bits 5, 6, 7 and 8 (PL[3:0]) of register 2 are used to control the output format as shown in Table 11.
PL3
PL2
PL1
PL0
LEFT
RIGHT
NOTE
OUTPUT
OUTPUT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
Mute both channels
L
MUTE
R
(L + R)/2
MUTE
L
MUTE
MUTE
L
L
R
L
Reverse channels
Stereo mode
(L + R)/2
MUTE
L
L
R
R
R
R
(L + R)/2
MUTE
L
R
(L + R)/2
(L + R)/2
(L + R)/2
(L + R)/2
R
(L + R)/2
Mono mode
Table 11 Programmable DAC Output Format
SERIAL PROTOCOL
Bits 0 (I2S) and 1 (LRP) of register 3 are used to control the input data format completely. A low on
bit 0 (I2S = 0) sets the format to Normal (MSB-first, right justified Japanese format), whilst a high
(I2S = 1) sets the format to I2S (Philips serial data protocol).
POLARITY OF LRCIN SELECT
Bit 1 (LRP) of register 3 is used to control the polarity of LRCIN (sample rate clock). When bit 1 is
low (LRP = 0), left channel data is assumed when LRCIN is in a high phase and right channel data
is assumed when LRCIN is in a low phase. When bit 1 is high (LRP = 1), the polarity assumption
is reversed.
INTERFACE CLOCKS AND SAMPLING RATES
Bits 6 (SF0) and 7 (SF1) of register 3 are used to control the sampling frequency, as shown in
Table 12.
SF0
0
SF1
0
SAMPLING FREQUENCY
44.1 kHz group
22.05 / 44.1 / 88.2 kHz
24 / 48 / 96 kHz
16 / 32 / 64 kHz
Not defined
0
1
48 kHz group
32 kHz group
Reserved
1
0
1
1
Table 12 Sampling Frequencies
INFINITE ZERO DETECTION
Bit 8 (IZD) in register 3 controls operation of the automute function. If IZD (Infinite Zero Detect) is
high, 1024 consecutive zero audio samples will force the output to zero. See Figure 6. Note that the
control of pin MUTE also affects automute operation. To turn off automute, pin MUTE must be held
low as well as IZD being low (default).
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RECOMMENDED EXTERNAL COMPONENTS
DVDD
AVDD
+
19
11
10
DVDD
AVDD
AGND
+
C1
C2
C3
C4
20
DGND
AGND
DGND
C5
4
5
6
7
9
ML/I2S
MC/IWL
MD/DM
RSTB
VOUTR
VOUTL
AC-Coupled
Output to
External LPF
+
C6
Software I/F or
Hardware Control Pins
12
+
AVDD
R1
18
1
MODE
PWDN
MUTE
8
3
ZERO
TEST
CAP
17
13
+
2
SCKI
BCKIN
DIN
C7
C8
14
15
16
Audio Serial Data I/F
AGND
LRCIN
NOTES:
1. AGND and DGND should be connected as close to the WM8720 as possible.
2. C2, C3 and C7 should be positioned as close to the WM8720 as possible.
3. Capacitor types should be carefully chosen. Capacitors with very low ESR are
recommended for optimum performance.
Figure 8 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1 and C4
C2 and C3
C5 and C6
C7
10µF
0.1µF
10µF
0.1µF
10µF
10kΩ
Output AC coupling caps to remove midrail DC level from outputs.
Reference de-coupling capacitors for CAP pin.
C8
R1
Resistor to AVDD for open drain output operation.
Table 13 External Components Description
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PACKAGE DIMENSIONS
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
DM0015.B
b
e
20
11
E1
E
GAUGE
PLANE
Θ
1
10
D
0.25
L
c
A1
A A2
L
1
-C-
0.10 C
SEATING PLANE
Dimensions
(mm)
NOM
-----
Symbols
MIN
-----
MAX
2.0
-----
1.85
0.38
0.25
7.50
A
A1
A2
b
c
D
e
E
E1
L
0.05
1.65
0.22
0.09
6.90
-----
1.75
0.30
-----
7.20
0.65 BSC
7.80
7.40
5.00
0.55
8.20
5.60
0.95
5.30
0.75
L1
θ
0.125 REF
0o
4o
8o
-
JEDEC.95, MO 150
REF:
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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IMPORTANT NOTICE
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service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
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WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical
components in life support devices or systems without the express written approval of an officer of the company. Life
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
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Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that
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ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
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