WM8725CGED/R [WOLFSON]
99dB Stereo DAC; 99分贝立体声DAC
| 型号： | WM8725CGED/R |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | 99dB Stereo DAC |
| 文件： | 总14页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8725
w
99dB Stereo DAC
DESCRIPTION
FEATURES
99dB SNR performance
WM8725 is a high-performance stereo DAC designed for
use in portable audio equipment, video CD players and
similar applications. It comprises selectable normal or I2S
compatible serial data interfaces for 16 to 24-bit digital
inputs, high performance digital filters, and sigma-delta
output DACs, achieving an excellent 99dB signal-to-noise
performance.
Stereo DAC with input sampling from 8kHz to 96kHz
Additional mute feature
Normal or I2S compatible data format
Sigma-delta design with 64x oversampling
System clock 256fs or 384fs
Supply range 3V to 5V
14-lead SOIC package
The device is available in a 14-lead SOIC package that
offers selectable mute and de-emphasis functions using a
minimum of external components.
APPLICATIONS
Portable audio equipment
Video CD players
BLOCK DIAGRAM
Production Data, February 2012, Rev 4.3
WOLFSON MICROELECTRONICS plc
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Copyright 2012 Wolfson Microelectronics plc.
WM8725
Production Data
TABLE OF CONTENTS
DESCRIPTION................................................................................................................ 1
FEATURES..................................................................................................................... 1
APPLICATIONS.............................................................................................................. 1
BLOCK DIAGRAM ......................................................................................................... 1
TABLE OF CONTENTS.................................................................................................. 2
PIN CONFIGURATION................................................................................................... 3
ORDERING INFORMATION........................................................................................... 3
ABSOLUTE MAXIMUM RATINGS................................................................................. 4
RECOMMENDED OPERATING CONDITIONS.............................................................. 4
ELECTRICAL CHARACTERISTICS .............................................................................. 5
PIN DESCRIPTION......................................................................................................... 6
INTERNAL POWER ON RESET...............................................................................................6
DEVICE DESCRIPTION ................................................................................................. 8
INTRODUCTION .......................................................................................................................8
DAC CIRCUITS .........................................................................................................................8
SERIAL DATA INTERFACE......................................................................................................9
SYSTEM CLOCK.....................................................................................................................10
RECOMMENDED EXTERNAL COMPONENTS........................................................... 11
DETAIL OF RECOMMENDED EXTERNAL COMPONENTS SHOWING THE EXTERNAL
LOW PASS FILTER.................................................................................................................11
PCB LAYOUT..........................................................................................................................11
PACKAGE DIMENSIONS............................................................................................. 12
ADDRESS: ..............................................................................................................................13
REVISION HISTORY .................................................................................................... 14
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PIN CONFIGURATION
LRCIN
DIN
1
2
3
4
5
6
7
14
13
12
11
10
9
SCKI
FORMAT
DEEMPH
NC
BCKIN
NC
WM8725
CAP
MUTE
VOUTL
VDD
VOUTR
GND
8
ORDERING INFORMATION
DEVICE
TEMPERATURE
RANGE
PACKAGE
MOISTURE SENSITIVITY
LEVEL
PEAK BODY
TEMPERATURE
14-lead SOIC
(lead free)
WM8725CGED
-40oC to +85oC
-40oC to +85oC
MSL1
MSL1
260oC
14-lead SOIC
(Pb-free, tape and reel)
WM8725CGED/R
260oC
Note:
Reel quantity: 3,000
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating
at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and
storage of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
MAX
+7.0V
Supply voltage
Reference input
-0.3V
VCC+0.3V
+85oC
+150oC
+240oC
+183oC
-40oC
-65oC
Operating temperature range, TA
Storage temperature
Lead temperature (soldering, 10 seconds)
Lead temperature (soldering, 2 minutes)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
-10%
TYP
MAX
UNIT
Supply Range
VDD
GND
3.0 to 5.0
+10%
V
V
Ground
0
Supply Current
VDD = 5V
VDD = 3V
15
7.5
25
mA
mA
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ELECTRICAL CHARACTERISTICS
Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
Digital Logic Levels
Input LOW level
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIL
VIH
0.8
V
V
Input HIGH level
2.0
Analogue Output Levels
Load Resistance
To midrail or AC coupled
(5V supply)
1
1
kΩ
kΩ
To midrail or AC coupled
(3V supply)
Maximum capacitance load
Output DC level
5V or 3V
100
pF
V
VDD/2
Reference Levels
Potential divider resistance
80
100
2.5
120
2.7
kΩ
V
DD to CAP and CAP to GND
Voltage at CAP
VDD = 5V
2.3
V
DAC Circuit Specifications
SNR (Note 1)
VDD = 5V
VDD = 3V
90
99
97
dB
dB
Full scale output voltage
Into 10kohm VDD = 5V, 0dB
0.9
1.0
0.6
0.01
92
1.1
0.02
VRMS
VRMS
%
Into 10kohm VDD = 3V, 0dB
THD (Full scale)
0dB
THD+N (Dynamic range)
Frequency response
Transition band
-60dB
dB
0
20,000
Hz
20,000
Hz
Out of band rejection
Channel Separation
-40
90
±1
dB
dB
Gain mismatch
±5
%FSR
channel-to-channel
Audio Data Input and System Clock Timing Information
BCKIN pulse cycle time
tBCY
tBCH
tBCL
tBL
100
50
ns
ns
ns
ns
ns
BCKIN pulse width high
BCKIN pulse width low
50
BCKIN rising edge to LRCIN edge
30
LRCIN rising edge to BCKIN
rising edge
tLB
30
DIN setup time
tDS
tDH
tSCKIH
tSCKIL
30
30
13
13
ns
ns
ns
ns
DIN hold time
System clock pulse width high
System clock pulse width low
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured
“A” weighted over a 20Hz to 20kHz bandwidth.
2. All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher
THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass
filter removes out of band noise; although it is not audible, it may affect dynamic specification values.
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PIN DESCRIPTION
PIN
1
NAME
LRCIN
TYPE
Digital input
DESCRIPTION
Sample rate clock input
Serial data input
DIN
Digital input
Digital input
No connect
Analogue output
Analogue output
Supply
2
BCKIN
NC
Bit clock input
3
No internal connection
4
CAP
Analogue internal reference
Right channel DAC output
0V supply
5
VOUTR
GND
6
7
VDD
Supply
Positive supply
8
VOUTL
MUTE
NC
Analogue output
Digital input
No connect
Digital input
Digital input
Digital input
Left channel DAC output
Mute control, high = muted. Internal pull-down
No internal connection
9
10
11
12
13
14
DEEMPH
FORMAT
SCKI
De-emphasis select, high = de-emphasis ON. Internal pull-up
Data input format select, low = normal, high = I2S. Internal pull-up
System clock input (256fs or 384fs)
INTERNAL POWER ON RESET
The WM8725 includes an internal power-on reset circuit. This is shown in Figure 1.This reset
circuit is used to reset the digital logic into a default state after power up.
Figure 1 Internal Power on Reset Circuit
The timing of the power on reset is shown in Figure 2 The circuit monitors VDD and VMID
(CAP pin) and asserts PORB low when VMID is below the minimum threshold Vpor. It is
assumed that VMID will rise slower than VCC due to the capacitor on VMID.
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Figure 2 Power on/off Reset Timing
SYMBOL
Vpor
Min
0.85
2.25
Typ
1.0
2.5
Max
1.2
Unit
V
Vpor_off
2.75
V
Table 1 Power on/off Reset Timing
At power on, when VDD and VMID have been established, PORB is released and the
WM8725 has been reset.
At power down, PORB is asserted low whenever VMID drops below the minimum threshold of
Vpor_off.
If VDD is removed at any time, the internal power-on reset circuit is powered down and PORB
will follow VDD.
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DEVICE DESCRIPTION
INTRODUCTION
WM8725 is a complete stereo audio 16-24 bit digital-to-analogue converter, including digital
interpolation filter, multibit sigma-delta with dither, and switched capacitor multibit stereo DAC
and output smoothing filters.
Special functions of mute and de-emphasis are provided, and operation using system clock of
256fs or 384fs is provided, selection between either clock rate being automatically controlled.
Sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate system
clock is input.
MUTE
DESCRIPTION
Mute is OFF
Mute is ON
0
1
Table 2 Mute Control
A novel multi bit sigma-delta DAC design is used, utilising a 64x oversampling rate, to
optimise signal to noise performance and offer increased clock jitter tolerance.
Internally generated midrail references are used to DC bias output signals, requiring only a
single external capacitor for decoupling purposes.
Single 3V to 5V supplies may be used, the output amplitude scaling with absolute supply
level. Low supply voltage operation and low current consumption, and the low pin count small
package, make the WM8725 attractive for many consumer type applications.
DAC CIRCUITS
The WM8725 DACs are designed to allow playback of 16-bit PCM audio or similar data with
high resolution and low noise and distortion. Sample rates up to 96ks/s may be used, with
much lower sample rates acceptable provided that the ratio of sample rate (LRCIN) to system
clock is maintained at the required 256fs or 384fs times.
The DACs on WM8725 are implemented using sigma-delta oversampled conversion
techniques. These require that the PCM samples are digitally filtered and interpolated to
generate a set of samples at a much higher rate than the 96ks/s input rate. This sample
stream is then digitally modulated to generate a digital pulse stream that is then converted to
analogue signals in a switched capacitor DAC. The advantage of this technique is that the
DAC is linearised using noise shaping techniques, allowing the full performance to be met
using non-critical analogue components. A further advantage is that the high sample rate at
the DAC output means that smoothing filters on the output of the DAC need only have fairly
crude characteristics in order to remove the characteristic steps, or images, on the output of
the DAC. To ensure that generation of tones characteristic to sigma-delta convertors is not a
problem, dithering is used in the digital modulator and a higher order modulator is used. The
switched capacitor technique used in the DAC reduces sensitivity to clock jitter compared to
switched current techniques used in other implementations.
De-emphasis of 44.1kHz signals may be applied if required.
DEEMPH
DESCRIPTION
De-emphasis is OFF
De-emphasis is ON
0
1
Table 3 De-emphasis Control
The voltage on the CAP pin is used as the reference for the DACs, therefore the amplitude of
the signals at the DAC outputs will scale with the amplitude of the voltage at the CAP. An
external reference could be used to drive into the CAP pin if desired, but a value typically of
about midrail should be used for optimum performance.
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The outputs of the 2 DACs are buffered out of the device by buffer amplifiers. These
amplifiers will source load current of several mA and sink current up to 1.5mA, so allowing
significant loads to be driven. The output source is active and the sink is Class A, i.e. fixed
value, so greater loads might be driven if an external ‘pull-down’ resistor is connected at the
output.
Typically an external low pass filter circuit will be used to remove residual sampling noise of
the 64x oversampling used and if desired adjust the signal amplitude and device strength.
SERIAL DATA INTERFACE
WM8725 has serial interface formats that are fully compatible with both normal (MSB first, 16
bit right-justified) and I2S interfaces. The data format is selected with the FORMAT pin. When
FORMAT is LOW, normal data format is selected. When the format is HIGH, I2S format is
selected. It must be noted that in “packed” mode operation (exactly 32 BCLKs per LRCIN
period), the data word must align exactly with LRCIN clock edges (effectively both left and
right justified at the same time). This is true in both normal and I2S modes.
FORMAT
DESCRIPTION
Normal format
0
(MSB-first, 16 bit right justified)
I2S format
1
(Philips serial data protocol)
Table 4 Serial Interface Formats
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
Audio Data Word = 16-Bit
DIN
1
2
3
14 15
1
2
3
14 15
16
16
LSB
MSB
MSB
LSB
Figure 3 'Normal' Data Input Timing
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
Audio Data Word = 16-Bit
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
DIN
MSB
MSB
Figure 4 I2S Data Input Timing
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SYSTEM CLOCK
The system clock is used to operate the digital filters and the noise shaping circuits. The
system clock input is at pin 14 (SCKI). The frequency of WM8725’s system clock should be
set to 256fs or 384fs, (where fs is the audio sampling frequency). The sample rate is typically:
32 kHz, 44.1 kHz, 48 kHz or 96kHz.
WM8725 has a system clock detection circuit that automatically determines whether the
system clock being supplied is at 256fs or 384fs. The system clock should be synchronised
with LRCIN, but WM8725 is tolerant of phase differences. Severe distortion in the phase
difference between LRCIN and the system clock will be detected, and cause the device to
automatically resynchronise. During resynchronisation, the output of the device will either
repeat the previous sample, or drop the next sample, depending on the nature of the phase
slip. This will ensure minimal “click“ at the analogue outputs during resynchronisation.
tSCKIL
SCKI
tSCKIH
Figure 5 System Clock Timing Requirements
SYSTEM CLOCK FREQUENCY
SAMPLING
(MHz)
RATE (LRCIN)
256fs
384fs
32 kHz
8.192
12.288
44.1 kHz
48 kHz
96kHz
11.2896
12.288
24.5761
16.9340
18.432
36.8641
Table 5 System Clock Frequencies Versus Sampling Rate
Notes:
1
96kHz sample rate at either 256fs or 384fs are only supported with 5V supplies.
LRCIN
tBCH
tBCL
tLB
BCKIN
DIN
tBL
tBCY
tDS
tDH
Figure 6 Audio Data Input Timing
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RECOMMENDED EXTERNAL COMPONENTS
1
14
256fs/384fs CLK
LRCIN
SCKI
FORMAT
DEEMPH
FROM AUDIO
PROCESSOR
2
DIN
13
12
3
BCKIN
4
NC
WM8725
11
10
9
NC
MUTE
VOUTL
VDD
10µF
+
5
CAP
ANALOGUE
ANALOGUE
OUTPUT FOR
LEFT
OUTPUT
FOR RIGHT
CHANNEL
External
LPF
External
LPF
6
7
VOUTR
GND
CHANNEL
8
GND
VDD
0.1µF
10µF
Figure 7 Recommended External Components
DETAIL OF RECOMMENDED EXTERNAL COMPONENTS SHOWING THE EXTERNAL
LOW PASS FILTER
External LPF
x2 for Stereo Operation
-
Filtered
Analogue
Output
VOUTR
VOUTL
1500pF
10k
+
10k
10k
680pF
100pF
Figure 8 Third-Order Low Pass Filter (LPF) Example
An external low pass filter is recommended (see Figure 8) if the device is driving a wideband
amplifier. In some applications, second-order or passive RC filter may be adequate.
PCB LAYOUT
1.
2.
3.
Place all supply decoupling capacitors as close as possible to their respective supply
pins and provide a low impedance path from the capacitors to the appropriate ground.
Separate analogue and digital ground planes should be situated under respective
analogue and digital device pins.
Avoid noise on the CAP reference pin. The decoupling capacitor should be placed as
close to this pin as possible with a low impedance path from the capacitor to analogue
ground.
4.
5.
Digital input signals should be screened from each other and from other sources of
noise to avoid cross-talk and interference. They should also run over the digital ground
plane to avoid introducing unwanted noise into the analogue ground plane.
Analogue output signal tracks should be kept as short as possible and over the
analogue ground plane reducing the possibility of losing signal quality.
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PACKAGE DIMENSIONS
D: 14 PIN SOIC 3.9mm Wide Body
DM001.C
e
B
14
8
H
E
1
7
D
L
h x 45o
A1
SEATING PLANE
-C-
C
A
0.10 (0.004)
Dimensions
(MM)
Dimensions
(Inches)
Symbols
MIN
MAX
1.75
0.25
0.51
0.25
8.75
4.00
MIN
MAX
A
A1
B
C
D
E
1.35
0.10
0.33
0.19
8.55
3.80
0.0532
0.0040
0.0130
0.0075
0.3367
0.1497
0.0688
0.0098
0.0200
0.0098
0.3444
0.1574
e
1.27 BSC
0.05 BSC
H
h
L
5.80
0.25
0.40
0o
6.20
0.50
1.27
8o
0.2284
0.0099
0.0160
0o
0.2440
0.0196
0.0500
8o
REF:
JEDEC.95, MS-012
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Any use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or
services might be or are used. Any provision or publication of any third party’s products or services does not constitute
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document
belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is
not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any
reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
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REVISION HISTORY
DATE
REV
ORIGINATOR
CHANGES
Order codes updated from WM8725GED/V and WM8725GED/RV to
20/02/12
4.3
JMacD
WM8725CGED and WM8725CGED/R to reflect change to copper wire bonding.
20/02/12
01/02/12
4.3
4.3
JMacD
JMacD
MSL changed from MSL2 to MSL1.
Operating Temp changed to -40oC to +85oC
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