WM8737 [WOLFSON]
STEREO ADC WITH MICROPHONE PREAMPLIFIER; 用麦克风前置放大器的立体声ADC
| 型号： | WM8737 |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | STEREO ADC WITH MICROPHONE PREAMPLIFIER |
| 文件： | 总38页 (文件大小：535K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8737L
w
Stereo ADC with Microphone Preamplifier
DESCRIPTION
FEATURES
•
SNR 97dB (‘A’ weighted @ 3.3V, 48kHz, normal power
mode)
THD –85dB (at –1dB, 3.3V, normal power mode)
Complete Stereo / Mono Microphone Interface
The WM8737L is a low power stereo audio ADC designed
specifically for portable applications such as minidisc and
memory audio / voice recorders.
•
•
The device offers three sets of stereo inputs, which can be
configured for line-level signals, for internal or table-top
microphones, or for DC measurement (battery monitor). A
programmable gain amplifier can be used for automatic
level control (ALC) with user programmable hold, attack and
decay times. The device also has a selectable high pass
filter to remove residual DC offsets.
-
-
-
Programmable microphone preamp
Automatic Level Control
Low-noise microphone bias voltage
•
•
Configurable Power / Performance
Low Power Mode
-
-
8.5mW at AVDD = 1.8V (stereo, mic preamps off)
20mW at AVDD = 3.3V (stereo, mic preamps off)
•
Low Supply Voltages
If the signal source is mono, the WM8737L can run in mono
mode, saving power. It can also mix two channels to mono,
either in the analogue or the digital domain.
-
-
-
Analogue 1.8V to 3.6V
Digital core: 1.42V to 3.6V
Digital I/O: 1.8V to 3.6V
Master or slave mode clocking schemes are offered. Stereo
24-bit multi-bit sigma-delta ADCs are used with digital audio
output word lengths from 16-32 bits, and sampling rates
from 8kHz to 96kHz supported.
•
•
256fs / 384fs or USB master clock rates: 12MHz, 24MHz
Audio sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1,
48, 88.2, 96kHz generated internally from master clock
32-pin QFN package, 5 x 5 x 0.9mm
•
The device is controlled via a 2 or 3 wire serial interface.
The interface provides access to all features including gain
controls, analogue or digital mono mixing, and power
management facilities. The device is supplied in a leadless
5x5mm QFN package.
APPLICATIONS
•
•
•
Memory Audio / Voice Recorders
Minidisc Recorders
Portable Digital Music Systems
BLOCK DIAGRAM
Advanced Informion, May 2004, Rev 3.0
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
Copyright 2004 Wolfson Microelectronics plc
WM8737L
Preliminary Technical Data
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM .................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
PIN DESCRIPTION ................................................................................................4
ABSOLUTE MAXIMUM RATINGS.........................................................................5
RECOMMENDED OPERATING CONDITIONS .....................................................5
ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY............................................................................................................. 8
NOTES........................................................................................................................... 8
POWER CONSUMPTION ......................................................................................9
SIGNAL TIMING REQUIREMENTS.....................................................................11
DEVICE DESCRIPTION.......................................................................................14
INTRODUCTION.......................................................................................................... 14
INPUT SIGNAL PATH.................................................................................................. 14
ANALOGUE TO DIGITAL CONVERTER (ADC) .......................................................... 19
3D STEREO ENHANCEMENT..................................................................................... 20
AUTOMATIC LEVEL CONTROL (ALC) ....................................................................... 21
DIGITAL AUDIO INTERFACE...................................................................................... 24
MASTER CLOCK AND AUDIO SAMPLE RATES ........................................................ 28
CONTROL INTERFACE .............................................................................................. 30
POWER SUPPLIES..................................................................................................... 31
POWER MANAGEMENT............................................................................................. 31
REGISTER MAP...................................................................................................32
DIGITAL FILTER CHARACTERISTICS...............................................................33
TERMINOLOGY........................................................................................................... 33
APPLICATIONS INFORMATION .........................................................................35
LINE INPUT CONFIGURATION................................................................................... 35
MICROPHONE INPUT CONFIGURATION.................................................................. 35
RECOMMENDED EXTERNAL COMPONENTS ..................................................36
PACKAGE DIMENSIONS ....................................................................................37
IMPORTANT NOTICE..........................................................................................38
ADDRESS:................................................................................................................... 38
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Preliminary Technical Data
WM8737L
PIN CONFIGURATION
ORDERING INFORMATION
ORDER CODE
TEMPERATURE RANGE
PACKAGE
MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
TEMPERATURE
32-pin QFN (5x5x0.9mm)
lead free
MSL1
260°C
WM8737LGEFL
-25°C to +85°C
-25°C to +85°C
WM8737LGEFL/R
32-pin QFN (5x5x0.9mm)
lead free, tape
MSL1
260°C
and reel
Note:
Reel Quantity = 3,500
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Preliminary Technical Data
PIN DESCRIPTION
PIN NO
1
NAME
NC
TYPE
No Connect
DESCRIPTION
No Internal Connection
2
SCLK
Digital Input
Control Interface Clock Input
Digital Buffer (I/O) Supply
Digital Core Supply
3
DBVDD
DCVDD
DGND
Supply
4
Supply
5
Supply
Digital Ground (return path for both DCVDD and DBVDD)
No Internal Connection
6
NC
No Connect
7
MCLK
Digital Input
Master Clock
8
BCLK
Digital Input / Output
Digital Output
Digital Input / Output
Digital Input
Audio Interface Bit Clock
9
ADCDAT
ADCLRC
MODE
AGND
ADC Digital Audio Data
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Audio Interface Left / Right Clock
Control Interface Selection
Supply
Analogue Ground (return path for both AVDD and MVDD)
Microphone Bias
MICBIAS
MVDD
Analogue Output
Supply
Microphone Bias and Microphone Pre-amplifier Positive Supply
Analogue Positive Supply
AVDD
Supply
RACIN
RACOUT
RINPUT3
RINPUT2
RINPUT1
LINPUT1
LINPUT2
LINPUT3
LACOUT
LACIN
Analogue Input
Analogue Output
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Output
Analogue Input
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Supply
Right Channel DC Blocking Capacitor
Right Channel DC Blocking Capacitor
Right Channel Input 3
Right Channel Input 2
Right Channel Input 1
Left Channel Input 1
Left Channel Input 2
Left Channel Input 3
Left Channel DC Blocking Capacitor
Left Channel DC Blocking Capacitor
Midrail Voltage Decoupling Capacitor
Reference Voltage Decoupling Capacitor
Positive Reference Decoupling Connection
Negative Reference Decoupling Connection
Analogue Ground (return path for both AVDD and MVDD)
Chip Select / Device Address Selection
Control Interface Data Port
VMID
VREF
VREFP
VREFN
AGND
CSB
Digital Input
SDIN
Digital Input / Output
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Preliminary Technical Data
WM8737L
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling
and storage of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
CONDITION
MIN
MAX
+3.63V
Supply voltages
-0.3V
Voltage range digital inputs
Voltage range analogue inputs
DGND -0.3V
AGND -0.3V
AGND -0.3V
DBVDD +0.3V
AVDD +0.3V
MVDD +0.3V
40MHz
Voltage range LACIN, RACIN, LACOUT, RACOUT, MICBIAS
Master Clock Frequency
Operating temperature range, TA
Storage temperature after soldering
Notes:
-25°C
-65°C
+85°C
+150°C
1. Analogue and digital grounds must always be within 0.3V of each other.
2. All digital and analogue supplies are completely independent from each other.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
DCVDD
TEST CONDITIONS
MIN
1.42
1.8
TYP
MAX
3.6
UNIT
Digital supply range (Core)
Digital supply range (I/O Buffers)
Analogue supplies range
Ground
V
V
V
V
DBVDD
3.6
AVDD, MVDD
DGND, AGND
1.8
3.6
0
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Preliminary Technical Data
ELECTRICAL CHARACTERISTICS
Test Conditions
DCVDD = 1.5V, AVDD = MVDD = 3.3V, TA = +25oC, 1kHz -0.5dBFS signal, Normal Power Mode, fs = 48kHz, PGA gain = 0dB,
24-bit audio data, unless otherwise stated. Microphone preamplifier at maximum bias (default) and gain 13dB, unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Microphone Preamplifier (LINPUT1/2/3, RINPUT1/2/3) to ADC
Microphone Pre-amp (Boost)
Gain
MICBOOST = 00
13
18
28
33
6
dB
MICBOOST = 01
MICBOOST = 10
MICBOOST = 11
Voltage at 1kHz
Microphone preamplifier noise
(referred to input)
nV / √Hz
Micboost gain = 28dB
at 20Hz – 20kHz
(A-weighted)
0.7
-123
1
µV rms
dBV
mV
Micboost gain = 28dB
Input Offset Voltage
5
Microphone preamplifier Signal
to Noise Ratio
SNR
AVDD = 3.3V
600Ω Rsource
AVDD=1.8V
600Ω Rsource
28 dB gain,
109
dB
(A-weighted)
(Note 1)
102
94
AVDD = 3.3V
600Ω Rsource
Dynamic Range (Note 2)
DNR
THD
A-weighted, -60dBFS
Gain = 0dB
94
dB
Total Harmonic Distortion
(Note 3)
13dB gain,
-74
dB
%
AVDD = 3.3V, Single
Channel
0.0056
13dB gain,
-73
AVDD=1.8V, Single
Channel
0.02
Channel Separation
Power Supply Rejection Ratio
Input Leakage
-65
60
1
dB
dB
µA
PSRR
1kHz, 100mV pk-pk,
Microphone
-10
10
preamplifier enabled
Input Resistance
Ω
500k
Ω
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Preliminary Technical Data
WM8737L
Test Conditions
DCVDD = 1.5V, AVDD = MVDD = 3.3V, TA = +25oC, 1kHz -0.5dBFS signal, Normal Power Mode, fs = 48kHz, PGA gain = 0dB,
24-bit audio data, unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V rms
dB
Line Inputs (LINPUT1/2/3, RINPUT1/2/3) to ADC – MIC pre-amp BYPASSED
Full Scale Input Signal Level
(for ADC 0dB Input at 0dB Gain)
Signal to Noise Ratio
(A-weighted)
AVDD = 3.3V
AVDD = 1.8V
1.0
0.545
97
SNR
AVDD = 3.3V,
90
Normal Power Mode
AVDD = 2.7V,
(Note 1)
95
Normal Power Mode
AVDD = 1.8V,
92
Normal Power Mode
AVDD = 3.3V,
95
Low Power Mode
AVDD = 2.7V,
93
Low Power Mode
AVDD = 1.8V,
90
Low Power Mode
-60dBFS,
Dynamic Range
(A-weighted)
(Note 2)
DNR
THD
90
97
95
dB
Normal Power Mode
-60dBFS,
Low Power Mode
-1dB input
Total Harmonic Distortion
(Note 3)
-86 (0.007%)
dB
%
-1dB input,
AVDD=1.8V
-81 (0.009%)
105
ADC Channel Separation
(Note 4)
1kHz signal
dB
dB
Channel Matching
1kHz signal
0.2
Programmable Gain Amplifier (PGA)
Programmable Gain
-97
0
30
dB
dB
dB
Programmable Gain Step Size
Monotonic
0.5
Gain Error (Deviation from ideal
0.5dB/step gain characteristic)
1kHz signal
-0.2
0.2
Input Resistance
0dB gain
30
1.9
kΩ
30dB gain
Input Capacitance
16.9pF
pF
Automatic Level Control (ALC)
Typical Record Level
-18
-3
dB
Gain Hold Time (Note 5)
tHLD
tDCY
tATK
0, 2.67, 5.33, 10.67, … , 43691
(time doubles with each step)
33.6, 67.2, 134.4, … , 3441
(time doubles with each step)
8.4, 16.8, 33.6, … , 8600
ms
MCLK = 12.288MHz
(Note 3)
Gain Ramp-Up (Decay) Time
(Notes 6, 7)
ms
ms
Gain Ramp-Down (Attack) Time
(Notes 6, 7)
(time doubles with each step)
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WM8737L
Preliminary Technical Data
Test Conditions
DCVDD = 1.5V, AVDD = MVDD = 3.3V, TA = +25oC, 1kHz signal, Normal Power Mode, fs = 48kHz, PGA gain = 0dB, 24-bit
audio data, unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
–3%
–3%
TYP
MAX
+3%
+3%
UNIT
Analogue Reference Levels
Mid-rail Reference Voltage
VMID Output Resistance
Buffered Reference Voltage
Microphone Bias
VMID
RVMID
VREF
AVDD/2
75
V
kΩ
V
AVDD/2
Bias Voltage
VMICBIAS
MICBIAS = 01
MICBIAS = 10
0.75×AVDD
V
V
0.9×AVDD 0.9×AVDD 0.9×AVDD
–3%
+3%
MICBIAS = 11,
AVDD = 2.5V
1.2×AVDD
V
Bias Current Source
Output Noise Voltage
Digital Input / Output
Input HIGH Level
IMICBIAS
Vn
3
mA
1K to 20kHz
24
nV/√Hz
VIH
VIL
0.7×DBVDD
0.9×DBVDD
V
V
V
V
Input LOW Level
0.3×DBVDD
0.1×DBVDD
Output HIGH Level
Output LOW Level
VOH
VOL
IOH = 1mA
IOL = -1mA
TERMINOLOGY
1. Signal-to-noise ratio (dB) – for the microphone preamplifiers, quoted SNR is the ratio of the rms voltages of the full-
scale output at the L/RACOUT pins and the noise observed at these pins with no input signals. This figure indicates
only the microphone preamplifier noise and does not account for additional noise that will be added by the PGAs and
ADCs in obtaining the final digitised result. For the line inputs, quoted SNR is the ratio of the rms code ranges as
measured at the ADC output for a full-scale output signal and the noise observed with no input. This figure combines
the PGA and ADC noise contributions. (No Auto-zero or Auto-mute function is employed in achieving these results).
2. Dynamic range (dB) - DR measures the ratio in the ADC output between the full-scale signal power and all power
contributed by noise and spurious tones in the specified bandwidth. Normally THD+N is measured at 60dB below full
scale (to reduce any distortion components to negligible levels) and the measurement is then corrected by adding the
60dB to its magnitude. (e.g. THD+N @ -60dB= -32dB, DR= 60 + |-32| = 92dB).
3. Total Harmonic Distortion and Noise (dB) - THD+N is a ratio of the rms values of (Noise + Distortion) and Signal.
4. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring how much of this
signal appears at the output of the other channel.
5. Hold Time is the length of time between a signal detected by the ALC as being too quiet and beginning to ramp up
the gain. It does not apply to ramping down the gain when the signal is too loud, which happens without a delay.
6. Ramp-up and Ramp-Down times are defined as the time it takes for the PGA to sweep across 90% of its gain range.
7. All hold, ramp-up and ramp-down times scale proportionally with MCLK
NOTES
1. All performance measurements are done with a 20kHz low pass filter, and where noted an A-weight filter. Failure to
use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the
Electrical Characteristics. The low pass filter removes out of band noise; although this is not audible, it may affect
dynamic specification values.
2. VMID and VREF are each to be decoupled to a clean analogue ground with 10uF and 0.1uF capacitors placed as
close to the device package as possible. Smaller capacitors may reduce performance. VREFP should be connected
to VREF and VREFN should be connected to AGND using short PCB traces. It is not recommended to connect other
components to VMID or VREF in case of noise injection to the internal references of the device.
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Preliminary Technical Data
WM8737L
POWER CONSUMPTION
The power consumption of the WM8737L depends on the following factors.
•
Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power
savings (at the cost of reduced maximum SNR and THD performance).
•
Operating mode: Power consumption is lower when microphone pre-amps are not used. It can be also reduced in mono
or analogue mix-to-mono modes by switching off unused PGAs and ADCs via the power management register.
MODE DESCRIPTION
POWER MANAGEMENT REGISTER
SETTING
TYP. SUPPLY CURRENTS
TOTAL
POWER
(MILLIAMPS)
(mW)
IAVDD
IDBVDD
IDCVDD
MVDD = 1.8V, AVDD = 1.8V, DBVDD = 1.8V, DCVD = 1.5V, Low Power Mode, no MICBIAS or mic preamps
0.000
(<0.01)
0.692
(0.55)
1.978
(2.5)
0.000
(<0.01)
0.004
(<0.01)
0.011
0.007
(<0.01)
0.009
(<0.01)
1.633
0.011
(<0.02)
1.356
OFF
000000000
Standby
Mono (L/R)
110000000
6.029
8.299
6.537
111101000 / 111010100
111111100
3.205
(4.2)
0.018
0.017
1.666
1.640
Stereo / Digital Mono Mix
Analogue mono mix
2.543
(3.3)
111111000
111111100
(without dc monitoring via
Right ADC)
3.205
(4.2)
0.018
1.670
8.306
Analogue mono mix
(with continuous dc
monitoring via Right ADC)
+0.255
(+0.45)
-
-
-
-
+0.459
+1.688
Using MICBIAS in 0.9 X
AVDD mode in addition to
any of the above
Set appropriate MICBIAS[1:0] bits in
power management register
+0.692
(+0.7)
Using microphone boost
preamplifiers in addition to
any of the above
Set appropriate MBCTRL[1:0] bits in
register 09h and set LMBE and/or RMBE
bits in registers 02h and 03h
MVDD = 3.3V, AVDD = 3.3V, DBVDD = 3.3V, DCVDD = 1.5V, Low Power Mode, no MICBIAS or mic preamps
0.000
(<0.01)
1.288
(1.1)
0.000
(<0.01)
0.007
(<0.01)
0.018
0.007
(<0.01)
0.064
(<0.01)
1.624
0.011
(<0.02)
0.117
OFF
000000000
Standby
Mono (L/R)
110000000
2.993
(3.5)
12.173
17.273
14.648
111101000 / 111010100
111111100
4.453
(5.6)
0.031
0.018
1.650
1.620
Stereo / Digital Mono Mix
Analogue mono mix
3.684
(4.5)
111111000
111111100
(without dc monitoring via
Right ADC)
4.453
(5.6)
0.031
1.660
17.288
Analogue mono mix
(with continuous dc
monitoring via Right ADC)
+0.47
(+0.85)
-
-
-
-
+1.551
+4.663
Using MICBIAS in 0.9 X
AVDD mode in addition to
any of the above
Set appropriate MICBIAS[1:0] bits in
power management register
+1.413
(+1.3)
Using microphone boost
preamplifiers in addition to
any of the above
Set appropriate MBCTRL[1:0] bits in
register 09h and set LMBE and/or RMBE
bits in registers 02h and 03h
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Preliminary Technical Data
MVDD = 1.8V, AVDD = 1.8V, DBVDD = 1.8V, DCVDD = 1.5V, Normal Power Mode, no MICBIAS or mic preamps
0.000
(<0.01)
0.698
(0.55)
3.453
(4.6)
0.000
(<0.01)
0.004
(<0.01)
0.010
0.007
(<0.01)
0.069
(<0.01)
1.910
0.011
(<0.02)
1.367
OFF
000000000
Standby
110000000
9.098
13.959
11.116
Mono (L/R)
111101000 / 111010100
111111100
6.109
(8.3)
0.017
0.010
1.955
1.910
Stereo / Digital Mono Mix
4.574
(5.9)
Analogue mono mix
111111000
111111100
(without dc monitoring via
Right ADC)
6.109
(8.3)
0.017
1.940
13.937
Analogue mono mix
(with continuous dc
monitoring via Right ADC)
+0.252
(+0.45)
-
-
-
-
+0.454
+1.328
Using MICBIAS in 0.9 X
AVDD mode in addition to
any of the above
Set appropriate MICBIAS[1:0] bits in
power management register
+0.738
(+0.7)
Using microphone boost
preamplifiers in addition to
any of the above
Set appropriate MBCTRL[1:0] bits in
register 09h and set LMBE and/or RMBE
bits in registers 02h and 03h
MVDD = 3.3V, AVDD = 3.3V, DBVDD = 3.3V, DCVDD = 1.5V, Normal Power Mode, no MICBIAS or mic preamps
0.001
(<0.01)
1.288
(1.1)
0.000
(<0.01)
0.007
(<0.01)
0.020
0.007
(<0.01)
0.064
(<0.01)
1.905
0.014
(<0.02)
4.371
OFF
000000000
Standby
110000000
4.632
(5.8)
18.210
28.606
22.688
Mono (L/R)
111101000 / 111010100
111111100
7.750
(10.1)
5.996
(7.6)
0.032
0.020
1.950
1.890
Stereo / Digital Mono Mix
Analogue mono mix
111111000
111111100
(without dc monitoring via
Right ADC)
7.750
(10.1)
0.033
1.960
28.624
Analogue mono mix
(with continuous dc
monitoring via Right ADC)
+0.446
(+0.85)
-
-
-
-
+1.472
+4.640
Using MICBIAS in 0.9 X
AVDD mode in addition to
any of the above
Set appropriate MICBIAS[1:0] bits in
power management register
+1.406
(+1.3)
Using microphone boost
preamplifiers in addition to
any of the above
Set appropriate MBCTRL[1:0] bits in
register 09h and set LMBE and/or RMBE
bits in registers 02h and 03h
Table 1 Supply Current Consumption (see also “Power Management” section)
Notes:
1. TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 12.288 MHz (256fs), 24-bit data
2. All figures are quiescent, with no signal.
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Preliminary Technical Data
WM8737L
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
TMCLKL
TMCLKH
TMCLKY
13
13
26
ns
ns
ns
AUDIO INTERFACE TIMING – MASTER MODE
BCLK
(Output)
tDL
ADCLRC
(Output)
tDDA
ADCDAT
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
tDL
0
0
10
10
ns
ns
tDDA
AUDIO INTERFACE TIMING – SLAVE MODE
tBCH
tBCL
BCLK
tBCY
ADCLRC
tLRSU
tLRH
tDD
ADCDAT
Figure 3 Digital Audio Data Timing – Slave Mode
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Test Conditions
DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
tLRSU
tLRH
tDD
50
20
20
10
10
0
ns
ns
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
ADCLRC set-up time to BCLK rising edge
ADCLRC hold time from BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
10
CONTROL INTERFACE TIMING – 3-WIRE MODE
tCSL
tCSH
CSB
tCSS
tSCY
tSCS
tSCH
tSCL
SCLK
SDIN
LSB
tDSU
tDHO
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
tSCS
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
tSP
40
80
40
40
10
10
10
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes which will be suppressed
5
CONTROL INTERFACE TIMING – 2-WIRE MODE
t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t7
t1
t9
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
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Test Conditions
DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
400
kHz
ns
us
ns
ns
ns
ns
ns
ns
ns
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
600
1.3
600
600
100
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
300
300
600
900
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DEVICE DESCRIPTION
INTRODUCTION
The WM8737L is a low power analogue to digital converter (ADC) designed for audio recording. Its
features, performance and low power consumption make it ideal for recordable CD players, MP3
players, portable MD players and PDAs.
The device includes three stereo analogue inputs with a multiplexer to select between inputs. Each
input can be used as either a line level input or as a microphone input with on-chip microphone pre-
amplifiers. A programmable gain amplifier provides additional gain or attenuation, and can be used
for automatic level control (ALC), keeping the recording volume constant. It is also possible to use
the WM8737L as a mono device, or to mix the two channels to mono, either in the analogue or in the
digital domain.
The ADC is of a high quality using a multi-bit high-order oversampling architecture delivering high
SNR at low power consumption. It can operate at oversampling rates of 64fs (low power mode) or
128fs (normal power mode), allowing users to design for low power consumption or high
performance. The ADC also includes a digital high pass filter to remove unwanted DC components
from the audio signal. This filter may be turned off for DC measurements.
The output from the ADC is available on a configurable digital audio interface. It supports a number
of audio data formats including I2S, DSP Mode, Left justified and Right justified, and can operate in
master or slave modes.
The WM8737L master clock can be either an industry standard 256/384 fs clock or a 12MHz/24MHz
USB clock. Sample rates of 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz,
48kHz, 88.2kHz and 96kHz can be generated directly from the master clock, without an external PLL.
The digital filters are optimised for each sample rate.
The WM8737L can be controlled through a 2 wire or 3 wire MPU control interface. It is fully
compatible and an ideal partner for a range of industry standard microprocessors, controllers and
DSPs.
The design of the WM8737L has minimised power consumption without compromising performance.
It can operate at very low voltages, can power off parts of the circuitry under software control and
includes standby and power off modes.
INPUT SIGNAL PATH
The signal path consists of a multiplexer switch to select between three sets of analogue inputs,
followed by a microphone boost preamplifier with selectable gain settings of 13dB, 18dB, 28dB and
33dB.
The microphone preamplifier feeds into a PGA (programmable gain amplifier) via an external
capacitor which removes dc offsets that could otherwise produce zipper noise when the PGA gain
changes. Alternatively, for line input signals, the microphone preamplifier can be bypassed to reduce
power consumption and noise. The PGA gain can be controlled either by the user or by the on-chip
ALC function (see Automatic Level Control).
The output signal from each PGA (left and right) enters an ADC where it is digitised. The two
channels can also be mixed in the analogue domain and digitised in one ADC while the other ADC is
switched off to reduce power consumption (see “Power Management” section). The mono-mix signal
appears on both digital output channels.
LEFT AND RIGHT CHANNEL SIGNAL INPUTS
The WM8737L has two sets of low capacitance ac coupled analogue inputs, LINPUT1, LINPUT2,
LINPUT3 and RINPUT1, RINPUT2, RINPUT3. The LINSEL and RINSEL control bits select between
them. These inputs can be configured as microphone or line inputs by enabling or disabling the
microphone preamplifier. All inputs have high impedance when the preamplifier is used and their
impedance is between 1.8kΩ and 50kΩ (depending on PGA gain) if the preamplifier is bypassed.
The signal inputs are internally high-impedance biased to the reference voltage, VREF. Whenever
line inputs are muted or the device is placed into standby mode 2 (see “Power Management”
section), the inputs stay biased to VREF. This reduces any audible clicks that may otherwise be
heard when changing inputs or awakening from standby.
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WM8737L
DC MEASUREMENT
For dc measurements (battery voltage monitoring for example), the LINPUT1 and/or RINPUT1 pins
can be taken directly into the respective ADC, bypassing the microphone preamplifier and PGA.
In dc mode the ADC output is mid-scale for L/RINPUT1 voltage AGND and full-scale for L/RINPUT
voltage 1.7 x AVDD. Note that L/RINPUT1 must not exceed AVDD and so a voltage divider will be
required to bring the battery voltage into range.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2 (02h)
8:7 LINSEL
00
Left Channel Input Select
00: LINPUT1
Analogue Audio
Path Control
01: LINPUT2
(Left Channel)
10: LINPUT3
11: dc measure on LINPUT1
Left Channel Microphone Gain Boost
00: 13dB boost
6:5 LMICBOOST[1:0]
00
01: 18dB boost
10: 28dB boost
11: 33dB boost
4
LMBE
0
Left Channel Mic Boost Enable
0: Mic preamp disabled, bypass switch
is closed.
1: Mic preamp is enabled, bypass
switch is open.
R3 (03h)
8:7 RINSEL
00
Right Channel Input Select
00: RINPUT1
Analogue Audio
Path Control
01: RINPUT2
(Right Channel)
10: RINPUT3
11: dc measure on RINPUT1
Right Channel Microphone Gain Boost
Same as LMICBOOST
Right Channel Mic Boost Enable
Same as LMBE
6:5 RMICBOOST[1:0]
00
0
4
RMBE
Table 2 Input Software Control
The internal VREF input bias may cause unwanted loading of any potential divider connected to
L/RINPUT1 for the purpose of dc measurement. In this case, the internal bias sources can be
disabled by setting the appropriate bits of register R10 to zero.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R10 (0Ah)
0
RINPUT1 dc
BIAS ENABLE
1
0: Disable dc bias to RINPUT1
1: Enable dc bias to RINPUT1
0: Disable dc bias to LINPUT1
1: Enable dc bias to LINPUT1
DC Measure
Control
1
LINPUT1 dc BIAS
ENABLE
1
Table 3 DC Measurement Bias Control
MICROPHONE PREAMPLIFER BYPASS AND BIAS CONTROL
When the Left or Right microphone preamplifier is disabled the user has two options for driving the
corresponding Left or Right PGA.
Default operation is to close a preamplifier bypass switch that connects the PGA input directly to the
L/RINPUT1/2/3 multiplexer output.
If the application has only a single left or right line level signal source and hence does not require the
multiplexer or microphone preamplifier, then better PGA gain accuracy and THD+N performance are
obtained by disabling the multiplexer and bypass switch and driving the PGA directly via the L/RACIN
pin. The multiplexer and switch are disabled by setting to zero the appropriate L/RBYPEN bit in
register R9. The L/RINPUT1/2/3 pads remain biased to VREF. These bits should be set to 1 if the
multiplexer is required (always required when the microphone preamplifier is enabled).
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The user can also adjust the microphone preamplifier bias settings to optimise THD+N versus supply
current consumption for their application. Default is full bias for best THD+N performance, but the
user can reduce the bias to 75%, 50% or 25% of default by programming MBCTRL[1:0] in register
R9.
REGISTER
ADDRESS
BIT
LABEL
RBYPEN
DEFAULT
DESCRIPTION
R9 (09h)
3
1
Right channel bypass enable
Microphone
Preamplifiers
Control
0: Bypass switch is always open.
RINPUT1/2/3 high-impedance biased to
AVDD/2. RPGA input is RACIN pin.
1: Close bypass switch when right mic
preamp is disabled.
2
LBYPEN
1
Left channel bypass enable
0: Bypass switch is always open.
LINPUT1/2/3 high-impedance biased to
AVDD/2. LPGA input is LACIN pin.
1: Close bypass switch when left mic
preamp is disabled.
1:0 MBCTRL[1:0]
11
Bias control for left and right
microphone preamplifiers
00: bias 25%
01: bias 50%
10: bias 75%
11: nominal (100%) bias
Table 4 Microphone Preamplifier Control
MONO-MIXING
The WM8737L can operate as a stereo or mono device, or the two channels can be mixed to mono
in either the analogue domain (before the ADC) or in the digital domain (after the ADC). In all mono
and mono-mix modes unused circuitry can be switched off to save power (see “Power Management”
section). 3D stereo enhancement (See “3D Stereo Enhancement” section) is automatically disabled
in all mono and mono-mix modes.
In analogue mono-mix mode, the signals are mixed in the Left ADC and the Right ADC automatically
switches to dc measurement mode on pin RINPUT1. If dc measurement mode is not required then
the Right ADC can be powered down by setting bit 2 (ADCR) in the power management register R6.
Note that the high pass filter must be disabled if d.c. measurements are required.
In stereo and mono modes the Left/Right ADC data appear at the corresponding Left/Right Channel
outputs. In digital mono-mix mode the mixed data appears on both the Left and Right Channel
outputs. In analogue mono-mix mode the MONOUT bit controls whether the Right channel output
presents the data from the Right ADC (dc measurement) or a copy of the Left Channel (mixed)
output.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5 (05h)
8:7
MONOMIX[1:0]
00
00: Stereo
ADC Control
01: Analogue Mono-mix
10: Digital Mono-mix
11: Reserved
R5 (05h)
1
MONOUT
0
Analogue mono-mix format control
ADC Control
0: Left ADC data appears on Left
Channel output and Right ADC data
appears on Right Channel Output.
1: Left ADC data appears on both Left
and Right channel outputs.
Table 5 Mono Mixing Control
Note: In stereo mode (R5) 00, Bit 1 must always be set to 0.
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WM8737L
MICROPHONE BIAS
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type
microphones and the associated external resistor biasing network. The output voltage is derived from
VREF and is programmable in three steps from 0.75 × AVDD to 1.2 × AVDD, as shown below.
Supply voltage MVDD must be at least 170mV higher than the desired MICBIAS voltage to ensure
correct MICBIAS operation.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R6 (06h)
1:0
MICBIAS[1:0]
00
Microphone Bias Control
Power
Management
00: MICBIAS OFF (powered down,
high-impedance output)
01: VMICBIAS = 0.75 × AVDD
10: VMICBIAS = 0.9 × AVDD
11: VMICBIAS = 1.2 × AVDD
Table 6 MICBIAS Control
The internal MICBIAS circuitry is shown below. MVDD is a separate power supply pin used only for
MICBIAS and the microphone preamplifiers. When MICBIAS < AVDD, then MVDD can be tied to
AVDD. However, when MICBIAS = 1.2 × AVDD, then MVDD must be large enough to generate this
output voltage, i.e. it must be higher than AVDD.
Note: The maximum voltage for MVDD of 3.6V must be observed.
MVDD
VREF
MICBIAS
internal
resistor
AGND
Figure 6 Microphone Bias Schematic
Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors
therefore must be large enough to limit the MICBIAS current to 3mA. Please refer to the
“Applications Information” section for recommended external components.
PGA CONTROL
The Left and Right PGAs match the input signal levels to the ADC input ranges. The PGA gain is
logarithmically adjustable from –97dB to +30dB in 0.5dB steps. Each PGA can be controlled either
by the user or by the ALC function (see “Automatic Level Control” section). When ALC is enabled for
one or both channels then writing to the corresponding PGA gain control register has no effect. The
gain is independently adjustable on both Right and Left Line Inputs. By setting the LVU or RVU bits
whilst programming the PGA gain, both channels can be simultaneously updated. The inputs can
also be muted under software control. The PGA control register maps are shown in Table 7 PGA
Software Control.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R0 (00h)
7:0
LINVOL[7:0]
C3h
( 0dB )
Left Channel Input Volume Control
00000000: MUTE
00000001: -97dB
00000010: -96.5dB
…
Left Channel
PGA
11000011: 0dB
…
11111111: +30dB
Left PGA volume update
8
LVU
0
0: Store LINVOL in left intermediate
latch but do not update left gain.
1: Update both PGA gains
simultaneously (left gain = LINVOL,
right gain = right intermediate latch).
R1 (01h)
Right Channel
PGA
7:0
8
RINVOL[7:0]
RVU
C3h
( 0dB )
0
Right Channel Input Volume Control.
Same as LINVOL.
Right PGA volume update
0: Store RINVOL in right
intermediate latch but do not update
right gain.
1: Update both PGA gains
simultaneously (right gain =
RINVOL, left gain = left intermediate
latch).
Table 7 PGA Software Control
ZERO-CROSS DETECTION
To avoid zipper or click noises, it is preferable to change the microphone preamplifier and PGA gains
only when the input signal is at zero. The WM8737L has built-in zero-cross detectors to achieve this.
This function is enabled by setting the LMZC, LPZC, RMZC and RPZC bits. The zero-cross detection
feature includes a programmable time-out, selected by writing to LZCTO[1:0] and RZCTO[1:0]. If no
zero crossing occurs within the time-out period then the WM8737L changes the PGA or microphone
preamplifier gains when the time-out elapses.
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WM8737L
REGISTER
ADDRESS
BIT
LABEL
LMZC
DEFAULT
DESCRIPTION
R2 (02h)
Audio Path Left
3
None (first
gain
change
would
Left Mic preamp Zero-Cross Enable
0: Change gain immediately
1: Change gain on zero crossing only
overwrite!)
2
LPZC
1
Left PGA Zero-Cross Enable
0: Change gain immediately
1: Change gain on zero crossing only
Left Zero-Cross Time-Out
00: 256/fs
1:0
LZCTO[1:0]
11
01: 512/fs
10: 1024/fs
11: 2048/fs (42.67ms at 48kHz)
This timeout applies to both the PGA
and mic preamp zero-cross watchdog
timers.
R3 (03h)
3
RMZC
None
1
Right Mic preamp Zero-Cross Enable
Same as LMZC but for right channel
Right PGA Zero-Cross Enable
Audio Path
Right
2
RPZC
Same as LMZC but for right channel
Right Zero-Cross Time-Out
1:0
RZCTO[1:0]
11
Same as LMZC but for right channel
Table 8 Zero-Cross Detection Control
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8737L uses a multi-bit, oversampled sigma-delta ADC for each channel. The use of multi-bit
feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The
ADC full-scale input level is proportional to AVDD. With a 3.3V supply voltage the full scale level is
1.0 Volt rms (+/-1.414 Volts peak). Any voltage greater than full-scale will overload the ADC and
cause distortion.
ADC THD+N VERSUS POWER CONTROL
The ADCs can be operated in ‘normal mode’, which offers best THD+N performance at the cost of
highest power dissipation, or in ‘low power mode’ which offers significant power savings at the cost of
slightly reduced THD+N performance. The ADCs operating mode is controlled by the LP bit in
register R5. See the ‘Power Consumption’ section for power requirements in both modes.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5 (05h)
ADC Control
2
LP
0
ADC power mode control
0: Both ADCs in normal mode (best
THD+N)
1: Both ADCs in low power mode
Table 9 ADC Power Control
ADC DIGITAL FILTER
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital
filter path is illustrated below.
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Figure 7 ADC Digital Filter
The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass
filter response is detailed in the “Digital Filter Characteristics” section. When the high-pass filter is
enabled the dc offset is continuously calculated and subtracted from the input signal. By setting
HPOR, the last calculated d.c. offset value is maintained but still subtracted from the input.
The output data format can be programmed by the user to accommodate stereo or monophonic
recording on both inputs. The polarity of the output signal can also be changed under software
control. The software control is shown below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5 (05h)
ADC Control
0
4
ADCHPD
0
ADC High Pass Filter Enable (Digital)
1: Disable High Pass Filter
0: Enable High Pass Filter
Store dc offset
HPOR
0
0: Present offset maintained
1: Continuously update offset
00: Polarity not inverted
01: L polarity invert
6:5
POLARITY
00
10: R polarity invert
11: L and R polarity invert
Table 10 ADC Control
3D STEREO ENHANCEMENT
The WM8737L has a 3D stereo enhancement function for use in applications where the natural
separation between stereo channels is low. The function is activated by the 3DEN bit, and artificially
increases the separation between the left and right channels. The 3DDEPTH setting controls the
degree of stereo expansion. Additionally, one of four filter characteristics can be selected for the 3D
processing, using the 3DFILT control bits.
When 3D enhancement is enabled (and/or the tone control for playback) it may be necessary to
attenuate the signal by 6dB to avoid limiting. This is a user selectable function, enabled by setting
DIV2.
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WM8737L
REGISTER
ADDRESS
BIT
LABEL
3DEN
DEFAULT
DESCRIPTION
3D function enable
R4 (04h)
0
0
3D Control
0: disable
1: enable
4:1
3DDEPTH[3:0]
0000
Stereo depth
0000: 0% (minimum 3D effect)
0001: 6.67%
....
1110: 93.3%
1111: 100% (maximum 3D effect)
Upper Cut-off frequency
0 = High (2.2kHz at 48kHz sampling)
1 = Low (1.5kHz at 48kHz sampling)
Lower Cut-off frequency
0 = Low (200Hz at 48kHz sampling)
1 = High (500Hz at 48kHz sampling)
ADC 6dB attenuate enable
0: disabled (0dB)
5
6
7
3DUC
3DLC
DIV2
0
0
0
1: -6dB enabled
Table 11 Stereo Enhancement Control
AUTOMATIC LEVEL CONTROL (ALC)
The WM8737L has an automatic level control that aims to keep a constant recording volume
irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that
the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output
and changes the PGA gain if necessary.
input
signal
PGA
gain
signal
after
ALC
ALC
target
level
hold decay
time time
attack
time
Figure 8 ALC Operation
The ALC function is enabled using the ALCSEL[1:0] control bits in register R12. When enabled, the
recording volume can be programmed between -3dB and -18dB (relative to ADC full scale) using the
ALCL[3:0] register bits in register R12.
R13 and R14 bits HLD[3:0], DCY[3:0] and ATK[3:0] control the hold, decay and attack times,
respectively:
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Hold time is the time delay between the peak level detected being below target and the PGA gain
beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g. 2.67ms, 5.33ms,
10.67ms etc. up to 43.7ms. Alternatively, the hold time can also be set to zero. The hold time only
applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is
above target.
Decay time (Gain Ramp-Up) is the time that it takes for the PGA gain to ramp up across 90% of its
range (e.g. from –15dB up to 25.5 dB). The time it takes for the recording level to return to its target
value therefore depends on both the decay time and on the gain adjustment required. If the gain
adjustment is small, it will be shorter than the decay time. The decay time can be programmed in
power-of-two (2n) steps, from 33.6ms, 67.2ms, 134.4ms etc. to 34.41s.
Attack time (Gain Ramp-Down) is the time that it takes for the PGA gain to ramp down across 90%
of its range (e.g. from 25.5dB down to -15dB gain). The time it takes for the recording level to return
to its target value therefore depends on both the attack time and on the gain adjustment required. If
the gain adjustment is small, it will be shorter than the attack time. The attack time can be
programmed in power-of-two (2n) steps, from 8.4ms, 16.8ms, 33.6ms etc. to 8.6s.
When operating in stereo, the peak detector takes the maximum of left and right channel peak
values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is
preserved. However, the ALC function can also be enabled on one channel only. In this case, only
one PGA is controlled by the ALC mechanism, while the other channel runs independently with its
PGA gain set through the control register.
When one ADC channel is unused or used for dc measurement, the peak detector disregards that
channel. The ALC function can operate in digital mono mix mode (MONOMIX = 10), but not in
analogue mono mix mode (MONOMIX = 01).
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WM8737L
REGISTER
ADDRESS
BIT
8:7
LABEL
DEFAULT
00
DESCRIPTION
ALC function select
R12 (0Ch)
ALCSEL[1:0]
ALC Control 1
00 = ALC off (PGA gain set by
register)
01 = Right channel only
10 = Left channel only
11 = Stereo (PGA registers unused)
Set maximum gain for the PGA
111 : +30dB
6:4
3:0
MAXGAIN
ALCL[3:0]
111
110 : +24dB
…..(-6dB steps)
001 : -6dB
000 : -12dB
1100
ALC target level – sets signal level
after PGA at ADC input in 1dB steps
0000: -18dB FS
0001: -17dB FS
…
1110: -4dB FS
1111: -3dB FS
R13 (0Dh)
3:0
HLD[3:0]
0000
ALC hold time before gain is
increased
ALC Control 2
0000: 0ms
0001: 2.67ms
0010: 5.33ms
… (time doubles with every step)
1111: 43.691s
4
ALCZCE
ATK[3:0]
0
Enable zero-cross function for the
ALC gain updates
0: Zero-cross disabled
1: Zero-cross enabled
ALC attack (gain ramp-down) time
0000: 8.4ms
R14 (0Eh)
3:0
0010
ALC Control 3
0001: 16.8ms
0010: 33.6ms
… (time doubles with every step)
1010 or higher = 8.6s
ALC decay (gain ramp-up) time
0000: 33.6ms
7:4
DCY[3:0]
0011
0001: 67.2ms
0010: 134.4ms
… (time doubles with every step)
1010 or higher = 34.41s
Table 12 ALC Control
PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a
limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dBFS), the PGA gain is
ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below
87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.
(Note: If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed
to prevent clipping when long attack times are used.)
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NOISE GATE
When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise
pumping”, i.e. loud hissing noise during silence periods. The WM8737L has a noise gate function
that prevents noise pumping by comparing the signal level at the LINPUT1/2/3 and/or RINPUT1/2/3
pins against a noise gate threshold, NGTH. The noise gate cuts in when:
•
Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic preamp gain [dB]
This is equivalent to:
•
Signal level at input pin [dB] < NGTH [dB]
When the noise gate is triggered, the PGA gain is held constant (preventing it from ramping up as it
would normally when the signal is quiet).
The table below summarises the noise gate control register. The NGTH control bits set the noise
gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps.
Levels at the extremes of the range may cause inappropriate operation, so care should be taken with
set–up of the function. Note that the noise gate only works in conjunction with the ALC function, and
always operates on the same channel(s) as the ALC (left, right, both, or none).
REGISTER
ADDRESS
BIT
LABEL
NGAT
DEFAULT
DESCRIPTION
R11 (0Bh)
0
0
Noise gate function enable
1 = enable
Noise Gate
Control
0 = disable
4:2
NGTH[2:0]
000
Noise gate threshold (with respect to
ADC output level)
000: -78dBFS
001: -72dBfs
… 6 dB steps
110: -42dBFS
111: -30dBFS
Table 13 Noise Gate Control
DIGITAL AUDIO INTERFACE
The digital audio interface uses three pins:
•
•
•
ADCDAT: ADC data output
ADCLRC: ADC data alignment clock
BCLK: Bit clock, for synchronisation
The digital audio interface takes the data from the internal ADC digital filters and places it on
ADCDAT and ADCLRC. ADCDAT is the formatted digital audio data stream output from the ADC
digital filters with left and right channels multiplexed together. ADCLRC is an alignment clock that
indicates whether Left or Right channel data is present on the ADCDAT line. ADCDAT and ADCLRC
are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low
transition. ADCDAT is always an output. BCLK and ADCLRC may be inputs or outputs depending
whether the device is in master or slave mode (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
•
•
•
•
Left justified
Right justified
I2S
DSP mode
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
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WM8737L
MASTER AND SLAVE MODE OPERATION
The WM8737L can be configured as either a master or slave mode device. As a master device the
WM8737L generates BCLK and ADCLRC and thus controls sequencing of the data transfer on
ADCDAT. In slave mode, the WM8737L responds with data to clocks it receives over the digital
audio interface. The mode can be selected by writing to the MS bit (see Table 14). Master and slave
modes are illustrated below.
BCLK
ADCLRC
ADCDAT
BCLK
ADCLRC
ADCDAT
WM8737
ADC
DSP /
ENCODER
WM8737
ADC
DSP /
ENCODER
Figure 9a Master Mode
Figure 9b Slave Mode
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an ADCLRC
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each ADCLRC
transition.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
ADCDAT
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Figure 10 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before an ADCLRC
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each ADCLRC transition.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
ADCDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 11 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following an ADCLRC
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one
sample and the MSB of the next.
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1/fs
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
1 BCLK
1 BCLK
ADCDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 12 I2S Justified Audio Interface (assuming n-bit word length)
In DSP mode, the left channel MSB is available on either the 1st or 2nd rising edge of BCLK
(selectable by LRP) following a rising edge of ADCLRC. Right channel data immediately follows left
channel data. Depending on word length, BCLK frequency and sample rate, there may be unused
BCLK cycles between the LSB of the right channel data and the next sample.
Figure 13 DSP Mode Audio Interface
1/fs
1 BCLK
DACLRC/
ADCLRC
BCLK
RIGHT CHANNEL
LEFT CHANNEL
DACDAT/
ADCDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
Input Word Length (WL)
Figure 14 DSP Mode Audio Interface (mode B, LRP=1)
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master/slave mode are summarised
below. Note that dynamically changing the software format may cause erroneous operation of the
interfaces and is therefore not recommended.
All ADC data is signed 2’s complement. The length of the digital audio data is programmable at
16/20/24 or 32 bits, as shown below. The ADC digital filters process data using 24 bits. If the
WM8737L is programmed to output 16 or 20 bit data then it strips the LSBs from the 24 bit data. If
the device is programmed to output 32 bits then it packs the LSBs with zeros.
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WM8737L
REGISTER
ADDRESS
BIT
LABEL
FORMAT
DEFAULT
10
DESCRIPTION
R7 (07h)
1:0
Audio Data Format Select
11: DSP Mode
10: I2S Format
Digital Audio
Interface
Format
01: Left justified
00: Right justified
Audio Data Word Length
11: 32 bits (see Note)
10: 24 bits
3:2
WL
10
0
01: 20 bits
00: 16 bits
4
LRP
right, left & I2S modes – ADCLRC
polarity
1 = invert ADCLRC polarity
0 = normal ADCLRC polarity
DSP Mode – mode A/B select
1 = MSB is available on 1st BCLK
rising edge after ADCLRC rising edge
(mode B)
0 = MSB is available on 2nd BCLK
rising edge after ADCLRC rising edge
(mode A)
6
7
MS
0
0
Master / Slave Mode Control
1: Master Mode
0: Slave Mode
SDODIS
ADCDAT serial data pin disable
0: ADCDAT pin enabled
1: ADCDAT pin off (high impedance)
Table 14 Audio Data Format Control
Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual
word length is 24 bits.
To prevent any communication problems on the Audio Interface, the interface is disabled (ADCDAT
tristated and floating) when the WM8737L starts up. Once the Audio Interface and sample rates have
been programmed, the audio interface can be activated under software control by setting the AI bit
(see “Power Management” section).
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MASTER CLOCK AND AUDIO SAMPLE RATES
The master clock (MCLK) is used to operate the digital filters and the noise shaping circuits. The
WM8737L supports a wide range of master clock frequencies, and can generate many commonly
used audio sample rates directly from the master clock.
There are two clocking modes:
•
•
‘Normal’ mode supports master clocks of 128fs, 192fs, 256fs, 384fs, and their multiples
USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in
systems with a USB interface, and eliminates the need for an external PLL to generate
another clock frequency for the audio ADC.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8 (08h)
6
0
CLKDIV2
0
0
Master Clock Divide by 2
1: MCLK is divided by 2
0: MCLK is not divided
Clocking Mode Select
1: USB Mode
Clocking and
Sample Rate
Control
USB
0: ‘Normal’ Mode
5:1
7
SR[4:0]
0000
0
Sample Rate Control
Clock Ratio Autodetect
(Slave Mode Only)
0: Autodetect Off
AUTO
DETECT
1: Autodetect On
Table 15 Clocking and Sample Rate Control
The clocking of the WM8737L is controlled using the CLKDIV2, USB, and SR control bits. Setting the
CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode.
Each combination of the SR4 to SR0 control bits selects one sample rate (see next page). The digital
filter chacteristics are automatically adjusted to suit the MCLK and sample rate selected (see Digital
Filter Characteristics).
Since all sample rates are generated by dividing MCLK, their accuracy depends on the accuracy of
MCLK. If MCLK changes, the sample rates change proportionately. Note that some sample rates
(e.g. 44.1kHz in USB mode) are approximated, i.e. they differ from their target value by a very small
amount. This is not audible, as the maximum deviation is only 0.27% (8.0214kHz instead of 8kHz in
USB mode - for comparison, a half-tone step corresponds to a 5.9% change in pitch).
In slave mode, it is possible to autodetect the audio clock rate ratio, instead of programming it. The
WM8737L can autodetect the following clock ratios:
•
•
CLKDIV2 = 0: MCLK = 128fs, 192fs, 256fs, or 384fs subject to MCLK < 40MHz
CLKDIV2 = 1: MCLK = 256fs, 384fs, 512fs, 768fs, 1024fs, 1536fs, subject to MCLK <
40MHz
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WM8737L
MCLK
MCLK
CLKDIV2=1
ADC SAMPLE RATE
USB
SR [4:0]
FILTER
TYPE
CLKDIV2=0
Normal Clock Mode
12.288MHz
24.576MHz
8 kHz (MCLK/1536)
12 kHz (MCLK/1024)
16 kHz (MCLK/768)
24 kHz (MCLK/512)
32 kHz (MCLK/384)
48 kHz (MCLK/256)
96 kHz (MCLK/128)
8.0182 kHz (MCLK/1408)
11.025 kHz (MCLK/1024)
22.05 kHz (MCLK/512)
44.1 kHz (MCLK/256)
88.2 kHz (MCLK/128)
8 kHz (MCLK/2304)
12 kHz (MCLK/1536)
16 kHz (MCLK/1152)
24 kHz (MCLK/768)
32 kHz (MCLK/576)
48 kHz (MCLK/384)
96 kHz (MCLK/192)
8.0182 kHz (MCLK/2112)
11.025 kHz (MCLK/1536)
22.05 kHz (MCLK/768)
44.1 kHz (MCLK/384)
88.2 kHz (MCLK/192)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00100
01000
01010
11100
01100
00000
01110
10100
11000
11010
10000
11110
00101
01001
01011
11101
01101
00001
01111
10101
11001
11011
10001
11111
A
A
A
A
A
A
B
A
A
A
A
B
A
A
A
A
A
A
B
A
A
A
A
B
11.2896MHz
18.432MHz
22.5792MHz
36.864MHz
16.9344MHz
33.8688MHz
24.000MHz
USB Mode
12.000MHz
8 kHz (MCLK/1500)
11.0259 kHz (MCLK/1088)
12 kHz (MCLK/1000)
16 kHz (MCLK/750)
1
1
1
1
1
1
1
1
1
1
1
00100
11001
01000
01010
11011
11100
01100
10001
00000
11111
01110
C
A
C
C
A
C
C
A
C
B
D
22.0588 kHz (MCLK/544)
24 kHz (MCLK/500)
32 kHz (MCLK/375)
44.118 kHz (MCLK/272)
48 kHz (MCLK/250)
88.235 kHz (MCLK/136)
96 kHz (MCLK/125)
Table 16 Master Clock and Sample Rates
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Preliminary Technical Data
CONTROL INTERFACE
SELECTION OF CONTROL MODE
The WM8737L is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each
control register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The
MODE pin selects the interface format.
MODE
Low
INTERFACE FORMAT
2 wire
3 wire
High
Table 17 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB latches in a complete control word consisting of the last 16 bits.
latch
CSB
SCLK
SDIN
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
control register address
control register data bits
Figure 15 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8737L supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device can be identified by one of two 7-bit address (this is not the same as
the 7-bit address of each register in the WM8737L).
The WM8737L interface can be written to only and cannot be read back. The controller indicates the
start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates
that a device address and data will follow. All devices on the 2-wire bus respond to the start condition
and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device
address received matches the address of the WM8737L and the R/W bit is ‘0’, indicating a write,
then the WM8737L responds by pulling SDIN low on the next clock pulse (ACK). If the address is not
recognised or the R/W bit is ‘1’, the WM8737L returns to the idle condition and wait for a new start
condition and valid address.
Once the WM8737L has acknowledged a correct address, the controller sends the first byte of
control data (B15 to B8, i.e. the WM8737L register address plus the first bit of register data). The
WM8737L then acknowledges the first data byte by pulling SDIN low for one clock pulse. The
controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register
data), and the WM8737L acknowledges again by pulling SDIN low.
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8737L returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
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WM8737L
Figure 16 2-Wire Serial Control Interface
The WM8737L has two possible device addresses, which can be selected using the CSB pin.
CSB STATE
Low or Unconnected
High
DEVICE ADDRESS
0011010
0011011
Table 18 2-Wire MPU Interface Address Selection
POWER SUPPLIES
The WM8737L can use up to four separate power supplies:
•
AVDD/AGND: Analogue supply, powers all analogue functions except the microphone pre-amp
and MICBIAS. AVDD can range from 1.8V to 3.6V and has the most significant impact on
overall power consumption. A large AVDD improves audio quality by increasing the maximum
input signal range and thus SNR.
•
•
•
MVDD: Supply pin for microphone pre-amp and MICBIAS only. This separate pin makes it
possible to generate MICBIAS voltages larger than AVDD up to a maximum of 3.6V. If this is
not necessary, MVDD should also be tied to AVDD.
DCVDD: Digital core supply, powers all digital functions except the audio and control interface
pins. DCVDD can range from 1.42V to 3.6V, and has no effect on audio quality. The return
path for DCVDD is DGND, which is shared with DBVDD.
DBVDD: Digital buffer supply, powers the audio and control interface pins. This makes it
possible to run the digital core at very low voltages, saving power, while interfacing to other
digital devices using a higher voltage. DBVDD draws much less power than DCVDD, and has
no effect on audio quality. The return path for DBVDD is DGND, which is shared with DCVDD.
It is possible to use the same supply voltage on all three. However, digital and analogue supplies
should be routed and decoupled separately to keep digital switching noise out of the analogue signal
paths.
POWER MANAGEMENT
The WM8737L has a power management register that allows users to select which functions are
active. For minimum power consumption, unused functions should be disabled. To avoid any pop or
click noise.
When the WM8737L is not in use, it can be put into either one of two standby modes or OFF mode.
OFF mode is achieved by writing zeros to all bits in the power management register and gives lowest
power consumption, but wake-up may take several seconds if the VMID decoupling capacitor has
discharged, as it must be recharged from the selectable impedance VMID source.
The output impedance of VMID can be changed to allow variable voltage stabilization time after
VMID is powered on. The 300kΩ setting will ensure minimum VMID power consumption but with slow
charging time, while the 2.5kΩ setting will allow a more rapid charging time but with the penalty of
greatly increased VMID power consumption. The default 75kΩ setting is recommended for most
applications.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R10 (0Ah)
3:2
VMIDSEL
00
VMID impedance selection control
00: 75kΩ output
VMID
Impedance
Control
01: 300kΩ output
10: 2.5kΩ output
Table 19 VMID Impedance Selection
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Standby mode 1 is achieved by powering down everything except the VMID source and gives a very
low power sleep mode. Wake-up may require a few milliseconds to ensure that the VREF voltage
has stabilized.
Standby mode 2 is achieved by not powering down VMID and VREF. The WM8737L can awaken
instantly from standby mode 2 because VREF is already stable.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R6 (06h)
8
VMID
0
VMID (necessary for all other functions)
VREF (necessary for all other functions)
Audio Interface
Power
Manageme
nt
7
VREF
AI
0
6
0
5
PGL
0
PGA Left
4
PGR
0
PGA Right
3
ADL
0
ADC Left
2
ADR
0
ADC Right
1:0
4
MICBIAS
LMBE
RMBE
00
0
see “Microphone Bias” section
Mic Boost Left (see “Input Signal Path”)
Mic Boost Right (see “Input Signal Path”)
R2 (02h)
R3 (03h)
4
0
Notes: All control bits are 0=OFF, 1=ON
Table 20 Power Management
REGISTER MAP
REGISTER ADDRESS REMARKS
(BIT 15 – 9)
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
R0 (00h)
R1 (01h)
R2 (02h)
R3 (03h)
R4 (04h)
R5 (05h)
0000000
0000001
Left PGA
LVU
RVU
LINVOL [7:0]
RINVOL [7:0]
Right PGA
0000010 Audio Path L
0000011 Audio Path R
0001011 3D Enhance
0000101 ADC Control
LINSEL
RINSEL
DIV2
MONOMIX
LMICBOOST
RMICBOOST
LMBE
LMZC
RMZC
LPZC
RPZC
LZCTO[1:0]
RZCTO[1:0]
3DE
RMBE
0
3DLC
3DUC
3DDEPTH
POLARITY
HPOR
0
LP
MONOUT
ADC
HPD
R6 (06h)
R7 (07h)
R8 (08h)
0000110 Power Mgmt VMID
VREF
SDODIS
AUTO
DETECT
0
AI
MS
CLK
DIV2
0
PGL
0
PGR
LRP
ADL
ADR
MICBIAS
FORMAT
USB
Mode
MBCTRL[1:0]
0000111 Audio Format
0001000 Clocking
0
0
WL
SR (Sample Rate Selection)
R9 (09h)
0001001 Mic Preamp
Control
0
0
0
0
0
0
RBYPEN LBYPEN
VMIDSEL [1:0]
R10 (0Ah)
0001010 Misc. biases
control
0
0
LINPUT1 RINPUT1
dc BIAS dc BIAS
ENABLE ENABLE
R11 (0Bh)
R12 (0Ch)
R13 (0Dh)
R14 (0Eh)
R15 (0Fh)
0000100
0001100
0001101
0001110
0001111
Noise Gate
ALC1
0
0
0
0
MAXGAIN
0
NGTH (Threshold)
0
NGAT
ALCSEL
Reserved (must write zeros)
ALCL (Target Level)
HLD (Hold Time)
ATK (Attack Time)
ALC2
ALCZCE
ALC3
0
DCY (Decay Time)
Reset
RESET (writing 000000000 to this register resets all registers to their default state)
Table 21 Control Register Map
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WM8737L
DIGITAL FILTER CHARACTERISTICS
The WM8737L has four different types of digital filter characteristics to suit different MCLK and
sample rates (see Master Clock and Audio Sample Rates).
PARAMETER
ADC Filter Type A
Passband
TEST CONDITIONS
MIN
TYP
MAX
0.4535fs
+/- 0.05
UNIT
+/- 0.05dB
-6dB
0
0.5fs
Passband Ripple
Stopband
dB
dB
Hz
0.5465fs
-60
Stopband Attenuation
f > 0.5465fs
-3dB
High Pass Filter Corner
Frequency
3.7
-0.5dB
10.4
21.6
-0.1dB
Table 22 Digital Filter Characteristics
TERMINOLOGY
Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band)
Pass-band Ripple – any variation of the frequency response in the pass-band region
The filter responses are shown on the following page.
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0.02
0.01
0
0
-20
-40
-60
-80
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-100
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 17 Digital Filter Type A Frequency Response
Figure 18 ADC Digital Filter Type A Ripple
0.02
0.01
0
0
-20
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-40
-60
-80
-100
0
0.05
0.1
0.15
0.2
0.25
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 19 Digital Filter Type B Frequency Response
Figure 20 Digital Filter Type B Ripple
0.02
0.01
0
0
-20
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-40
-60
-80
-100
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 21 Digital Filter Type C Frequency Response
Figure 22 Digital Filter Type C Ripple
0.02
0.01
0
0
-20
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-40
-60
-80
-100
0
0.05
0.1
0.15
0.2
0.25
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 23 Digital Filter Type D Frequency Response
Figure 24 Digital Filter Type D Ripple
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WM8737L
APPLICATIONS INFORMATION
LINE INPUT CONFIGURATION
In order to avoid clipping, the user must ensure that the input signal does not exceed AVDD. This
may require a potential divider circuit in some applications. It is also recommended to remove RF
interference picked up on any cables using a simple first-order RC filter, as high-frequency
components in the input signal may otherwise cause aliasing distortion in the audio band. This filter
must not have high output impedance at audio frequencies (e.g. use a LC filter) if PGA gain errors
are to be minimised when bypassing the microphone preamplifier.
When using ac signals with no dc bias they should be coupled to the WM8737L signal inputs through
a DC blocking capacitor, e.g. 470nF or 1µF when using the microphone preamplifier, and at least
10µF if directly driving the PGA (bigger capacitance may be required at higher gains due to the low
PGA input impedance at high gain).
MICROPHONE INPUT CONFIGURATION
MICBIAS
R1
680 Ohm
FROM
MICROPHONE
LINPUT1/2/3
RINPUT1/2/3
C2
1uF
AGND
R2
47KOhm
C1
220pF
AGND
AGND
Figure 25 Recommended Circuit for Microphone Input
For interfacing to a microphone, the ALC function should be enabled and the microphone boost
switched on. Microphones held close to a speaker’s mouth would normally use a lower boost setting
such as 13dB, while tabletop or room microphones would need a higher boost, for example 28dB.
The recommended application circuit is shown above. R1 and R2 form part of the biasing network
(refer to Microphone Bias section). R1 connected to MICBIAS is necessary only for electret type
microphones that require a voltage bias. R2 should always be present to prevent the microphone
input from charging to a high voltage which may damage the microphone on connection. R1 and R2
should be large so as not to attenuate the signal from the microphone, which can have source
impedance greater than 2kΩ. C1 together with the source impedance of the microphone and the
WM8737L input impedance forms an RF filter. C2 is a dc blocking capacitor to allow the microphone
to be biased at a different dc voltage to the MICIN signal.
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WM8737L
Preliminary Technical Data
RECOMMENDED EXTERNAL COMPONENTS
Notes:
1. C1-18 should be fitted as close to WM8737 as possible.
2. AGND and DGND should be connected as close to WM8737 as possible
Figure 26 External Components Diagram
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1
C2
100nF
10µF
100nF
10µF
100nF
10µF
100nF
10µF
100nF
10µF
100nF
10µF
100nF
10µF
1µF
Decoupling for AVDD
Reservoir capacitor for AVDD
Decoupling for MVDD
C3
C4
Reservoir capacitor for MVDD
Decoupling for DCVDD
C5
C6
Reservoir capacitor for DCVDD
Decoupling for DBVDD
C7
C8
Reservoir capacitor for DBVDD
Decoupling for VMID
C9
C10
C11
C12
C9
Reservoir capacitor for VMID
Decoupling for MICBIAS
Reservoir capacitor for MICBIAS
Decoupling for VREF
C10
C11
C12
Reservoir capacitor for VREF
RACIN to RACOUT coupling capacitor
LACIN to LACOUT coupling capacitor
1µF
Table 23 External Components Descriptions
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Preliminary Technical Data
WM8737L
PACKAGE DIMENSIONS
FL: 32 PIN QFN PLASTIC PACKAGE 5
X
5
X
0.9 mm BODY, 0.50 mm LEAD PITCH
DM030.C
SEE DETAIL A
D
CORNER
TIE BAR
D2
B
D2/2
5
25
32
L
1
24
INDEX AREA
(D/2 X E/2)
E2/2
A
E2
E
SEE DETAIL B
17
8
aaa
C
2 X
16 15
9
b
aaa
C
2 X
B
e
TOP VIEW
DETAIL A
ccc
C
(A3)
1
A
CORNER
TIE BAR
0.08
C
1
32x b
C A B
5
M
A1
bbb
C
SEATING PLANE
DETAIL B
EXPOSED
CENTRE
PAD
1
L1
Symbols
Dimensions (mm)
MIN
0.85
0
NOM
0.90
0.02
MAX
1.00
0.05
NOTE
A
A1
A3
b
D
D2
E
E2
e
L
L1
R
K
0.2 REF
0.23
5.00
0.18
4.90
3.2
0.30
5.10
3.4
5.10
3.4
1
2
2
3.3
5.00
4.90
3.2
3.3
0.5 BSC
0.4
0.35
0.45
0.1
1
b(min)/2
0.20
Tolerances of Form and Position
aaa
bbb
ccc
0.15
0.10
0.10
JEDEC, MO-220, VARIATION VKKD-2
REF:
NOTES:
1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM
PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF
ETCHING OF LEADFRAME.
2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2:
D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION
3. ALL DIMENSIONS ARE IN MILLIMETRES
4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY
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WM8737L
Preliminary Technical Data
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical
components in life support devices or systems without the express written approval of an officer of the company. Life
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual
property right of WM covering or relating to any combination, machine, or process in which such products or services might
be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s
approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and
deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
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相关型号：
WM8737CLGEFL/R
Consumer Circuit, CMOS, PQCC32, 5 X 5 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, MO-220VHHD-5, QFN-32
CIRRUS
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