WM8751L [WOLFSON]
STEREO DAC FOR PORTABLE AUDIO APPLICATIONS; 立体声DAC便携式音频应用
| 型号： | WM8751L |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | STEREO DAC FOR PORTABLE AUDIO APPLICATIONS |
| 文件： | 总41页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8751L
STEREO DAC FOR PORTABLE AUDIO APPLICATIONS
DESCRIPTION
FEATURES
•
•
•
DAC SNR 98dB, THD -95dB (‘A’ weighted @ 48kHz, 3.3V)
On-chip 400mW BTL Speaker Driver (mono)
On-chip Headphone Driver
The WM8751L is a low power, high qualitystereo DAC with
integrated headphone and loudspeaker amplifiers, designed
to reduce external component requirements in portable digital
audio applications.
°
°
40mW output power on 16Ω / 3.3V
THD –80dB at 20mW, SNR 90dB with 16Ω load
The on-chip headphone amplifiers can deliver 40mW into a
16Ω load. Advanced on-chip digital signal processing
performs bass and treble tone control.
•
•
•
•
•
Stereo and Mono Line-in mix into DAC output
SeparatelyMixed Stereo and Mono Outputs
Digital Tone Control and Bass Boost
Low Power
The WM8751L can operate as a master or a slave, with
various master clock frequencies including 12 or 24MHz for
USB devices or standard 256fs rates like 12.288MHz and
24.576MHz. Different audio sample rates such as 96kHz,
48kHz, 44.1kHz are generated directlyfrom the master clock
without the need for an external PLL.
Low SupplyVoltages
°
°
°
Analogue 1.8V to 3.6V
Digital core: 1.42V to 3.6V
Digital I/O: 1.42V to 3.6V
•
•
256fs / 384fs or USB master clock rates: 12MHz, 24MHz
Audio sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1,
48, 88.2, 96kHz generated internallyfrom master clock
32-pin QFN package, 5x5x0.9mm size, 0.5mm lead pitch
The WM8751L operates on supplyvoltages from 1.8V up to
3.6V, although the digital core can operate on a separate
supplydown to 1.42V, saving power. Different sections of the
chip can also be powered down under software control.
•
APPLICATIONS
The WM8751L is supplied in a verysmall and thin 5x5mm
QFN package, ideal for use in hand-held and portable
systems.
•
•
•
Digital Audio Player
MP3 Phone
Minidisc Player
BLOCK DIAGRAM
DBVDD DCVDD
DGND
HPGND
HPVDD
MONOOUT
-1
M
U
X
OUT3
DIFF. IN
LI2LO
W
WM8751L
ROUT1
VREF
LEFT
MIXER
LD2LO
RD2LO
LD2MO
RD2MO
LD2RO
RD2RO
LOUT1
CSB
SDIN
LOUT1VOL
MONOVOL
MI2LO
LI2MO
DAC
DAC
CONTROL
INTERFACE
MONO
MIXER
DIGITAL
FILTERS
SCLK
MODE
MONOOUT
TONE
CONTROL
RI2MO
MI2RO
BCLK
DACLRC
DACDAT
DIGITAL
AUDIO
INTERFACE
RIGHT
MIXER
ROUT1
LOUT2
ROUT1VOL
LOUT2VOL
RI2RO
MCLK
Loudspeaker
L - (-R)
= L+R
VREF
ROUT2
INV
-1
50K
50K
ROUT2
ROUT2VOL
HPDETECT
WOLFSON MICROELECTRONICS PLC
www.wolfsonmicro.com
Product Preview, May2003, Rev 1.42
Copyright 2003 Wolfson Microelectronics Ltd.
WM8751L
Product Preview
PIN CONFIGURATION
ORDERING INFORMATION
ORDER CODE
TEMPERATURE
RANGE
PACKAGE
WM8751LEFL
-25°C to +85°C
32-pin QFN
(5x5x0.9mm)
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
16
15
14
LOUT2
ROUT2
HPGND
MONOIN-
MONOIN+
LINEINR
13 LOUT1
LINEINL
MODE
ROUT1
OUT3
12
11
CSB
10 MONOOUT
SDIN
SCLK 32
9
AGND2
1
2
3
4
5
6
7
8
Product Preview Rev 1.42 May2003
w
2
Product Preview
WM8751L
PIN DESCRIPTION
PIN #
NAME
MCLK
TYPE
DESCRIPTION
1
2
3
4
5
6
7
8
9
Digital Input
Master Clock
DCVDD
DBVDD
DGND
BCLK
SupplyDigital Core Supply
SupplyDigital Buffer (I/O) Supply
SupplyDigital Ground (return path for both DCVDD and DBVDD)
Digital Input / Output
Audio Interface Bit Clock
DAC Digital Audio Data
DACDAT
DACLRC
NC
Digital Input
Digital Input / Output
No Connect
Audio Interface Left / Right Clock
No Internal Connection
AGND2
SuppclyoInnntercnteadllyto AGND. Leave this pin floating or connect to
AGND.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
MONOOUT
OUT3
Analogue Output
Mono Output
Analogue Output
Analogue Output
Analogue Output
Output 3 (can be used as Headphone Pseudo Ground)
Right Output 1 (Line or Headphone)
Left Output 1 (Line or Headphone)
ROUT1
LOUT1
HPGND
ROUT2
LOUT2
HPVDD
AVDD
SufpoprlAySnuaplopglyue Output Drivers (LOUT1/2, ROUT1/2)
Analogue Output
Analogue Output
Right Output 1 (Line or Headphone or Speaker)
Left Output 1 (Line or Headphone or Speaker)
SufpoprlAySnuaplopglyue Output Drivers (LOUT1/2, ROUT1/2, MONOUT)
SupplyAnalogue Supply
AGND
SupplyAnalogue Ground (return path for AVDD)
VREF
Analogue Output
Reference Voltage Decoupling Capacitor
Midrail Voltage Decoupling Capacitor
No Internal Connection
VMID
Analogue Output
No Connect
NC
HPDETECT
NC
Logic Input
Headphone / Speaker switch (referred to AVDD)
No Internal Connection
No Connect
MONOIN-
MONOIN+
LINEINR
LINEINL
MODE
CSB
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Digital Input
Negative end of MONOIN+, for differential mono signals
Analogue Line-in to mixers (mono channel)
Analogue Line-in to mixers (right channel)
Analogue Line-in to mixers (left channel)
Control Interface Selection
Digital Input
Chip Select / Device Address Selection
Control Interface Data Input / 2-wire Acknowledge output
Control Interface Clock Input
SDIN
Digital Input/Output
Digital Input
SCLK
Product Preview Rev 1.42 May2003
w
3
WM8751L
Product Preview
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device maybe caused bycontinuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore genericallysusceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
MIN
-0.3V
MAX
+3.63V
Supplyvoltages
Voltage range digital inputs
Voltage range analogue inputs
DGND -0.3V
AGND -0.3V
-25°C
DBVDD +0.3V
AVDD +0.3V
+85°C
Operating temperature range, TA
Storage temperature prior to soldering
Storage temperature after soldering
Package bodytemperature (soldering 10 seconds)
Package bodytemperature (soldering 2 minutes)
Notes
30°C max / 85% RH max
-65°C
+150°C
+260°C
+183°C
1. Analogue and digital grounds must always be within 0.3V of each other.
2. All digital and analogue supplies are completelyindependent from each other.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
DCVDD
TEST CONDITIONS
MIN
1.42
1.8
TYP
2.0
2.0
2.0
0
MAX
3.6
UNIT
Digital supplyrange (Core)
Digital supplyrange (Buffer)
Analogue supplies range
Ground
V
V
V
V
DBVDD
3.6
AVDD, HPVDD
DGND, AGND, HPGND
1.8
3.6
Product Preview Rev 1.42 May2003
w
4
Product Preview
WM8751L
ELECTRICAL CHARACTERISTICS
Test Conditions
DCVDD = 1.5V, AVDD = HPVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
DAC to Line-Out (LOUT1/2, ROUT1/2, MONOOUT with 10kΩ / 50pF load)
Signal to Noise Ratio
(A-weighted)
SNR
THD
AVDD = 3.3V
AVDD = 1.8V
AVDD = 3.3V
AVDD = 1.8V
1kHz signal
98
95
Total Harmonic Distortion
-95
-90
90
dB
Channel Separation
dB
Analogue Mixer Inputs (LINEINL, LINEINR, MONOIN+)
Full-scale Input Signal Level
VINFS
AVDD = 3.3V
AVDD = 1.8V
AVDD = 3.3V
AVDD = 1.8V
1.0
0.516
95
V rms
dB
Signal to Noise Ratio
Line-in to Line-Out
(A-weighted)
SNR
90
Total Harmonic Distortion
THD
AVDD = 3.3V
AVDD = 1.8V
-92
-92
20
10
10
5
dB
dB
kΩ
Input Resistance
RLINEIN
PGA gain = 0dB
PGA gain = +6dB
PGA gain = 0dB
PGA gain = +6dB
anygain
(signal enters one mixer only)
Input Resistance
(signal enters two mixers)
MONOIN- input resistance
Programmable Gain
RMONOIN-
20
k Ω
dB
dB
dB
-15
+6
+6
Programmable Gain Step Size
Mute Attenuation
Monotonic
3
TBD
Analogue Outputs (LOUT1/2, ROUT1/2, MONOOUT)
0dB Full scale output voltage
AVDD/3.3
Vrms
dB
Programmable Gain
Programmable Gain Steps
Mute attenuation
1kHz signal
-67
80
Monotonic
80
85
90
steps
dB
1kHz, full scale signal
Channel Separation
dB
Headphone Output (LOUT1/2, ROUT1/2 with 16 or 32 Ohm load)
Output Power per channel
Total Harmonic Distortion
PO
Output power is verycloselycorrelated with THD; see below.
THD
HPVDD=1.8V, RL=32Ω
0.013
-78
dB
%
PO=5mW
HPVDD=1.8V, RL=16Ω
PO=5mW
0.013
-78
HPVDD=3.3V, RL=32Ω,
0.01
-80
PO=20mW
HPVDD=3.3V, RL=16Ω,
0.01
-80
PO=20mW
Signal to Noise Ratio
(A-weighted)
SNR
HPVDD = 3.3V
HPVDD = 1.8V
90
dB
90
Product Preview Rev 1.42 May2003
w
5
WM8751L
Product Preview
Test Conditions
DCVDD = 1.5V, AVDD = HPVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Speaker Output (LOUT2/ROUT2 with 8Ω bridge tied load, ROUT2INV=1)
Output Power
PO
HPVDD=3.3V, RL=8Ω
HPVDD=3.0V, RL=8Ω
HPVDD=2.7V, RL=8Ω
HPVDD=3.3V, RL=8Ω
HPVDD=3.0V, RL=8Ω
HPVDD=2.7V, RL=8Ω
400
300
230
75
mW
Signal to Noise Ratio
(A-weighted)
SNR
THD
dB
75
75
Total Harmonic Distortion
Po=150mW, RL=8Ω,
-60
0.1
-50
0.3
dB
%
HPVDD=3.3V
Po=300mW, RL=8Ω
HPVDD=3.3V
Analogue Reference Levels
Midrail Reference Voltage
Buffered Reference Voltage
VREF source current
VREF sink current
VMID
VREF
IVREF
–3%
–3%
AVDD/2
AVDD/2
+3%
+3%
5
V
V
mA
mA
IVREF
5
Digital Input / Output
Input HIGH Level
VIH
VIL
0.7×DBVDD
0.9×DBVDD
V
V
V
V
Input LOW Level
0.3×DBVDD
0.1×DBVDD
Output HIGH Level
VOH
VOL
Output LOW Level
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal.
Normallya THD+N measurement at 60dB below full scale. The measured signal is then corrected byadding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normallymeasured bysending a full scale signal down one channel and measuring the other.
Product Preview Rev 1.42 May2003
w
6
Product Preview
WM8751L
OUTPUT PGA’S LINEARITY
10.000
0.000
Output PGA Gains
-10.000
-20.000
-30.000
-40.000
-50.000
-60.000
-70.000
LOUT1
ROUT1
LOUT2
ROUT2
MONOOUT
40
50
60
70
80
90
100
110
120
130
XXXVOL Register Setting (binary)
2.000
1.750
1.500
1.250
1.000
0.750
0.500
0.250
0.000
Output PGA GainStep Size
LOUT1
ROUT1
LOUT2
ROUT2
MONOOUT
40
50
60
70
80
90
100
110
120
130
XXXVOL Register Setting (binary)
Product Preview Rev 1.42 May2003
w
7
WM8751L
Product Preview
HEADPHONE OUTPUT THD VERSUS POWER (SIMULATION)
0
Headphone Power vs THD+N (32Ohm load)
-20
-40
AVDD=1.8V
AVDD=1.8V, capless
AVDD=3.3V
-60
AVDD=3.3V, capless
-80
-100
0
5
10
15
20
25
30
Pow er (mW)
0
-20
Headphone Power vs THD+N (16Ohm load)
AVDD=1.8V
-40
AVDD=1.8V, capless
AVDD=3.3V
-60
AVDD=3.3V, capless
-80
-100
0
10
20
30
40
50
60
Pow er (mW)
Product Preview Rev 1.42 May2003
w
8
Product Preview
WM8751L
SPEAKER OUTPUT THD VERSUS POWER (SIMULATION)
-10
-20
-30
-40
-50
AVDD=1.8V
AVDD=2.5V
AVDD=3.3V
Speaker Power vs THD+N (8Ohm BTL load)
-60
-70
0
100
200
300
400
500
Pow er (mW)
10
8
Speaker Power vs THD+N (8 Ohm BTL load)
6
AVDD=1.8V
AVDD=2.5V
AVDD=3.3V
4
2
0
0
100
200
300
400
500
Power (mW)
Product Preview Rev 1.42 May2003
w
9
WM8751L
Product Preview
POWER CONSUMPTION
The power consumption of the WM8751L depends on the following factors.
•
Supplyvoltages: Reducing the supplyvoltages also reduces supplycurrents, and therefore results in significant power
savings.
•
Operating mode: Power consumption is lower in mono modes than in stereo, as one DAC is switched OFF. Unused
analogue outputs should be switched off.
Control Register
R25
R26 (1Ah)
R24 R23 R38
Other settings
Clocks stopped
AVDD
DCVDD
DBVDD
HPVDD
Tot. Power
Bit
V
I (mA)
V
I (mA)
V
I (mA)
V
I (mA)
(mW)
<0.01
<0.01
<0.01
<0.02
<0.02
<0.02
40
20
9
34
19
OFF
00
0
0
0
0
0
0
0
0
0
0
11
01
00
11
01
00
11
01
00
11
01
00
11
01
00
0
0
0
3.3 TBD 3.3 TBD 3.3 TBD 3.3 TBD
2.5 TBD 2.5 TBD 2.5 TBD 2.5 TBD
1.8 TBD 1.5 TBD 1.5 TBD 1.8 TBD
3.3 TBD 3.3 TBD 3.3 TBD 3.3 TBD
2.5 TBD 2.5 TBD 2.5 TBD 2.5 TBD
1.8 TBD 1.5 TBD 1.5 TBD 1.8 TBD
3.3 TBD 3.3 TBD 3.3 TBD 3.3 TBD
2.5 TBD 2.5 TBD 2.5 TBD 2.5 TBD
1.8 TBD 1.5 TBD 1.5 TBD 1.8 TBD
3.3 TBD 3.3 TBD 3.3 TBD 3.3 TBD
2.5 TBD 2.5 TBD 2.5 TBD 2.5 TBD
1.8 TBD 1.5 TBD 1.5 TBD 1.8 TBD
3.3 TBD 3.3 TBD 3.3 TBD 3.3 TBD
2.5 TBD 2.5 TBD 2.5 TBD 2.5 TBD
1.8 TBD 1.5 TBD 1.5 TBD 1.8 TBD
3.3 TBD 3.3 TBD 3.3 TBD 3.3 TBD
2.5 TBD 2.5 TBD 2.5 TBD 2.5 TBD
1.8 TBD 1.5 TBD 1.5 TBD 1.8 TBD
3.3 TBD 3.3 TBD 3.3 TBD 3.3 TBD
2.5 TBD 2.5 TBD 2.5 TBD 2.5 TBD
1.8 TBD 1.5 TBD 1.5 TBD 1.8 TBD
3.3 TBD 3.3 TBD 3.3 TBD 3.3 TBD
2.5 TBD 2.5 TBD 2.5 TBD 2.5 TBD
1.8 TBD 1.5 TBD 1.5 TBD 1.8 TBD
3.3 TBD 3.3 TBD 3.3 TBD 3.3 TBD
2.5 TBD 2.5 TBD 2.5 TBD 2.5 TBD
1.8 TBD 1.5 TBD 1.5 TBD 1.8 TBD
3.3 TBD 3.3 TBD 3.3 TBD 3.3 TBD
2.5 TBD 2.5 TBD 2.5 TBD 2.5 TBD
1.8 TBD 1.5 TBD 1.5 TBD 1.8 TBD
Low-power standby(LPS)
using 500 KOhm VMID string
10
01
01
01
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Playback to Line-out
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
Playback to Line-out
(64x oversampling mode)
1
1
8.5
40
20
9
Playback
to 16 Ohm headphone
using caps on HPOUTL/R
Play back
to 16 Ohm headphone
capless mode using OUT3
Playback
01
1
1
1
1
1
0
0
0
1
0
11
0
R24, OUT3SW=00
R24, ROUT2INV=1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
01
00
11
01
00
11
01
00
11
01
00
11
01
00
0
0
0
0
0
0
0
0
0
0
0
1
1
1
01
01
01
01
1
1
1
1
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
0
0
0
to 8 Ohm BTL speaker
Headphone Amp
line-in to 16 Ohm h/phone
0
0
1
Speaker Amp
line-in to 8 Ohm speaker
R24, ROUT2INV=1
Phone Call
diff. mono line-in to h/phone,
diff. mono line-out to TX
0
1
Table 1 Supply Current Consumption (Target)
Notes:
1. TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 12.288 MHz (256fs), 24-bit data
2. All figures are quiescent, with no signal.
3. The power dissipated in the headphone itself is not included in the above table.
Product Preview Rev 1.42 May2003
w
10
Product Preview
WM8751L
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
tMCLKL
tMCLKH
tMCLKY
16
16
27
ns
ns
ns
AUDIO INTERFACE TIMING – MASTER MODE
BCLK
(Output)
tDL
DACLRC
(Output)
tDST
tDHT
DACDAT
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
DACLRC propagation delayfrom BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
tDL
10
ns
ns
ns
tDST
tDHT
10
10
AUDIO INTERFACE TIMING – SLAVE MODE
tBCH
tBCL
BCLK
DACLRC
DACDAT
tBCY
tLRSU
tDS
tLRH
Figure 3 Digital Audio Data Timing – Slave Mode (see Control Interface)
Product Preview Rev 1.42 May2003
11
w
WM8751L
Product Preview
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
50
20
20
10
10
10
ns
ns
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
DACLRC setup time to BCLK rising edge
DACLRC hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
CONTROL INTERFACE TIMING – 3-WIRE MODE
tCSL
tCSH
CSB
tCSS
tSCY
tSCS
tSCH
tSCL
SCLK
SDIN
LSB
tDSU
tDHO
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
tSCS
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
tps
500
200
80
80
40
40
40
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes that will be suppressed
5
Product Preview Rev 1.42 May2003
12
w
Product Preview
WM8751L
CONTROL INTERFACE TIMING – 2-WIRE MODE
t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t7
t1
t9
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
400
kHz
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
tps
600
1.3
600
600
100
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
300
300
Setup Time (Stop Condition)
Data Hold Time
600
0
900
5
Pulse width of spikes that will be suppressed
Product Preview Rev 1.42 May2003
13
w
WM8751L
Product Preview
DEVICE DESCRIPTION
INTRODUCTION
The WM8751L is a low power audio DAC offering a combination of high qualityaudio, advanced
features, low power and small size. These characteristics make it ideal for portable digital audio
applications such as portable music players and smartphones.
The device has a configurable digital audio interface where digital audio data is fed to the internal
digital filters and then the DAC. The interface supports a number of audio data formats including I2S,
DSP Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), Left
Justified and Right Justified formats, and can operate in master or slave modes.
The on-chip digital filters perform tone control and digital volume control according to the user
setting, and convert the audio data into oversampled bitstreams, which are passed to the left and
right channel DACs. A multi-bit, low-order Σ∆ DAC architecture with dynamic element matching is
used, delivering optimum performance with low power consumption.
The DAC output signal enters an analogue mixer where analogue input signals can be added to it.
The WM8751L has a total of six analogue output pins, which can be configured as stereo line-outs,
mono line-outs, differential mono line-outs, stereo headphone outputs or differential mono (BTL)
speaker outputs.
The WM8751L master clock can be either an industrystandard 256/384 f clock or a 12MHz/24MHz
s
USB clock. Sample rates of 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 32kHz, 44.1kHz, 48kHz,
88.2kHz and 96kHz can be generated directlyfrom the master clock, without an external PLL. The
digital filters are optimised for each sample rate.
To allow full software control over all its features, the WM8751L offers a choice of 2 or 3 wire MPU
control interface. It is fullycompatible and an ideal partner for a wide range of industrystandard
microprocessors, controllers and DSPs.
The design of the WM8751L has given much attention to power consumption without compromising
performance. It operates at verylow voltages, and includes the abilityto power off parts of the
circuitryunder software control, including standbyand power off modes.
Product Preview Rev 1.42 May2003
14
w
Product Preview
WM8751L
SIGNAL PATH
The WM8751L signal paths consists of digital filters, DACs, analogue mixers and output drivers.
Each circuit block can be enabled or disabled separatelyusing the control bits in register 26 (see
“Power Management”). Thus it is possible to utilise the analogue mixing and amplification provided
bythe WM8751L, irrespective of whether the DACs are running or not.
The WM8751L receives digital input data on the DACDAT pin. The digital filter block processes the
data to provide the following functions:
•
•
•
•
Digital volume control
Tone control and Bass Boost
Digital Mono Mix
Sigma-Delta Modulation
Two high performance, sigma-delta audio DACs convert the digital data into two analogue signals
(left and right). These can then be mixed with analogue signals from the LINEINL, LINEINR and
MONOIN pins, and the mix is fed to the output drivers, LOUT1/ROUT1, LOUT2/ROUT2, and
MONOOUT.
•
•
•
•
LOUT1/ROUT1: can drive 16Ω or 32Ω stereo headphones or stereo line output.
LOUT2/ROUT2: can drive an 8Ω mono speaker, stereo headphones or a stereo line-out.
MONOOUT: line output designed to drive a 10kΩ load.
OUT3: multi-function output, maybe used for capacitor-less headphone drive, differential
mono-out, line-out or 32Ω earpiece driver.
Product Preview Rev 1.42 May2003
w
15
WM8751L
Product Preview
DIGITAL VOLUME CONTROL
The WM8751L has on-chip digital attenuation from –127dB to 0dB in 0.5dB steps, allowing the user
to adjust the volume of each channel separately. The level of attenuation for an eight-bit code X is
given by:
-0.5 × (255 – X) dB for 1 ≤ X ≤ 255;
MUTE for X = 0
The LDVU and RDVU control bits control the loading of digital volume control data. When LDVU or
RDVU are set to 0, the LDACVOL or RDACVOL control data is loaded into an intermediate register,
but the actual gain does not change. Both left and right gain settings are updated simultaneously
when either LDVU or RDVU are set to 1.
REGISTER
ADDRESS
BIT
7:0
LABEL
DEFAULT
DESCRIPTION
R10 (0Ah)
LDACVOL[7:0] 11111111 Left DAC Digital Volume Control
Left Channel
Digital Volume
( 0dB )
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
8
LDVU
0
Left DAC Volume Update
0 = Store LDACVOL in intermediate latch
(no gain change)
1 = Update left and right channel gains
(left = LDACVOL, right = intermediate
latch)
R11 (0Bh)
7:0
8
RDACVOL[7:0] 11111111 Right DAC Digital Volume Control
Right Channel
Digital Volume
( 0dB )
0
similar to LDACVOL
RDVU
Right DAC Volume Update
0 = Store RDACVOL in intermediate latch
(no gain change)
1 = Update left and right channel gains
(left = intermediate latch, right =
RDACVOL)
Table 2 Digital Volume Control
Product Preview Rev 1.42 May2003
w
16
Product Preview
WM8751L
TONE CONTROL
The WM8751L provides separate controls for bass and treble with programmable gains and filter
characteristics. This function operates on digital audio data before it is passed to the audio DACs.
Bass control can take two different forms:
•
Linear bass control: bass signals are amplified or attenuated bya user programmable
gain. This is independent of signal volume, and veryhigh bass gains on loud signals
maylead to signal clipping.
•
Adaptive bass boost: The bass volume is amplified bya variable gain. When the bass
volume is low, it is boosted more than when the bass volume is high. This method is
recommended because it prevents clipping, and usuallysounds more pleasant to the
human ear.
Treble control applies a user programmable gain, without anyadaptive boost function.
REGISTER
ADDRESS
BIT
LABEL
BB
DEFAULT
DESCRIPTION
R12 (0Ch)
7
0
0
Bass Mode
Bass Control
0 = Linear bass control
1 = Adaptive bass boost
6
BC
Bass Filter Characteristic
0 = Low Cutoff (130 Hz at 48kHz sampling)
1 = High Cutoff (200 Hz at 48kHz sampling)
Bass Intensity
3:0
BASS
1111 (OFF)
Code
0000
0001
0010
…
BB=0
BB=1
15 (max)
14
+9dB
+9dB
+7.5dB
(1.5dB steps)
0dB
13
…
0111
…
8
(1.5dB steps)
…
1011-1101 -6dB
4-2
1110
1111
-6dB
1 (min)
Bypass (OFF)
R13 (0Dh)
6
TC
0
Treble Filter Characteristic
Treble Control
0 = High Cutoff (8kHz at 48kHz sampling)
1 = Low Cutoff (4kHz at 48kHz sampling)
Treble Intensity
3:0
TRBL
1111
(Disabled)
0000 or 0001 = +9dB
0010 = +7.5dB
… (1.5dB steps)
1011 to 1110 = -6dB
1111 = Disable
Table 3 Tone Control
Note:
1. All cut-off frequencies change proportionallywith the DAC sample rate.
Product Preview Rev 1.42 May2003
17
w
WM8751L
Product Preview
DIGITAL TO ANALOGUE CONVERTER (DAC)
Treble and linear bass enhancement mayproduce signals that exceed full-scale. In order to avoid
limiting under these conditions, it is recommended to set the DAT bit to attenuate the digital input
signal by6dB. The gain at the outputs should be increased by6dB to compensate for the
attenuation. Cut-onlytone adjustment and adaptive bass boost cannot produce signals above full-
scale and therefore do not require the DAT bit to be set.
After passing through the tone control filters, digital ‘de-emphasis’ can be applied to the audio data if
necessary(e.g. when the data comes from a CD with pre-emphasis used in the recording). De-
emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz.
The WM8751L also has a Soft Mute function, which graduallyattenuates the volume of the digital
signal to zero. This function is enabled bydefault. To playback an audio signal, the WM8751L must
first be unmuted bysetting the DACMU bit to zero.
REGISTER
ADDRESS
BIT
LABEL
DAT
DEFAULT
DESCRIPTION
R5 (05h)
DAC Control
7
0
DAC 6dB attenuate enable
0 = disabled (0dB)
1 = -6dB enabled
3
DACMU
1
DAC Digital Soft Mute
1 = mute
0 = no mute (signal active)
De-emphasis Control
11 = 48kHz sample rate
10 = 44.1kHz sample rate
01 = 32kHz sample rate
00 = No De-emphasis
2:1
DEEMPH
00
Table 4 DAC Control
The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital
interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to
high qualityanalogue audio signals. The multi-bit DAC architecture reduces high frequencynoise and
sensitivityto clock jitter. It also uses a Dynamic Element Matching technique for high linearityand
low distortion.
In normal operation, the left and right channel digital audio data are converted to analogue in two
separate DACs. However, it is also possible to disable one channel, so that the same signal (left or
right) appears on both analogue output channels. Additionally, there is a mono-mix mode where the
two audio channels are mixed together digitallyand then converted to analogue using onlyone DAC,
while the other DAC is switched off. The mono-mix signal can be selected to appear on both
analogue output channels (see Analogue Outputs).
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R23 (17h)
5:4
DMONOMIX[1:0]
00
DAC mono mix
Additional (1)
00: stereo
01: mono ((L+R)/2) into DACL, ‘0’ into
DACR
10: mono ((L+R)/2) into DACR, ‘0’ into
DACL
11: mono ((L+R)/2) into DACL & DACR
Table 5 DAC Mono Mix Select
Product Preview Rev 1.42 May2003
18
w
Product Preview
WM8751L
LINE INPUTS AND OUTPUT MIXERS
The WM8751L provides the option to mix the DAC output signal with analogue line-in signals from
the LINEINL, LINEINR and MONOIN pins. The level of the mixed-in signals can be controlled with
PGAs (Programmable Gain Amplifiers).
LINEINL, LINEINR, MONOIN+ and MONOIN- are high impedance, low capacitance AC coupled
analogue inputs. Theyare biased internallyto the reference voltage VREF. Whenever these inputs
are muted or the device placed into standbymode, the inputs remain biased to VREF using special
anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when re-activating
the inputs.
REGISTER
ADDRESS
BIT
LABEL
LD2LO
DEFAULT
DESCRIPTION
Left DAC to Left Mixer
R34 (22h)
8
0
0
Left Mixer (1)
0 = Disable (Mute)
1 = Enable Path
7
LI2LO
LINEINL Signal to Left Mixer
0 = Disable (Mute)
1 = Enable Path
6:4
LI2LOVOL
101
LINEINL Signal to Left Mixer Volume
000 = +6dB
(-9dB)
… (3dB steps)
111 = -15dB
R35 (23h)
8
RD2LO
0
0
Right DAC to Left Mixer
0 = Disable (Mute)
1 = Enable Path
Left Mixer (2)
7
MI2LO
MONOIN Signal to Left Mixer
0 = Disable (Mute)
1 = Enable Path
6:4
MI2LOVOL
101
MONOIN Signal to Left Mixer Volume
000 = +6dB
(-9dB)
… (3dB steps)
111 = -15dB
Table 6 Left Output Mixer Control
Product Preview Rev 1.42 May2003
w
19
WM8751L
Product Preview
REGISTER
ADDRESS
BIT
LABEL
LD2RO
DEFAULT
DESCRIPTION
Left DAC to Right Mixer
R36 (24h)
8
0
0
Right Mixer (1)
0 = Disable (Mute)
1 = Enable Path
7
MI2RO
MONOIN Signal to Right Mixer
0 = Disable (Mute)
1 = Enable Path
6:4
MI2ROVOL
101
MONOIN Signal to Right Mixer Volume
000 = +6dB
(-9dB)
… (3dB steps)
111 = -15dB
R37 (25h)
8
RD2RO
0
0
Right DAC to Right Mixer
0 = Disable (Mute)
1 = Enable Path
Right Mixer (2)
7
RI2RO
LINEINR Signal to Right Mixer
0 = Disable (Mute)
1 = Enable Path
6:4
RI2ROVOL
101
LINEINR Signal to Right Mixer Volume
000 = +6dB
(-9dB)
… (3dB steps)
111 = -15dB
Table 7 Right Output Mixer Control
REGISTER
ADDRESS
BIT
LABEL
LD2MO
DEFAULT
DESCRIPTION
R38 (26h)
8
0
0
Left DAC to Mono Mixer
0 = Disable (Mute)
1 = Enable Path
Mono Mixer (1)
7
LI2MO
LINEINL Signal to Mono Mixer
0 = Disable (Mute)
1 = Enable Path
6:4
LI2MOVOL
101
LINEINL Signal to Right Mono Volume
000 = 0dB
(-9dB)
… (3dB steps)
111 = -21dB
R39 (27h)
8
RD2MO
0
0
Right DAC to Mono Mixer
0 = Disable (Mute)
1 = Enable Path
Mono Mixer (2)
7
RI2MO
LINEINR Signal to Mono Mixer
0 = Disable (Mute)
1 = Enable Path
6:4
RI2MOVOL
101
LINEINR Signal to Mono Mixer Volume
000 = 0dB
(-9dB)
… (3dB steps)
111 = -21dB
Table 8 Mono Output Mixer Control
Note: The mono mixer has half the gain of the left and right mixers (i.e. 6dB less), to ensure that the
left and right channels can be mixed to mono without clipping.
Product Preview Rev 1.42 May2003
20
w
Product Preview
WM8751L
DIFFERENTIAL MONO LINE-IN
The WM8751L can take either a single-ended or a differential mono signal and mix it into the
LOUT1/2 and ROUT1/2 outputs. In both cases, LINEINL and LINEINR still remain available as stereo
line-in. Differential mono input mode is enabled bysetting the DMEN bit, as shown below.
REGISTER
ADDRESS
BIT
LABEL
DMEN
DEFAULT
DESCRIPTION
R38 (26h)
0
0
Differential mono line-in enable
0 = Single-ended line-in from MONOIN+
1 = Differential line-in
Mono Mixer (1)
Table 9 Differential Mono Line-in Enable
MONO OUT(-)
DEVICE WITH
DIFFERENTIAL
MONO OUTPUT
MONO OUT(+)
DMEN = 1
(ON)
DIFF. IN
LI2LO
LEFT
MIXER
LD2LO
RD2LO
LD2MO
RD2MO
LD2RO
RD2RO
LOUT1
LOUT1VOL
MI2LO
LI2MO
DAC
DAC
MONO
MIXER
MONOOUT
MONOVOL
RI2MO
MI2RO
RIGHT
MIXER
ROUT1
LOUT2
ROUT1VOL
LOUT2VOL
RI2RO
Loudspeaker
L - (-R)
= L+R
W
WM8751L
ROUT2
INV
-1
ROUT2
ROUT2VOL
Figure 6 Differential Mono Line-in Configuration
DEVICE WITH
MONO OUT
SINGLE-ENDED
MONO OUTPUT
DMEN = 0
(OFF)
DIFF. IN
LI2LO
LEFT
MIXER
LD2LO
RD2LO
LD2MO
RD2MO
LD2RO
RD2RO
LOUT1
LOUT1VOL
MONOVOL
MI2LO
LI2MO
DAC
DAC
MONO
MIXER
MONOOUT
RI2MO
MI2RO
RIGHT
MIXER
ROUT1
LOUT2
ROUT1VOL
LOUT2VOL
RI2RO
Loudspeaker
L - (-R)
= L+R
W
WM8751L
ROUT2
INV
-1
ROUT2
ROUT2VOL
Figure 7 Single-ended Mono Line-in Configuration
Product Preview Rev 1.42 May2003
w
21
WM8751L
Product Preview
ANALOGUE OUTPUTS
ENABLING THE OUTPUTS
Each analogue output of the WM8751L can be separatelyenabled or disabled. The analogue mixer
associated with each output is powered on or off along with the output pin. All outputs are disabled by
default. To save power, unused outputs should remain disabled.
Outputs can be enabled at anytime, except when the WM8751L is in OFF mode, as this maycause
pop noise (see Minimising Pop Noise at the Analogue Outputs)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R26 (1Ah)
8
7
5
4
2
LOUT1
0
0
0
0
0
0
LOUT1 Enable
Power
Management
(2)
ROUT1
LOUT2
ROUT2
MONO
OUT3
ROUT1 Enable
LOUT2 Enable
ROUT2 Enable
MONOOUT Enable
OUT3 Enable
1
Note: All “Enable” bits are 1 = ON, 0 = OFF
Table 10 Analogue Output Control
HEADPHONE SWITCH
The HPDETECT pin can be used as a headphone switch control input to automaticallydisable the
speaker output and enable the headphone output e.g. when a headphone is plugged into a jack
socket. In this mode, enabled bysetting HPSWEN, HPDETECT switches between headphone and
speaker outputs (typically, the pin is connected to a mechanical switch in the headphone socket to
detect plug-in). The HPSWPOL bit reverses the pin’s polarity. HPDETECT has CMOS thresholds at
0.3 AVDD / 0.7 AVDD. Note that the LOUT1, ROUT1, LOUT2 and ROUT2 bits in register 26 must
also be set to enable headphone and speaker outputs (see tables below).
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R24 (18h)
6
HPSWEN
0
0
Headphone Switch Enable
Additional (1)
0 : Headphone switch disabled
1 : Headphone switch enabled
Headphone Switch Polarity
5
HPSWPOL
0 : HPDETECT high = headphone
1 : HPDETECT high = speaker
Table 11 Headphone Switch
HPSWEN HPSWPOL HPDETECT L/ROUT1 L/ROUT2 Headphone
Speaker
(PIN23)
(reg. 26)
(reg. 26)
enabled
no
enabled
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
X
X
0
1
X
X
0
1
0
1
0
1
0
1
X
X
0
1
X
X
no
y
no
es
es
yes
yes
no
no
yes
no
y
no
no
no
no
no
no
no
y
yes
no
yes
no
no
es
Table 12 Headphone Switch Operation
Product Preview Rev 1.42 May2003
22
w
Product Preview
WM8751L
AVDD
/
HPSWEN = 1
HPSWPOL = 1
L/ROUT1 = L/ROUT2 = 1
-
-
ROUT1
LOUT1
L
R
47k
Ω
headphone /
speaker
switching
100k
Ω
HPDETECT
switch closes
on insertion
Figure TBD Example Headset Detection circuit using normally-open switch
AVDD
HPSWEN = 1
HPSWPOL = 0
L/ROUT1 = L/ROUT2 = 1
-
-
ROUT1
LOUT1
L
R
47k
Ω /
headphone /
speaker
switching
100k
Ω
switch opens
on insertion
HPDETECT
Figure TBD Example Headset Detection circuit using normally-closed switch
THERMAL SHUTDOWN
The speaker and headphone outputs can drive verylarge currents. To protect the WM8751L from
overheating, a thermal shutdown circuit is included. If the device temperature reaches approximately
1500C and the thermal shutdown circuit is enabled (TSDEN = 1 ) then the speaker and headphone
amplifiers (outputs OUT1L/R, OUT2L/R & OUT3) will be disabled.
REGISTER
ADDRESS
BIT
LABEL
TSDEN
DEFAULT
DESCRIPTION
R23 (17h)
8
0
Thermal Shutdown Enable
0 : thermal shutdown disabled
1 : thermal shutdown enabled
Additional (1)
Table 13 Thermal Shutdown
Product Preview Rev 1.42 May2003
w
23
WM8751L
Product Preview
LOUT1/ROUT1 OUTPUTS
The LOUT1 and ROUT1 pins can drive a 16Ω or 32Ω headphone or a line output (see Headphone
Output and Line Output sections, respectively). The signal volume on LOUT1 and ROUT1 can be
independentlyadjusted under software control bywriting to LOUT1VOL and ROUT1VOL,
respectively. Note that gains over 0dB may cause clipping if the signal is large. Any gain setting
below 0101111 (minimum gain) mutes the output driver. The corresponding output pin remains at the
same DC level (the reference voltage on the VREF pin), so that no click noise is produced when
muting or un-muting.
The analogue outputs have a zero cross detect feature to minimize audible clicks and zipper noise
when on gain changes (i.e. the updating of the gain value is delayed until the signal passes through
zero). Bydefault, this includes a time-out function, which forces the gain to update if no zero crossing
occurs within a certain period of time.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2 (02h)
LOUT1
Volume
6:0
LOUT1VOL
1111001
(0dB)
LOUT1 Volume
1111111 = +6dB
… (80 steps)
0110000 = -67dB
0101111 to 0000000 = Analogue MUTE
LOUT1 zero cross enable
1 = Change gain on zero cross only
0 = Change gain immediately
Left Volume Update
7
LO1ZC
LO1VU
0
0
8
0 = Store LOUT1VOL in intermediate
latch (no gain change)
1 = Update left and right channel gains
(left = LOUT1VOL, right =
intermediate latch)
R3 (03h)
ROUT1
Volume
6:0
7
ROUT1VOL
RO1ZC
1111001
ROUT1 Volume
Similar to LOUT1VOL
ROUT1 zero cross enable
Similar to LO1ZC
0
0
8
RO1VU
Right Volume Update
0 = Store ROUT1VOL in intermediate
latch (no gain change)
1 = Update left and right channel gains
(left = intermediate latch, right =
ROUT1VOL)
R23 (17h)
0
TOEN
1
Time-out enable for zero-cross detectors
0 = time-out disabled (i.e. gains are never
updated if there is no zero crossing)
1 = time-out enabled
Table 14 LOUT1/ROUT1 Volume Control
Product Preview Rev 1.42 May2003
24
w
Product Preview
WM8751L
LOUT2/ROUT2 OUTPUTS
The LOUT2 and ROUT2 output pins are essentiallysimilar to LOUT1 and ROUT1, but theyare
independentlycontrolled and can also drive an 8 Ω mono speaker. For speaker drive, the ROUT2
signal must be inverted (ROUT2INV = 1), so that the left and right channel are mixed to mono in the
speaker [L–(-R) = L+R].
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
similar to LOUT1VOL
R40 (28h)
LOUT2
6:0
LOUT2VOL
1111001
(0dB)
0
Volume
7
LO2ZC
Left zero cross enable
1 = Change gain on zero cross only
0 = Change gain immediately
similar to LO1VU
8
LO2VU
0
R41 (29h)
ROUT2
6:0
ROUT2VOL
1111001
(0dB)
0
similar to ROUT1VOL
Volume
7
RO2ZC
Left zero cross enable
1 = Change gain on zero cross only
0 = Change gain immediately
similar to RO1VU
8
RO2VU
TOEN
0
1
0
R23 (17h)
0
as for LOUT1 / ROUT1
R24 (18h)
3
ROUT2INV
ROUT2 Invert
Additional (2)
0 = No Inversion (0° phase shift)
1 = Signal inverted (180° phase shift)
Table 15 LOUT2/ROUT2 Control
MONO OUTPUT
The MONOOUT pin can drive a mono line output. The signal volume on MONOOUT can be adjusted
under software control bywriting to MONOOUTVOL.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R42 (2Ah)
MONOOUT
Volume
6:0
MONOOUT
VOL
1111001
(0dB)
MONOOUT Volume
1111111 = +6dB
… (80 steps)
0110000 = -67dB
0101111 to 0000000 = Analogue MUTE
MONOOUT zero cross enable
1 = Change gain on zero cross only
0 = Change gain immediately
as for LOUT1 / ROUT1
7
MOZC
TOEN
0
1
R23 (17h)
0
Table 16 MONOOUT Volume Control
OUT3 OUTPUT
The OUT3 pin can drive a 16Ω or 32Ω headphone or a line output or be used as a DC reference for a
headphone output. It can be selected to either drive out an inverted ROUT1 or inverted MONOOUT
for e.g. an earpiece drive between OUT3 and LOUT1 or differential output between OUT3 and
MONOOUT.
OUT3SW selects the mode of operation required.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
00
DESCRIPTION
R24 (18h)
8:7
OUT3SW
OUT3 select
00 : VREF
Additional (2)
01 : ROUT1
10 : MONOOUT
11 : right mixer output
Table 17 OUT3 select
Product Preview Rev 1.42 May2003
w
25
WM8751L
Product Preview
DIGITAL AUDIO INTERFACE
The digital audio interface is used for feeding audio data into the WM8751L. It uses three pins:
•
•
•
DACDAT: DAC data input
DACLRC: DAC data alignment clock
BCLK: Bit clock, for synchronisation
The clock signals BCLK and DACLRC can be outputs when the WM8751L operates as a master, or
inputs when it is a slave (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
•
•
•
•
Left justified
Right justified
I2S
DSP mode
All four of these modes are MSB first. Theyare described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8751L can be configured as either a master or slave mode device. As a master device the
WM8751L generates BCLK and DACLRC and thus controls sequencing of the data transfer on
DACDAT. In slave mode, the WM8751L responds with data to clocks it receives over the digital
audio interface. The mode can be selected bywriting to the MS control bit. Master and slave modes
are illustrated below.
BCLK
DACLRC
DACDAT
BCLK
DACLRC
DACDAT
WM8751
DAC
DSP /
DECODER
WM8751
DAC
DSP /
DECODER
Figure 8 Master Mode
AUDIO DATA FORMATS
Figure 9 Slave Mode
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a DACLRC
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequencyand sample rate, there maybe unused BCLK ccyles before each DACLRC
transition.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC
BCLK
DACDAT
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Note: Input word length is defined bythe WL register.
Timing is shown with LRP = 1
Input Word Length (WL)
Figure 10 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a DACLRC
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequencyand sample rate, there maybe unused BCLK cycles after each DACLRC transition.
Product Preview Rev 1.42 May2003
26
w
Product Preview
WM8751L
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC
BCLK
DACDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Data Word Length (WL)
Note: Word length is defined bythe WL register.
Timing is shown with LRP = 1
Figure 11 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a DACLRC transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequencyand sample rate, there maybe unused BCLK cycles between the LSB of one sample and
the MSB of the next.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC
BCLK
1 BCLK
1 BCLK
DACDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Note: Word length is defined bythe WL register.
Timing is shown with LRP = 1
Data Word Length (WL)
Figure 12 I2S Justified Audio Interface (assuming n-bit word length)
In DSP mode, the left channel MSB is available on either the first or second rising edge of BCLK
(selectable byLRP) following a rising edge of DACLRC. Right channel data immediatelyfollows left
channel data. Depending on word length, BCLK frequencyand sample rate, there maybe unused
BCLK cycles between the LSB of the right channel data and the next sample.
1/fs
1 BCLK
DACLRC
BCLK
RIGHT CHANNEL
n-2 n-1
LEFT CHANNEL
DACDAT
1
2
3
n
1
2
3
n
n-2 n-1
MSB
LSB
Data Word Length (WL)
Note: Word length is defined bythe WL register.
Timing is shown with LRP = 1
Figure 13 DSP Mode Audio Interface (Mode A; LRP = 0)
Product Preview Rev 1.42 May2003
27
w
WM8751L
Product Preview
1/fs
1 BCLK
DACLRC/
ADCLRC
BCLK
RIGHT CHANNEL
LEFT CHANNEL
DACDAT/
ADCDAT
1
2
3
n
1
2
3
n-2 n-1
n
n-2 n-1
MSB
LSB
Input Word Length (WL)
Figure 14 DSP Mode Audio Interface (Mode B; LRP = 1)
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised
below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7 (07h)
1:0
FORMAT
10
Audio Data Format Select
Digital Audio
Interface
Format
11 = DSP Mode
10 = I2S Format
01 = Left justified
00 = Right justified
Audio Data Word Length
11 = 32 bits (see Note)
10 = 24 bits
3:2
WL
10
0
01 = 20 bits
00 = 16 bits
4
LRP
I2S, LJ, RJ Formats
DSP Format
1: Right Channel data 1: MSB available on
when DACLRC high
2nd BCLK rising edge
after LRC rising edge
0: Right Channel data
when DACLRC low
0: MSB available on
1st BCLK rising edge
after LRC rising edge
5
6
7
LRSWAP
MS
0
0
0
Swap Left and Right Channels
0: No swap (L to L, R to R)
1: Swap (L to R, R to L)
Master / Slave Mode Control
1: Master Mode
0: Slave Mode
BCLKINV
BCLK Invert
1: BCLK inverted
0: BCLK not inverted
Table 18 Audio Data Format Control
Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual
word length will be 24 bits.
Product Preview Rev 1.42 May2003
28
w
Product Preview
WM8751L
MASTER CLOCK AND AUDIO SAMPLE RATES
The WM8751L supports a wide range of master clock frequencies on the MCLK pin, and can
generate manycommonlyused audio sample rates directlyfrom the master clock.
There are two clocking modes:
•
•
‘Normal’ mode supports master clocks of 128fs, 192fs, 256fs, 384fs, and their multiples
USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in
systems with a USB interface, and eliminates the need for an external PLL to generate
another clock frequencyfor the audio DAC.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
6
MCLKDIV2
0
Core Clock Divide by2
0: Core clock = MCLK
1: Core clock = MCLK / 2
Sample Rate Control
Clocking Mode Select
1: USB Mode
5:1
0
SR [4:0]
USB
0000
0
0: ‘Normal’ Mode
Table 19 Clocking and Sample Rate Control
The clocking of the WM8751L is controlled using the MCLKDIV2, USB, and SR control bits. Setting
the MCLKDIV2 bit divides MCLK bytwo internally. The USB bit selects between ‘Normal’ and USB
mode. Each combination of the SR4 to SR0 control bits selects one MCLK division ratio and hence
one sample rate (see next page). The digital filter characteristics are automaticallyadjusted to suit
the MCLK and sample rate selected (see Digital Filter Characteristics).
Since all sample rates are generated bydividing MCLK, their accuracydepends on the accuracyof
MCLK. If MCLK changes, the sample rates change proportionately. Note that some sample rates
(e.g. 44.1kHz in USB mode) are approximated, i.e. theydiffer from their target value bya verysmall
amount. This is not audible, as the maximum deviation is only0.27% (8.0214kHz instead of 8kHz in
USB mode - for comparison, a half-tone step corresponds to a 5.9% change in pitch).
Product Preview Rev 1.42 May2003
29
w
WM8751L
Product Preview
MCLK
MCLK
DAC SAMPLE RATE
USB
SR [4:0]
FILTER
TYPE
BCLK
MCLKDIV2=0
MCLKDIV2=1
(MS=1)
‘Normal’ Clock Mode (‘*’ indicates backward compatibilitywith WM8711 and WM8721)
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/2
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/2
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/3
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/3
12.288MHz
24.576MHz
8 kHz (MCLK/1536)
12 kHz (MCLK/1024)
16 kHz (MCLK/768)
24 kHz (MCLK/512)
32 kHz (MCLK/384)
48 kHz (MCLK/256)
96 kHz (MCLK/128)
8.0182 kHz (MCLK/1408)
11.025 kHz (MCLK/1024)
22.05 kHz (MCLK/512)
44.1 kHz (MCLK/256)
88.2 kHz (MCLK/128)
8 kHz (MCLK/2304)
12 kHz (MCLK/1536)
16 kHz (MCLK/1152)
24 kHz (MCLK/768)
32 kHz (MCLK/576)
48 kHz (MCLK/384)
96 kHz (MCLK/192)
8.0182 kHz (MCLK/2112)
11.025 kHz (MCLK/1536)
22.05 kHz (MCLK/768)
44.1 kHz (MCLK/384)
88.2 kHz (MCLK/192)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00010 *
01000
1
1
1
1
1
1
3
1
1
1
1
3
1
1
1
1
1
1
3
1
1
1
1
3
01010
11100
01100 *
00000 *
01110 *
10010
11.2896MHz
18.432MHz
22.5792MHz
36.864MHz
11000
11010
10000 *
11110 *
00011 *
01001
01011
11101
01101 *
00001 *
01111 *
10011 *
11001
16.9344MHz
33.8688MHz
11011
10001 *
11111 *
USB Mode (‘*’ indicates backward compatibilitywith WM8711 and WM8721)
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
12.000MHz
24.000MHz
8 kHz (MCLK/1500)
11.0259 kHz (MCLK/1088)
12kHz (MCLK/1000)
16kHz (MCLK/750)
1
1
1
1
1
1
1
1
1
1
1
00010 *
11001
0
1
0
0
1
0
0
1
0
3
2
01000
01010
22.0588 kHz (MCLK/544)
24kHz (MCLK/500)
11011
11100
32 kHz (MCLK/375)
01100 *
10001 *
00000 *
11111 *
01110 *
44.118 kHz (MCLK/272)
48 kHz (MCLK/250)
88.235kHz (MCLK/136)
96 kHz (MCLK/125)
Table 20 Master Clock and Sample Rates
Product Preview Rev 1.42 May2003
30
w
Product Preview
WM8751L
CONTROL INTERFACE
SELECTION OF CONTROL MODE
The WM8751L is controlled bywriting to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each
control register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The
MODE pin selects the interface format.
MODE
Low
INTERFACE FORMAT
2 wire
3 wire
High
Table 21 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, everyrising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB latches in a complete control word consisting of the last 16 bits.
latch
CSB
SCLK
SDIN
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
control register address
control register data bits
Figure 15 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8751L supports software control via a 2-wire serial bus. Manydevices can be controlled by
the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address
of each register in the WM8751L).
The WM8751L operates as a slave device only. The controller indicates the start of data transfer with
a high to low transition on SDIN while SCLK remains high. This indicates that a device address and
data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight
bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the
address of the WM8751L and the R/W bit is ‘0’, indicating a write, then the WM8751L responds by
pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’,
the WM8751L returns to the idle condition and wait for a new start condition and valid address.
Once the WM8751L has acknowledged a correct address, the controller sends the first byte of
control data (B15 to B8, i.e. the WM8751L register address plus the first bit of register data). The
WM8751L then acknowledges the first data byte by pulling SDIN low for one clock pulse. The
controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register
data), and the WM8751L acknowledges again bypulling SDIN low.
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8751L returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at anypoint
during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
Product Preview Rev 1.42 May2003
31
w
WM8751L
Product Preview
DEVICE ADDRESS RD / WR
(7 BITS) BIT
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
ACK
(LOW)
SDIN
SCLK
START
STOP
register address and
1st register data bit
remaining 8 bits of
register data
Figure 16 2-Wire Serial Control Interface
The WM8751L has two possible device addresses, which can be selected using the CSB pin.
CSB STATE
Low
DEVICE ADDRESS
0011010
High
0011011
Table 22 2-Wire MPU Interface Address Selection
Product Preview Rev 1.42 May2003
32
w
Product Preview
WM8751L
POWER SUPPLIES
The WM8751L can use up to four separate power supplies:
•
AVDD / AGND: Analogue supply, powers all analogue functions except the headphone drivers.
AVDD can range from 1.8V to 3.6V and has the most significant impact on overall power
consumption (except for power consumed in the headphone). A large AVDD slightlyimproves
audio quality.
•
HPVDD / HPGND: Headphone supply, powers the headphone drivers. HPVDD can range from
1.8V to 3.6V. HPVDD is normallytied to AVDD, but it requires separate layout and decoupling
capacitors to curb harmonic distortion. With a larger HPVDD, louder headphone outputs can be
achieved with lower distortion. If HPVDD is lower than AVDD, the output signal maybe clipped.
•
•
DCVDD: Digital core supply, powers all digital functions except the audio and control
interfaces. DCVDD can range from 1.42V to 3.6V, and has no effect on audio quality. The
return path for DCVDD is DGND, which is shared with DBVDD.
DBVDD: Digital buffer supply, powers the audio and control interface buffers. This makes it
possible to run the digital core at verylow voltages, saving power, while interfacing to other
digital devices using a higher voltage. DBVDD draws much less power than DCVDD, and has
no effect on audio quality. The return path for DBVDD is DGND, which is shared with DCVDD.
It is possible to use the same supplyvoltage on all four. However, digital and analogue supplies
should be routed and decoupled separatelyto keep digital switching noise out of the analogue signal
paths.
POWER MANAGEMENT
The WM8751L has two control registers that allow users to select which functions are active. For
minimum power consumption, unused functions should be disabled. To avoid anypop or click noise,
it is important to enable or disable functions in the correct order (see Applications Information)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
00
DESCRIPTION
R25 (19h)
8:7
VMIDSEL
VMID resistor divider select
Power
00 – VMID disabled
Management
(1)
01 – 50kΩ divider enabled
10 – 500kΩ divider enabled
VREF (necessaryfor all other functions)
DAC Left
6
8
7
6
5
4
3
2
1
VREF
0
0
0
0
0
0
0
0
0
R26 (1Ah)
DACL
Power
Management
(2)
DACR
LOUT1
ROUT1
LOUT2
ROUT2
MOUT
OUT3
DAC Right
LOUT1 Output Buffer*
ROUT1 Output Buffer*
LOUT2 Output Buffer*
ROUT2 Output Buffer*
MONOOUT Output Buffer and Mono Mixer
OUT3 Output Buffer
Note: All control bits are 0=OFF, 1=ON
* The left mixer is enabled when LOUT1=1 or LOUT2=1. The right mixer is enabled when
ROUT1=1 or ROUT2=1.
Table 23 Power Management
Product Preview Rev 1.42 May2003
33
w
WM8751L
Product Preview
STOPPING THE MASTER CLOCK
In order to minimise power consumed in the digital core of the WM8751L, the master clock should be
stopped in Standbyand OFF modes. If this is cannot be done externallyat the clock source, the
DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core.
However, since setting DIGENB has no effect on the power consumption of other system
components external to the WM8751L, it is preferable to disable the master clock at its source
wherever possible.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R25 (19h)
1
DIGENB
0
Master clock disable
Additional Control
(1)
0: master clock enabled
1: master clock disabled
Table 2 ADC and DAC Oversampling Rate Selection
NOTE: Before DIGENB can be set, the control bits DACL and DACR must be set to zero and a
waiting time of 1ms must be observed. Any failure to follow this procedure may prevent DACs
and ADCs from re-starting correctly.
SAVING POWER BY REDUCING OVERSAMPLING RATE
Bydefault, the oversampling rate of the DAC digital filters is 128x. However, this can be changed to
64x bywriting to the DACOSR bit. In the 64x oversampling mode, the digital filters consumes less
power. However, the signal-to-noise ratio is slightlyreduced.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R24 (18h)
0
DACOSR
0
DAC oversample rate select
1 = 64x (lowest power)
0 = 128x (best SNR)
Additional
Functions (2)
Table 24 Oversampling Rate Selection
SAVING POWER AT LOW SUPPLY VOLTAGES
The analogue supplies to the WM8751L can run from 1.8V to 3.6V. Bydefault, all analogue circuitry
on the device is optimized to run at 3.3V. This set-up is also good for all other supplyvoltages down
to 1.8V. However, at lower voltages, it is possible to save power byreducing the internal bias
currents used in the analogue circuitry. This is controlled as shown below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R23 (17h)
7:6
VSEL[1:0]
11
Analogue Bias optimization
Additional
Control(1)
00 : Lowest bias current, optimized for 1.8V
01 : Low bias current, optimized for 2.5V
10, 11 : Default bias current, optimized for 3.3V
Table 25 Analogue Bias Selection
Product Preview Rev 1.42 May2003
w
34
Product Preview
WM8751L
REGISTER MAP
REGISTER ADDRESS REMARKS
(BIT 15 – 9)
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
R0 (00h)
R1 (01h)
R2 (02h)
R3 (03h)
R4 (04h)
R5 (05h)
R6 (06h)
R7 (07h)
R8 (08h)
0000000
0000001
0000010
0000011
0000100
0000101
0000110
Reserved
Reserved
LOUT1
000000000
000000000
LO1VU
RO1VU
LO1ZC
RO1ZC
LOUT1VOL
ROUT1VOL
ROUT1
Reserved
DAC Control
Reserved
000000000
0
0
DAT
0
0
DACMU
DEEMPH
0
000000000
LRP
0000111 Audio Interface
0
0
BCLKINV
BCLK
MS
LRSWAP
WL
FORMAT
0001000
Clocking
MCLK
DIV2
SR
USB
DIV2
R9 (09h)
0001001
0001010
0001011
0001100
0001101
0001110
0001111
Reserved
Left Gain
Right Gain
Bass
000000000
R10 (0Ah)
R11 (0Bh)
R12 (0Ch)
R13 (0Dh)
R14 (0Eh)
R15 (0Fh)
R16 – R22
R23 (17h)
R24 (18h)
R25 (19h)
R26 (1Ah)
R27 – R33
R34 (22h)
R35 (23h)
R36 (24h)
R37 (25h)
R38 (26h)
R39 (27h)
R40 (28h)
R41 (29h)
R42 (2Ah)
LDVU
LDACVOL (Right DAC Digital Volume)
RDACVOL (Right DAC Digital Volume)
RDVU
0
0
BB
0
BC
TC
0
0
0
0
BASS (Bass Intensity)
TRBL (Treble Intensity)
Treble
TBD
000000000
Reset
writing 000000000 to this register resets all registers to their default state
000000
Reserved
0010111 Additional (1) TSDEN
VSEL
DMONOMIX
0
HPZC
0
0
DACINV
TOEN
DACOSR
DIGENB
0
0011000 Additional (2)
0011001 Pwr Mgmt (1)
0011010 Pwr Mgmt (2)
Reserved
OUT3SW
VMIDSEL
HPSWEN HPSWPOL ROUT2INV
0
0
0
0
VREF
0
0
DACL
DACR
LOUT1
ROUT1
LOUT2
000000
ROUT2
MOUT
OUT3
0100010
0100011
Left Mix (1)
Left Mix (2)
LD2LO
RD2LO
LD2RO
RD2RO
LI2LO
MI2LO
MI2RO
RI2RO
LI2MO
RI2MO
LO2ZC
RO2ZC
MOZC
LI2LOVOL
MI2LOVOL
MI2ROVOL
RI2ROVOL
LI2MOVOL
RI2MOVOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0100101 Right Mix (2)
0100100 Right Mix (1)
0
0
0
0
0
DMEN
0
0100110 Mono Mix (1) LD2MO
0100111 Mono Mix (2) RD2MO
0
0101000
0101001
0101010
LOUT2
ROUT2
LO2VU
RO2VU
0
LOUT2VOL
ROUT2VOL
ROUT2VOL
MONOOUT
Product Preview Rev 1.42 May2003
35
w
WM8751L
Product Preview
DIGITAL FILTER CHARACTERISTICS
Depending on the MCLK frequencyand sample rate selected, 4 different types of digital filter can be
used in the DAC, called Type 0, 1, 2 and 3 (see “Master Clock and Audio Sample Rates”). The
performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the
following pages.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.416fs
+/-0.03
UNIT
DAC Filter Type 0 (USB mode, 250fs operation)
Passband
+/- 0.03dB
-6dB
0
0.5fs
Passband Ripple
Stopband
dB
dB
0.584fs
-50
Stopband Attenuation
f > 0.584fs
DAC Filter Type 1 (USB mode, 272fs or Normal mode operation)
Passband
+/- 0.03dB
-6dB
0
0.4535fs
+/- 0.03
0.5fs
Passband Ripple
Stopband
dB
dB
0.5465fs
-50
Stopband Attenuation
f > 0.5465fs
Table 26 Digital Filter Characteristics
TERMINOLOGY
1. Stop Band Attenuation (dB) – the degree to which the frequencyspectrum is attenuated (outside audio band)
2. Pass-band Ripple – anyvariation of the frequencyresponse in the pass-band region
DAC FILTER RESPONSES
0.02
0
0.01
-20
0
-0.01
-40
-0.02
-60
-0.03
-0.04
-80
-0.05
-100
0
0.5
1
1.5
2
2.5
3
-0.06
Frequency (Fs)
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
Figure 17 DAC Filter Frequency Response – Type 0
Figure 18 DAC Filter Ripple – Type 0
Product Preview Rev 1.42 May2003
36
w
Product Preview
WM8751L
0.02
0.01
0
0
-20
-40
-60
-80
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-100
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 19 DAC Filter Frequency Response – Type 1
Figure 20 DAC Filter Ripple – Type 1
0.02
0.01
0
0
-20
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-40
-60
-80
-100
0
0.05
0.1
0.15
0.2
0.25
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 21 DAC Filter Frequency Response – Type 2
Figure 22 DAC Filter Ripple – Type 2
0
-0.05
-0.1
0
-20
-40
-0.15
-0.2
-60
-80
-0.25
-100
0
0.05
0.1
0.15
0.2
0.25
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 23 DAC Filter Frequency Response – Type 3
Figure 24 DAC Filter Ripple – Type 3
Product Preview Rev 1.42 May2003
37
w
WM8751L
Product Preview
PACKAGE DIMENSIONS
FL: 32 PIN QFN PLASTIC PACKAGE 5
X
5
X
0.9 mm BODY, 0.50 mm LEAD PITCH
DM030.C
SEE DETAIL A
D
CORNER
TIE BAR
D2
B
D2/2
5
25
32
L
1
24
INDEX AREA
(D/2 X E/2)
E2/2
A
E2
E
SEE DETAIL B
17
8
aaa
C
2 X
16 15
9
b
aaa
C
2 X
B
e
TOP VIEW
DETAIL A
ccc
C
(A3)
1
CORNER
TIE BAR
A
0.08
C
1
32x b
A
C B
5
M
A1
bbb
C
SEATING PLANE
DETAIL B
EXPOSED
CENTRE
PAD
1
L1
Symbols
Dimensions (mm)
MIN
0.85
0
NOM
0.90
0.02
MAX
1.00
0.05
NOTE
A
A1
A3
b
D
D2
E
E2
e
L
L1
R
K
0.2 REF
0.23
5.00
3.3
5.00
0.18
4.90
3.2
0.30
5.10
3.4
5.10
3.4
1
2
2
4.90
3.2
3.3
0.5 BSC
0.4
0.35
0.45
0.1
1
b(min)/2
0.20
Tolerances of Form and Position
aaa
bbb
ccc
0.15
0.10
0.10
JEDEC, MO-220, VARIATION VKKD-2
REF:
NOTES:
1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM
PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF
ETCHING OF LEADFRAME.
2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2:
D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION
3. ALL DIMENSIONS ARE IN MILLIMETRES
4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY
Product Preview Rev 1.42 May2003
38
w
Product Preview
WM8751L
APPLICATIONS INFORMATION
MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS
To minimise anypop or click noise when the system is powered up or down, the following procedures
are recommended.
POWER UP
•
•
•
Switch on power supplies. Bydefault the WM8751L is in OFF Mode (i.e. onlythe control
interface is powered up)
Enable the reference voltage VREF bysetting the WM8751L to Standbymode. DO NOT
enable anyof the analogue outputs at this point.
Allow VREF to settle. The settling time depends on the value of the capacitor connected at
VMID (formula TBD).
•
•
•
Enable outputs, DACs, etc. (sequence TBD)
Set ACTIVE = 1 to enable the Audio Interface
Set DACMU = 0 to soft-un-mute the audio DACs.
POWER DOWN
•
•
•
Set DACMU = 1 to soft-mute the audio DACs.
Disable functions (sequence TBD)
Switch off the power supplies.
LINE OUTPUT CONFIGURATION
All the analogue outputs, LOUT1/ROUT1, LOUT2/ROUT2, and MONOOUT, can be used as line
outputs. Recommended external components are shown below.
C1
R1
1uF
100 Ohm
LINE-OUT SOCKET
(LEFT)
LOUT2
ROUT2
AGND
AGND
WM8751L
LINE-OUT SOCKET
(RIGHT)
C2
1uF
R2
100 Ohm
Figure 25 Recommended Circuit for Line Output
The DC blocking capacitors and the load resistance together determine the lower cut-off frequency,
fc. Assuming a 10 kOhm load and C1, C2 = 10µF:
fc = 1 / 2π (RL+R1) C1 = 1 / (2π x 10.1kΩ x 1µF) = 16 Hz
Increasing the capacitance lowers fc, improving the bass response. Smaller values of C1 and C2 will
diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage
when used improperly.
Product Preview Rev 1.42 May2003
39
w
WM8751L
Product Preview
HEADPHONE OUTPUT CONFIGURATION
The analogue outputs LOUT1/ROUT1, LOUT2/ROUT2, and OUT3 can drive a 16Ω or 32Ω
headphone load, either through DC blocking capacitors, or DC coupled without anycapacitor.
DC Coupled Headphone Output
(OUT3SW = 00)
Headphone Output using DC blocking
capacitors
C1 220uF
LOUT1
LOUT1
ROUT1
WM8751L
HPDCEN = 1
WM8751L
C2 220uF
ROUT1
HPGND = 0V
HPDC = AVDD/2
Figure 26 Recommended Headphone Output Configurations
When DC blocking capacitors are used, then their capacitance and the load resistance together
determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass
response. Smaller capacitance values will diminish the bass response. Assuming a 16 Ohm load and
C1 = 220µF:
fc = 1 / 2π RLC1 = 1 / (2π x 16Ω x 220µF) = 45 Hz
In the DC coupled configuration, the headphone “ground” is connected to the OUT3 pin, which must
be enabled bysetting O3 = 1 and OUT3SW = 00. As the OUT3 pin produces a DC voltage of
AVDD/2 (=VREF), there is no DC offset between LOUT1/ROUT1 and OUT3, and therefore no DC
blocking capacitors are required. This saves space and material cost in portable applications.
It is recommended to connect the DC coupled headphone outputs onlyto headphones, and not to
the line input of another device. Although the built-in short circuit protection will prevent anydamage
to the headphone outputs, such a connection maybe noisy, and maynot function properlyif the
other device is grounded.
SPEAKER OUTPUT CONFIGURATION
LOUT2 and ROUT2 can differentiallydrive a mono 8 Ω speaker as shown below.
LEFT
MIXER
LOUT2
LOUT2VOL
WM8751L
ROUT2INV = 1
VSPKR = L-(-R) = L+R
-1
ROUT2
RIGHT
MIXER
ROUT2VOL
Figure 27 Speaker Output Connection
The right channel is inverted bysetting the ROUT2INV bit, so that the signal across the loudspeaker
is the sum of left and right channels.
Product Preview Rev 1.42 May2003
w
40
Product Preview
WM8751L
IMPORTANT NOTICE
Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue anyproduct or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of
liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s
standard warranty. Testing and other qualitycontrol techniques are utilised to the extent WM deems necessaryto support this
warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by
the customer to minimise inherent or procedural hazards.
WM assumes no liabilityfor applications assistance or customer product design. WM does not warrant or represent that any
license, either express or implied, is granted under anypatent right, copyright, mask work right, or other intellectual property
right of WM covering or relating to anycombination, machine, or process in which such products or services might be or are
used. WM’s publication of information regarding anythird party’s products or services does not constitute WM’s approval,
license, warrantyor endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissable onlyif reproduction is without alteration and is
accompanied byall associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for anysuch use.
Resale of WM’s products or services with statements different from or beyond the parameters stated byWM for that product
or service voids all express and anyimplied warranties for the associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for anysuch use.
ADDRESS:
Wolfson Microelectronics Ltd
20 Bernard Terrace
Edinburgh
EH8 9NX
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
Product Preview Rev 1.42 May2003
w
41
相关型号：
WM8753LEFL/V
PCM Codec, 1-Func, CMOS, PQCC48, 7 X 7 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-220VKKD-2, QFN-48
CIRRUS
©2020 ICPDF网 联系我们和版权申明