WM8976_06_技术文档

WM8976

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Stereo CODEC With Speaker Driver

DESCRIPTION

FEATURES

Stereo CODEC:

The WM8976 is a low power, high quality CODEC designed for

portable applications such as multimedia phone, digital still

camera or digital camcorder.

•

DAC SNR 98dB, THD -84dB (‘A’ weighted @ 48kHz)

ADC SNR 95dB, THD -84dB (‘A’ weighted @ 48kHz)

On-chip Headphone Driver with ‘capless’ option

The device integrates a preamp for differential microphone, and

includes drivers for speakers, headphone and differential or

stereo line output. External component requirements are

reduced as no separate microphone or headphone amplifiers

are required.

-

40mW per channel into 16Ω / 3.3V SPKVDD

•

0.9W output power into 8Ω BTL speaker / 5V SPKVDD

-

Capable of driving piezo speakers

Stereo speaker drive configuration

Mic Preamps:

•

Differential or single-ended microphone interfaces

Advanced on-chip digital signal processing includes a 5-band

equaliser, a mixed signal Automatic Level Control for the

microphone or line input through the ADC as well as a purely

digital limiter function for record or playback. Additional digital

filtering options are available in the ADC path, to cater for

application filtering such as ‘wind noise reduction’.

-

Programmable preamp gain

Psuedo differential input with common mode rejection

Programmable ALC / Noise Gate in ADC path

•

Low-noise bias supplied for electret microphone

Other Features:

•

Enhanced 3-D function for improved stereo separation

Digital playback limiter

The WM8976 digital audio interface can operate as a master or

a slave. An internal PLL can generate all required audio clocks

for the CODEC from common reference clock frequencies, such

as 12MHz and 13MHz.

5-band Equaliser (record or playback)

Programmable ADC High Pass Filter (wind noise reduction)

Programmable ADC Notch Filter

Aux inputs for stereo analog input signals or ‘beep’

On-chip PLL supporting 12, 13, 19.2MHz and other clocks

Support for 8, 11.025, 12, 16, 22.05, 24, 32, 44.1 and

48kHz sample rates

The WM8976 operates at analogue supply voltages from 2.5V

to 3.3V, although the digital core can operate at voltages down

to 1.71V to save power. The speaker outputs and OUT3/4 line

outputs can run from a 5V supply if increased output power is

required. Individual sections of the chip can also be powered

down under software control.

•

Low power, low voltage

-

2.5V to 3.6V (digital: 1.71V to 3.6V)

5x5mm 32-lead QFN package

APPLICATIONS

•

Stereo Camcorder or DSC

Multimedia Phone

Pre-Production, April 2006, Rev 3.0

WOLFSON MICROELECTRONICS plc

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WM8976

Pre-Production

TABLE OF CONTENTS

DESCRIPTION .......................................................................................................1

FEATURES.............................................................................................................1

APPLICATIONS .....................................................................................................1

TABLE OF CONTENTS .........................................................................................2

PIN CONFIGURATION...........................................................................................4

ORDERING INFORMATION ..................................................................................4

PIN DESCRIPTION ................................................................................................5

ABSOLUTE MAXIMUM RATINGS.........................................................................6

RECOMMENDED OPERATING CONDITIONS .....................................................6

ELECTRICAL CHARACTERISTICS ......................................................................7

TERMINOLOGY.......................................................................................................... 10

SPEAKER OUTPUT THD VERSUS POWER ......................................................11

POWER CONSUMPTION ....................................................................................12

AUDIO PATHS OVERVIEW.................................................................................14

SIGNAL TIMING REQUIREMENTS.....................................................................15

SYSTEM CLOCK TIMING ........................................................................................... 15

AUDIO INTERFACE TIMING – MASTER MODE ........................................................ 15

AUDIO INTERFACE TIMING – SLAVE MODE............................................................ 16

CONTROL INTERFACE TIMING – 3-WIRE MODE .................................................... 17

CONTROL INTERFACE TIMING – 2-WIRE MODE .................................................... 18

DEVICE DESCRIPTION.......................................................................................19

INTRODUCTION......................................................................................................... 19

INPUT SIGNAL PATH................................................................................................. 21

ANALOGUE TO DIGITAL CONVERTER (ADC).......................................................... 25

INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 29

OUTPUT SIGNAL PATH ............................................................................................. 41

3D STEREO ENHANCEMENT.................................................................................... 48

ANALOGUE OUTPUTS............................................................................................... 48

DIGITAL AUDIO INTERFACES................................................................................... 63

AUDIO SAMPLE RATES............................................................................................. 68

MASTER CLOCK AND PHASE LOCKED LOOP (PLL)............................................... 68

COMPANDING............................................................................................................ 70

GENERAL PURPOSE INPUT/OUTPUT...................................................................... 72

OUTPUT SWITCHING (JACK DETECT)..................................................................... 73

CONTROL INTERFACE.............................................................................................. 74

RESETTING THE CHIP .............................................................................................. 75

POWER SUPPLIES .................................................................................................... 76

RECOMMENDED POWER UP/DOWN SEQUENCE .................................................. 77

POWER MANAGEMENT ............................................................................................ 81

REGISTER MAP...................................................................................................82

REGISTER BITS BY ADDRESS..........................................................................84

DIGITAL FILTER CHARACTERISTICS...............................................................99

TERMINOLOGY.......................................................................................................... 99

DAC FILTER RESPONSES....................................................................................... 100

ADC FILTER RESPONSES....................................................................................... 100

HIGHPASS FILTER................................................................................................... 101

5-BAND EQUALISER................................................................................................ 102

APPLICATION INFORMATION..........................................................................106

RECOMMENDED EXTERNAL COMPONENTS........................................................ 106

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PACKAGE DIAGRAM ........................................................................................107

IMPORTANT NOTICE........................................................................................108

ADDRESS: ................................................................................................................ 108

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PIN CONFIGURATION

ORDERING INFORMATION

ORDER CODE

TEMPERATURE

RANGE

PACKAGE

MOISTURE

SENSITIVITY LEVEL

PEAK SOLDERING

TEMPERATURE

WM8976GEFL/V

-25°C to +85°C

32-lead QFN (5 x 5 mm)

(Pb-free)

MSL3

260^oC

WM8976GEFL/RV

-25°C to +85°C

32-lead QFN (5 x 5 mm)

(Pb-free, tape and reel)

260^oC

Note:

Reel quantity = 3,500

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PIN DESCRIPTION

1

NAME

LIP

TYPE

Analogue input

Do not connect

Digital Input / Output

Digital Output

Digital Input

DESCRIPTION

Mic Pre-amp positive input

Mic Pre-amp negative input

2

LIN

3

L2/GPIO2

DNC

Line input/secondary mic pre-amp positive input/GPIO2 pin

Leave this pin floating

4

5

DNC

Leave this pin floating

6

DNC

Leave this pin floating

7

LRC

DAC and ADC Sample Rate Clock

Digital Audio Port Clock

8

BCLK

9

ADCDAT

DACDAT

MCLK

ADC Digital Audio Data Output

DAC Digital Audio Data Input

Master Clock Input

10

11

12

13

14

15

16

Digital Input

DGND

DCVDD

DBVDD

CSB/GPIO1

SCLK

Supply

Digital ground

Supply

Digital core logic supply

Supply

Digital buffer (I/O) supply

Digital Input / Output

Digital Input

3-Wire Control Interface Chip Select / GPIO1 pin

3-Wire Control Interface Clock Input / 2-Wire Control Interface Clock

Input

17

18

19

20

21

SDIN

MODE

AUXL

AUXR

OUT4

Digital Input / Output

Digital Input

3-Wire Control Interface Data Input / 2-Wire Control Interface Data Input

Control Interface Selection

Analogue input

Analogue Output

Left Auxillary input

Right Auxillary input

Buffered midrail Headphone pseudo-ground, or Right line output or MONO

mix output

22

23

24

25

26

27

28

29

30

31

32

OUT3

ROUT2

SPKGND

LOUT2

SPKVDD

VMID

Analogue Output

Supply

Buffered midrail Headphone pseudo-ground, or Left line output

Second right output, or BTL speaker driver positive output

Speaker ground (feeds speaker amp and OUT3/OUT4)

Second left output, or BTL speaker driver negative output

Speaker supply (feed speaker amp only)

Decoupling for ADC and DAC reference voltage

Analogue ground (feeds ADC and DAC)

Headphone or Line Output Right

Analogue Output

Supply

Reference

AGND

Supply

ROUT1

LOUT1

AVDD

Analogue Output

Supply

Headphone or Line Output Left

Analogue supply (feeds ADC and DAC)

MICBIAS

Analogue Output

Microphone Bias

Note:

It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB. Refer to

the application note WAN_0118 on “Guidelines on How to Use QFN Packages and Create Associated PCB Footprints”

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ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously

operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given

under Electrical Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible

to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage

of this device.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage

conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.

MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

CONDITION

DBVDD, DCVDD, AVDD supply voltages

SPKVDD supply voltage

MIN

-0.3V

MAX

+4.5V

-0.3V

+7V

Voltage range digital inputs

DGND -0.3V

AGND -0.3V

-25°C

DVDD +0.3V

AVDD +0.3V

+85°C

Voltage range analogue inputs

Operating temperature range, T_A

Storage temperature after soldering

Notes

-65°C

+150°C

1. Analogue and digital grounds must always be within 0.3V of each other.

2. All digital and analogue supplies are completely independent from each other, i.e. not internally connected.

3. Analogue supply has to be ≥ to digital.

4. In non-boosted mode, SPKVDD should = AVDD, if boosted SPKVDD should be ≥ 1.5x AVDD.

5. When using PLL, DCVDD should be ≥ 1.9V.

6. DBVDD must be greater than or equal to DCVDD.

RECOMMENDED OPERATING CONDITIONS

PARAMETER

SYMBOL

TEST

MIN

TYP

MAX

UNIT

CONDITIONS

Digital supply range (Core)

Digital supply range (Buffer)

Analogue core supply range

Analogue output supply range

Ground

DCVDD

DBVDD

1.71¹

1.71

2.5

3.6

5.5

V

AVDD

SPKVDD

DGND, AGND,

SPKGND

2.5

0

Notes

1. When using the PLL, DCVDD must not be less than 1.9V.

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ELECTRICAL CHARACTERISTICS

Test Conditions

DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T_A= +25^oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise

stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Microphone Preamp Inputs (LIP, LIN, RIP)

Full-scale Input Signal Level –

note this changes in proportion

to AVDD (Note 1)

V_INFS

PGABOOST = 0dB

INPPGAVOL = 0dB

1.0

0

Vrms

dBV

Mic PGA equivalent input noise

At 35.25dB

gain

0 to 20kHz

150

uV

Input resistance

R_MICIN

R_MICIP

C_MICIN

Gain set to 35.25dB

Gain set to 0dB

1.6

47

75

94

10

kΩ

pF

Gain set to -12dB

L/RIP2INPPGA = 1

MIC Programmable Gain Amplifier (PGA)

Programmable Gain

-12

35.25

dB

Programmable Gain Step Size

Mute Attenuation

Guaranteed monotonic

0.75

120

Selectable Input Gain Boost (0/+20dB)

Gain Boost on PGA input

Boost disabled

Boost enabled

0

dB

20

Gain range from AUXL or L2

input to boost/mixer

+6

Gain step size to boost/mixer

3

dB

Auxilliary Analogue Inputs (AUXL, AUXR)

Full-scale Input Signal Level

(0dB) – note this changes in

proportion to AVDD

V_INFS

AVDD/3.3

0

Vrms

dBV

Input Capacitance

C_MICIN

10

pF

Automatic Level Control (ALC)

Target Record Level

-22.5

-12

-1.5

dB

ms

Programmable gain

35.25

Gain Hold Time (Note 3,5)

t_HOLD

t_DCY

MCLK = 12.288MHz

(Note 3)

0, 2.67, 5.33, 10.67, … , 43691

(time doubles with each step)

3.3, 6.6, 13.1, … , 3360

Gain Ramp-Up (Decay) Time

(Note 4,5)

ALCMODE=0 (ALC),

MCLK=12.288MHz

(Note 3)

(time doubles with each step)

ALCMODE=1 (limiter),

MCLK=12.288MHz

(Note 3)

0.73, 1.45, 2.91, … , 744

(time doubles with each step)

Gain Ramp-Down (Attack) Time

(Note 4,5)

t_ATK

ALCMODE=0 (ALC),

MCLK=12.288MHz

(Note 3)

0.83, 1.66, 3.33, … , 852

ms

(time doubles with each step)

ALCMODE=1 (limiter),

MCLK=12.288MHz

(Note 3)

0.18, 0.36, 0.73, … , 186

(time doubles with each step)

Mute Attenuation

120

dB

Analogue to Digital Converter (ADC)

Signal to Noise Ratio (Note 6)

Total Harmonic Distortion

(Note 7)

SNR

THD

A-weighted, 0dB gain

-3dBFS input

95

dB

-84

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Test Conditions

DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T_A= +25^oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise

stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Digital to Analogue Converter (DAC) to Line-Out (LOUT1, ROUT1 with 10kΩ / 50pF load)

Full-scale output

PGA gains set to 0dB,

OUT34BOOST=0

AVDD/3.3

Vrms

PGA gains set to 0dB,

OUT34BOOST=1

A-weighted

1.5x

(AVDD/3.3)

98

Signal to Noise Ratio (Note 6)

Total Harmonic Distortion

(Note 7)

SNR

THD

dB

R_L= 10kΩ

-84

full-scale signal

1kHz signal

Channel Separation (Note 9)

Output Mixers (LMX1, RMX1)

PGA gain range into mixer

PGA gain step into mixer

110

dB

-15

-57

0

3

+6

dB

Analogue Outputs (LOUT1, ROUT1, LOUT2, ROUT2)

Programmable Gain range

0

1

dB

Programmable Gain step size

Monotonic

1kHz, full scale signal

Mute attenuation

85

Headphone Output (LOUT1, ROUT1 with 32Ω load)

0dB full scale output voltage

AVDD/3.3

102

Vrms

dB

%

Signal to Noise Ratio

SNR

THD

A-weighted

R_L= 16Ω, Po=20mW

AVDD=3.3V

Total Harmonic Distortion

0.003

-92

dB

%

R_L= 32 Ω, Po=20mW

AVDD=3.3V

0.008

- 82

dB

Speaker Output (LOUT2, ROUT2 with 8Ω bridge tied load, INVROUT2=1)

Full scale output voltage, 0dB

gain. (Note 9)

SPKBOOST=0

SPKBOOST=1

SPKVDD/3.3

Vrms

(SPKVDD/3.3)*1.5

Output Power

P_O

Output power is very closely correlated with THD; see below

Total Harmonic Distortion

THD

P_O=200mW, R_L= 8Ω,

0.04

-68

1.0

-40

0.02

-74

1.0

-40

90

%

dB

%

SPKVDD=3.3V

P_O=320mW, R_L= 8Ω,

SPKVDD=3.3V

dB

%

P_O=500mW, R_L= 8Ω,

SPKVDD=5V

dB

%

P

_O=860mW, R_L= 8Ω,

SPKVDD=5V

dB

Signal to Noise Ratio

SNR

SPKVDD=3.3V,

R_L= 8Ω

SPKVDD=5V,

R_L= 8Ω

90

dB

Power Supply Rejection Ratio

(50Hz-22kHz)

PSRR

R_L= 8Ω BTL

80

69

dB

SPKVDD=5V (boost)

OUT3/OUT4 outputs (with 10kΩ / 50pF load)

Full-scale output voltage, 0dB

gain (Note 9)

OUT3BOOST=0/

OUT4BOOST=0

OUT3BOOST=1

OUT4BOOST=1

A-weighted

SPKVDD/3.3

Vrms

(SPKVDD/3.3)*1.5

Signal to Noise Ratio (Note 6)

Total Harmonic Distortion

(Note 7)

SNR

THD

98

dB

R_L= 10 kΩ

-84

full-scale signal

1kHz signal

Channel Separation (Note 8)

100

dB

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Test Conditions

DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T_A= +25^oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise

stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

52

MAX

UNIT

dB

Power Supply Rejection Ratio

(50Hz-22kHz)

PSRR

R_L= 10kΩ

56

dB

SPKVDD=5V (boost)

Microphone Bias

Bias Voltage

V_MICBIAS

MBVSEL=0

MBVSEL=1

0.9*AVDD

V

0.65*AVDD

Bias Current Source

Output Noise Voltage

Digital Input / Output

Input HIGH Level

Input LOW Level

I_MICBIAS

Vn

3

mA

1K to 20kHz

15

nV/√Hz

V_IH

V_IL

0.7×DBVDD

0.9×DBVDD

V

0.3×DBVDD

Output HIGH Level

Output LOW Level

Input capacitance

Input leakage

V_OH

V_OL

I_OL=1mA

I_OH-1mA

V

0.1xDBVDD

V

TBD

pF

pA

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TERMINOLOGY

1. Input level to LIP is limited to a maximum of -3dB or THD+N performance will be reduced.

2. Note when BEEP path is not enabled then AUXL and AUXR have the same input impedances.

3. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It does

not apply to ramping down the gain when the signal is too loud, which happens without a delay.

4. Ramp-up and Ramp-Down times are defined as the time it takes for the PGA to sweep across 90% of its gain range.

5. All hold, ramp-up and ramp-down times scale proportionally with MCLK

6. Signal-to-noise ratio (dB) – SNR is a measure of the difference in level between the full scale output and the output

with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).

7. THD+N (dB) – THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.

8. Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from

the other. Measured by applying a full scale signal to one channel input and measuring the level of signal apparent at

the other channel output.

9. The maximum output voltage can be limited by the speaker power supply. If OUT3BOOST, OUT4BOOST or

SPKBOOST is set then SPKVDD should be 1.5xAVDD to prevent clipping taking place in the output stage (when

PGA gains are set to 0dB).

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SPEAKER OUTPUT THD VERSUS POWER

Speaker Power vs THD+N (8Ohm BTL Load)

AVDD=SPKVDD=DBVDD=3.3, DCVDD=1.8

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0.00

50.00

100.00

150.00

200.00

250.00

300.00

350.00

400.00

450.00

500.00

Output Power (mW)

Speaker Power vs THD+N (8Ohm BTL Load)

AVDD=DBVDD=3.3V, SPKVDD=5V, DCVDD=1.8V

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0.00

100.00

200.00

300.00

400.00

500.00

600.00

700.00

800.00

900.00

1000.00

Output Power (mW)

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POWER CONSUMPTION

Typical current consumption for various scenarios is shown below.

AVDD

(3.0V)

(mA)

DCVDD

(1.8V)

(mA)

0.0008

1.0

DBVDD¹

(3.0V)

(mA)

<0.0001

0.001

TOTAL

POWER

(mW)

0.12

14.1

21.1

29.4

66.1

MODE

Off

0.04³

Sleep (VREF maintained, no clocks)

MIC Record (8kHz)²

Stereo 16Ω HP Playback (48kHz, quiescent)²

Stereo 16Ω HP Playback (48kHz, white noise)²

Stereo 16Ω HP Playback (48kHz, sine wave)²

Notes:

0.04

4.1

3.3

5.4

18

6.2

0.004

7.3

0.004

6.7

0.004

1. DBVDD Current will increase with greater loading on digital I/O pins.

2. 5 Band EQ is enabled.

3. AVDD standby current will fall to nearer 15uA when thermal shutdown sensor is disabled.

Table 1 Power Consumption

ESTIMATING SUPPLY CURRENT

When either the DAC or ADC is enabled approximately 7mA will be drawn from DCVDD when

DCVDD=1.8V and fs=48kHz. When the PLL is enabled approximately 1.5mA additional current will

be drawn from DCVDD.

As a general rule, digital supply currents will scale in proportion to sample rates. Supply current for

analogue and digital blocks will also be lower at lower supply voltages.

Power consumed by the output drivers will depend greatly on the signal characteristics. A quiet

signal, or a signal with long periods of silence will consume less power than a signal which is

continuously loud.

Estimated supply current for the analogue blocks is shown in Table 2. Note that power dissipated in

the load is not shown.

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REGISTER BIT

AVDD CURRENT (mA)

AVDD=3.3V

BUFDCOPEN

OUT4MIXEN

OUT3MIXEN

PLLEN

0.1

0.2

1.2 (with clocks applied)

MICBEN

0.5

BIASEN

0.3

BUFIOEN

VMIDSEL

ROUT1EN

LOUT1EN

BOOSTENL

INPPGAENL

ADCENL

0.1

5KΩ = >0.3, less than 0.1 for 75KΩ 300KΩ settings

0.4

0.2

2.6 (x64, ADCOSR=0)

4.9 ( x128, ADCOSR=1)

OUT4EN

OUT3EN

LOUT2EN

ROUT2EN

RMIXEN

LMIXEN

0.2

1mA from SPKVDD + 0.2mA from AVDD in 5V mode

0.2

DACENR

1.8 (x64, DACOSR=0)

1.9 (x128, DACOSR=1)

1.8 (x64, DACOSR=0)

1.9 (x128, DACOSR=1)

DACENL

Table 2 AVDD Supply Current (AVDD=3.3V)

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AUDIO PATHS OVERVIEW

Figure 1 WM8976 Audio Signal Paths

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SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

t_MCLKL

MCLK

t_MCLKH

t_MCLKY

Figure 2 System Clock Timing Requirements

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T_A= +25^oC

PARAMETER

SYMBOL

T_MCLKY

CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK=SYSCLK (=256fs)

MCLK input to PLL ^{Note 1}

81.38

20

ns

MCLK cycle time

MCLK duty cycle

T_MCLKDS

60:40

40:60

Note 1:

PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.

AUDIO INTERFACE TIMING – MASTER MODE

Figure 3 Digital Audio Data Timing – Master Mode (see Control Interface)

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Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T_A=+25^oC, Master Mode, fs=48kHz,

MCLK=256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

LRC propagation delay from BCLK falling edge

ADCDAT propagation delay from BCLK falling edge

DACDAT setup time to BCLK rising edge

DACDAT hold time from BCLK rising edge

t_DL

10

ns

t_DDA

t_DST

t_DHT

10

AUDIO INTERFACE TIMING – SLAVE MODE

Figure 4 Digital Audio Data Timing – Slave Mode

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T_A=+25^oC, Slave Mode, fs=48kHz,

MCLK= 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

t_BCY

t_BCH

t_BCL

t_LRSU

t_LRH

t_DH

50

20

10

ns

BCLK pulse width high

BCLK pulse width low

LRC set-up time to BCLK rising edge

LRC hold time from BCLK rising edge

DACDAT hold time from BCLK rising edge

DACDAT setup time to BCLK rising edge

ADCDAT propagation delay from BCLK falling edge

t_Ds

t_DD

10

Note:

BCLK period should always be greater than or equal to MCLK period.

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CONTROL INTERFACE TIMING – 3-WIRE MODE

Figure 5 Control Interface Timing – 3-Wire Serial Control Mode

Test Conditions

DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T_A=+25^oC, Slave Mode, fs=48kHz,

MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Program Register Input Information

SCLK rising edge to CSB rising edge

SCLK pulse cycle time

t_SCS

t_SCY

t_SCL

t_SCH

t_DSU

t_DHO

t_CSL

t_CSH

t_CSS

t_ps

80

200

80

40

0

ns

SCLK pulse width low

SCLK pulse width high

SDIN to SCLK set-up time

SCLK to SDIN hold time

CSB pulse width low

CSB pulse width high

CSB rising to SCLK rising

Pulse width of spikes that will be suppressed

5

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CONTROL INTERFACE TIMING – 2-WIRE MODE

t₃

t₅

SDIN

t₄

t₆

t₂

t₈

SCLK

t₇

t₁

t₉

Figure 6 Control Interface Timing – 2-Wire Serial Control Mode

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T_A=+25^oC, Slave Mode, fs=48kHz,

MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Program Register Input Information

SCLK Frequency

0

526

kHz

us

ns

SCLK Low Pulse-Width

SCLK High Pulse-Width

Hold Time (Start Condition)

Setup Time (Start Condition)

Data Setup Time

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

t_ps

1.3

600

100

SDIN, SCLK Rise Time

SDIN, SCLK Fall Time

300

Setup Time (Stop Condition)

Data Hold Time

600

0

900

5

Pulse width of spikes that will be suppressed

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DEVICE DESCRIPTION

INTRODUCTION

The WM8976 is a low power audio CODEC combining a high quality stereo audio DAC and mono

ADC, with flexible line and microphone input and output processing. Applications for this device

include multimedia phones, digital camcorders, and digital still cameras with record and playback

capability.

FEATURES

The chip offers great flexibility in use, and so can support many different modes of operation as

follows:

MICROPHONE INPUT

A microphone input is provided, allowing a microphone to be pseudo-differentially connected, with

user defined gain using internal resistors. The provision of the common mode input pin allows for

rejection of common mode noise on the microphone input (level depends on gain setting chosen). A

microphone bias is output from the chip which can be used to bias the microphone. The signal

routing can be configured to allow manual adjustment of mic level, or to allow the ALC loop to control

the level of mic signal that is transmitted.

Total gain through the microphone path of up to +55.25dB can be selected.

PGA AND ALC OPERATION

A programmable gain amplifier is provided in the input path to the ADC. This may be used manually

or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the

recording volume constant.

LINE INPUTS (AUXL, AUXR)

The inputs, AUXL and AUXR, can be used as a stereo line input or as an input for warning tones (or

‘beeps’) etc. The left input can be summed into the record path, along with the microphone preamp

output, so allowing for mixing of audio with ‘backing music’ etc as required.

ADC

The ADC uses a 24-bit delta sigma oversampling architecture to deliver optimum performance with

low power consumption.

HI-FI DAC

The hi-fi DAC provides high quality audio playback suitable for all portable audio hi-fi type

applications, including MP3 players and portable disc players of all types.

OUTPUT MIXERS

Flexible mixing is provided on the outputs of the device. A stereo mixer is provided for the stereo

headphone or line outputs, LOUT1/ROUT1, and additional summers on the OUT3/OUT4 outputs

allow for an optional differential or stereo line output on these pins. Gain adjustment PGAs are

provided for the LOUT1/ROUT1 and LOUT2/ROUT2 outputs, and signal switching is provided to

allow for all possible signal combinations. The output buffers can be configured in several ways,

allowing support of up to three sets of external transducers; ie stereo headphone, BTL speaker, and

BTL earpiece may be connected simultaneously. Thermal implications should be considered before

simultaneous full power operation of all outputs is attempted.

Alternatively, if a speaker output is not required, the LOUT2 and ROUT2 pins might be used as a

stereo headphone driver, (disable output invert buffer on ROUT2). In that case two sets of

headphones might be driven, or the LOUT2 and ROUT2 pins used as a line output driver.

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OUT3 and OUT4 can be configured to provide an additional stereo lineout from the output of the

DACs, the mixers or the input microphone boost stages. Alternatively OUT4 can be configured as a

mono mix of left and right DACs or mixers, or simply a buffered version of the chip midrail reference

voltage. OUT3 can also be configured as a buffered VMID output. This voltage may then be used as

a headphone ‘pseudo ground’ allowing removal of the large AC coupling capacitors often used in the

output path.

AUDIO INTERFACES

The WM8976 has a standard audio interface, to support the transmission of data to and from the

chip. This interface is a 3 wire standard audio interface which supports a number of audio data

formats including I2S, DSP/PCM Mode (a burst mode in which LRC sync plus 2 data packed words

are transmitted), MSB-First, left justified and MSB-First, right justified, and can operate in master or

slave modes.

CONTROL INTERFACES

To allow full software control over all features, the WM8976 offers a choice of 2 or 3 wire control

interface. It is fully compatible and an ideal partner for a wide range of industry standard

microprocessors, controllers and DSPs.

Selection between the modes is via the MODE pin. In 2 wire mode the address of the device is fixed

as 0011010.

CLOCKING SCHEMES

WM8976 offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to

the DAC and ADC.

A PLL is included which may be used to generate these clocks in the event that they are not

available from the system controller. This PLL uses an input clock, typically the 12MHz USB or ilink

clock, to generate high quality audio clocks. If this PLL is not required for generation of these clocks,

it can be reconfigured to generate alternative clocks which may then be output on the GPIO pins and

used elsewhere in the system.

POWER CONTROL

The design of the WM8976 has given much attention to power consumption without compromising

performance. It operates at very low voltages, and includes the ability to power off any unused parts

of the circuitry under software control, and includes standby and power off modes.

OPERATION SCENARIOS

Flexibility in the design of the WM8976 allows for a wide range of operational scenarios, some of

which are proposed below:

Multimedia phone; High quality playback to a stereo headset, a mono ear speaker or a loudspeaker

is supported, allowing Hi-Fi playback to be mixed with voice and other analogue inputs while

simultaneously transmitting a differential output from the microphone amplifier. A 5-band EQ enables

Hi-Fi playback to be customised to suit the user's preferences and the music style, while

programmable filtering allows fixed-frequency noise (e.g. 217Hz) to be reduced in the digital domain.

Camcorder; The provision of a microphone preamplifier allows support for both internal or external

microphones. All drivers for speaker, headphone and line output connections are integrated. The

selectable ‘application filters’ after the ADC provide for features such as ‘wind noise’ reduction, or

mechanical noise reducing filters.

Digital still camera recording; Support for digital recording is similar to the camcorder case. But

additionally if the DSC supports MP3 playback, and perhaps recording, the ability of the ADC to

support full 48ks/s high quality recording increases device flexibility.

AUXILIARY ANALOGUE INPUTS

An analogue stereo FM tuner or other auxiliary analogue input can be connected to the AUX inputs of

WM8976, and the stereo signal listened to via headphones.

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INPUT SIGNAL PATH

The WM8976 has flexible analogue inputs. An input PGA stage is followed by a boost/mix stage

which drives into the hi-fi ADC. The input path has three input pins which can be configured in a

variety of ways to accommodate single-ended or differential microphones. There is an auxiliary input

pin which can be fed into to the input boost/mix stage as well as driving into the output path. A

bypass path exists from the output of the boost/mix stage into the output left/right mixers.

MICROPHONE INPUTS

The WM8976 can accommodate a variety of microphone configurations including single ended and

differential inputs. The inputs to the differential input PGA are LIN, LIP and L2.

In single-ended microphone input configuration the microphone signal should be input to LIN and the

internal NOR gate configured to clamp the non-inverting input of the input PGA to VMID.

In differential mode the larger signal should be input to LIP or RIP and the smaller (e.g. noisy ground

connections) should be input to LIN or RIN.

Figure 7 Microphone Input PGA Circuit

The input PGA is enabled by the IPPGAENL/R register bits.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Input PGA enable

R2

2

INPPGAENL

0

Power

Management

2

0 = disabled

1 = enabled

Table 3 Input PGA Enable Register Settings

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R44

0

LIP2INPPGA

1

Connect LIP pin to input PGA amplifier

positive terminal.

Input

Control

0 = LIP not connected to input PGA

1 = input PGA amplifier positive terminal

connected to LIP (constant input

impedance)

1

2

LIN2INPPGA

L2_2INPPGA

1

0

Connect LIN pin to input PGA negative

terminal.

0=LIN not connected to input PGA

1=LIN connected to input PGA amplifier

negative terminal.

Connect L2 pin to input PGA positive

terminal.

0=L2 not connected to input PGA

1=L2 connected to input PGA amplifier

positive terminal (constant input

impedance).

Table 4 Input PGA Control

INPUT PGA VOLUME CONTROL

The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain

from the LIN input to the PGA output and from the L2 amplifier to the PGA output is always common

and controlled by the register bits INPPGAVOLL[5:0]. These register bits also affect the LIP pin

when LIP2INPPGA=1, the L2 pin when L2_2INPPGA=1 and the L2 pin when L2_2INPPGA=1.

When the Automatic Level Control (ALC) is enabled the input PGA gains are controlled

automatically and the INPPGAVOLL bits should not be used.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Input PGA volume

R45

5:0

INPPGAVOLL

010000

Input PGA

volume

control

000000 = -12dB

000001 = -11.25db

.

010000 = 0dB

.

111111 = 35.25dB

Mute control for input PGA:

6

7

INPPGAMUTEL

INPPGAZCL

0

0=Input PGA not muted, normal

operation

1=Input PGA muted (and disconnected

from the following input BOOST stage).

Input PGA zero cross enable:

0=Update gain when gain register

changes

1=Update gain on 1^stzero cross after

gain register write.

8

INPPGAUPDATE Not

latched

INPPGAVOLL volume does not update

until a 1 is written to INPPGAUPDATE

R32

ALCSEL

0

ALC function select:

0=ALC off

ALC control

1

1=ALC on

Table 5 Input PGA Volume Control

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AUXILLIARY INPUTS

There are two auxilliary inputs, AUXL and AUXR which can be used for a variety of purposes such

as stereo line inputs or as a ‘beep’ input signal to be mixed with the outputs.

The AUXL input can be used as a line input to the input BOOST stage which has gain adjust of -

12dB to +6dB in 3dB steps (plus off). See the INPUT BOOST section for further details.

The AUXL/R inputs can also be mixed into the output channel mixers, with a gain of -15dB to +6dB

plus off.

In addition the AUXR input can be summed into the Right speaker output path (ROUT2) with a gain

adjust of -15 to +6dB. This allows a ‘beep’ input to be output on the speaker outputs only without

affecting the headphone or lineout signals.

INPUT BOOST

The input PGA stage is followed by an input BOOST circuit. The input BOOST circuit has 3

selectable inputs: the input microphone PGA output, the AUX amplifier output and the L2 input pin

(can be used as a line input, bypassing the input PGA). These three inputs can be mixed together

and have individual gain boost/adjust as shown in Figure 8.

Figure 8 Input Boost Stage

The input PGA paths can have a +20dB boost (PGABOOSTL=1) , a 0dB pass through

(PGABOOSTL=0) or be completely isolated from the input boost circuit (INPPGAMUTEL=1).

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R47

8

PGABOOSTL

1

Boost enable for input PGA:

Input BOOST

control

0 = PGA output has +0dB gain

through input BOOST stage.

1 = PGA output has +20dB gain

through input BOOST stage.

Table 6 Input BOOST Stage Control

The Auxilliary amplifier path to the BOOST stage is controlled by the AUXL2BOOSTVOL[2:0]

register bits. When AUXL2BOOSTVOL=000 this path is completely disconnected from the BOOST

stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB.

The L2 path to the BOOST stage is controlled by the LIP2BOOSTVOL[2:0] register bits. When

L2_2BOOSTVOL=000 the L2 input pin is completely disconnected from the BOOST stage. Settings

001 through to 111 control the gain in 3dB steps from -12dB to +6dB.

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R47

2:0

AUXL2BOOSTVOL

000

Controls the auxilliary amplifer to

the input boost stage:

Input BOOST

control

000=Path disabled (disconnected)

001=-12dB gain through boost

stage

010=-9dB gain through boost

stage

…

111=+6dB gain through boost

stage

6:4

L2_2BOOSTVOL

000

Controls the L2 pin to the input

boost stage:

000=Path disabled (disconnected)

001=-12dB gain through boost

stage

010=-9dB gain through boost

stage

…

111=+6dB gain through boost

stage

Table 7 Input BOOST Stage Control

The BOOST stage is enabled under control of the BOOSTEN register bit.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2

4

BOOSTENL

0

Input BOOST enable

Power

management

2

0 = Boost stage OFF

1 = Boost stage ON

Table 8 Input BOOST Enable Control

MICROPHONE BIASING CIRCUIT

The MICBIAS output provides a low noise reference voltage suitable for biasing electret type

microphones and the associated external resistor biasing network. Refer to the Applications

Information section for recommended external components. The MICBIAS voltage can be altered via

the MBVSEL register bit.

When MBVSEL=0, MICBIAS=0.9*AVDD and when MBVSEL=1,

MICBIAS=0.65*AVDD. The output can be enabled or disabled using the MICBEN control bit.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Microphone Bias Enable

R1

4

MICBEN

0

Power

management 1

0 = OFF (high impedance output)

1 = ON

Table 9 Microphone Bias Enable Control

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R44

Input control

8

MBVSEL

0

Microphone Bias Voltage Control

0 = 0.9 * AVDD

1 = 0.65 * AVDD

Table 10 Microphone Bias Voltage Control

The internal MICBIAS circuitry is shown in Figure 9. Note that the maximum source current

capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit

the MICBIAS current to 3mA.

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MBVSEL=0

MICBIAS

= 1.8 x VMID

= 0.9 x AVDD

VMID

MB

internal

resistor

MBVSEL=1

MICBIAS

= 1.3 x VMID

= 0.65 x AVDD

internal

resistor

AGND

Figure 9 Microphone Bias Schematic

ANALOGUE TO DIGITAL CONVERTER (ADC)

The WM8976 uses a multi-bit, oversampled sigma-delta ADC. The use of multi-bit feedback and

high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale

input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0V_rms. Any

voltage greater than full scale may overload the ADC and cause distortion.

ADC DIGITAL FILTERS

The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data

from the ADC to the correct sampling frequency to be output on the digital audio interface. The

digital filter path for each ADC channel is illustrated in Figure 10.

Figure 10 ADC Digital Filter Path

The ADC is enabled by the ADCENL/R register bit.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Enable ADC:

R2

0

ADCENL

0

Power

management 2

0 = ADC disabled

1 = ADC enabled

Table 11 ADC Enable Control

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The polarity of the output signal can also be changed under software control using the ADCLPOL

register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR register bit.

With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when

ADCOSR=1 the oversample rate is 128x which gives best performance.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R14

ADC Control

0

ADCLPOL

0

ADC polarity adjust:

0=normal

1=inverted

3

ADCOSR

0

ADC oversample rate select:

0=64x (lower power)

1=128x (best performance)

Table 12 ADC Control

SELECTABLE HIGH PASS FILTER

A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two

modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off

frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off

frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown

in Table 14.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

High Pass Filter Enable

R14

ADC Control

8

7

HPFEN

1

0=disabled

1=enabled

HPFAPP

0

Select audio mode or application mode

0=Audio mode (1^storder, fc = ~3.7Hz)

1=Application mode (2^ndorder, fc =

HPFCUT)

6:4

Table 13 ADC Enable Control

HPFCUT

000

Application mode cut-off frequency

See Table 14 for details.

HPFCUT

[2:0]

SR=101/100

SR=011/010

fs (kHz)

22.05

SR=001/000

44.1

8

11.025

12

16

24

32

48

000

001

010

011

100

101

110

111

82

113

141

180

225

281

360

450

563

122

153

156

245

306

392

490

612

82

113

141

180

225

281

360

450

563

122

153

156

245

306

392

490

612

82

113

141

180

225

281

360

450

563

122

153

156

245

306

392

490

612

102

131

163

204

261

327

408

102

131

163

204

261

327

408

102

131

163

204

261

327

408

Table 14 High Pass Filter Cut-off Frequencies (HPFAPP=1). Values in Hz.

Note that the High Pass filter values (when HPFAPP=1) are calculated with the assumption that the

SR register bits are set correctly for the actual sample rate as shown in Table 14.

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PROGRAMMABLE NOTCH FILTER

A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth,

programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits

NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup

there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R27

0

6:0

NFA0[13:7]

NFEN

Notch Filter a0 coefficient, bits [13:7]

Notch filter enable:

Notch Filter 1

7

8

0=Disabled

1=Enabled

0

NFU

Notch filter update. The notch filter

values used internally only update

when one of the NFU bits is set high.

Notch Filter a0 coefficient, bits [6:0]

Notch filter update. The notch filter

values used internally only update

when one of the NFU bits is set high.

Notch Filter a1 coefficient, bits [13:7]

Notch filter update. The notch filter

values used internally only update

when one of the NFU bits is set high.

Notch Filter a1 coefficient, bits [6:0]

Notch filter update. The notch filter

values used internally only update

when one of the NFU bits is set high.

R28

0

6:0

8

NFA0[6:0]

NFU

Notch Filter 2

R29

0

6:0

8

NFA1[13:7]

NFU

Notch Filter 3

R30

0

0-6

8

NFA1[6:0]

NFU

Notch Filter 4

Table 15 Notch Filter Function

The coefficients are calculated as follows:

1− tan(w_b/ 2)

a₀=

1+ tan(w_b/ 2)

a₁= −(1+ a₀)cos(w₀)

Where:

w₀= 2πf_c/ f_s

w_b= 2πf_b/ f_s

f_c= centre frequency in Hz, f_b= -3dB bandwidth in Hz, f_s= sample frequency in Hz

The actual register values can be determined from the coefficients as follows:

NFA0 = -a0 x 2¹³

NFA1 = -a1 x 2¹²

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NOTCH FILTER WORKED EXAMPLE

The following example illustrates how to calculate the a0 and a1 coefficients for a desired centre

frequency and -3dB bandwidth.

fc = 1000 Hz

fb = 100 Hz

fs = 48000 Hz

w₀= 2πf_c/ f_s

w_b= 2πf_b/ f_s

2π

=

x (1000 / 48000) = 0.1308996939 rads

x (100 / 48000) = 0.01308996939 rads

1− tan(w_b/ 2)

1+ tan(w_b/ 2)

1− tan(0.01308996939/ 2)

a₀=

1+ tan(0.01308996939/ 2) _{= 0.9869949627}

=

a₁= −(1+ a₀)cos(w₀)

− (1+ 0.9869949627)cos(0.1308996939)

=

-

1.969995945

NFA0 = -a0 x 213 = -8085 (rounded to nearest whole number)

NFA1 = -a1 x 212 = 8069 (rounded to nearest whole number)

These values are then converted to a 14-bit sign / magnitude notation:

NFA0[13] = 1; NFA0[12:0] = 13’h1F95; NFA0 = 14’h3F95 = 14’b11111110010101

NFA1[13] = 0; NFA1[12:0] = 13’h1F85; NFA1 = 14’h1F85 = 14’b01111110000101

DIGITAL ADC VOLUME CONTROL

The output of the ADC can be digitally attenuated over a range from –127dB to 0dB in 0.5dB steps.

The gain for a given eight-bit code X is given by:

0.5 × (G-255) dB for 1 ≤ G ≤ 255;

MUTE for G = 0

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R15

7:0

ADCVOLL

[7:0]

11111111

( 0dB )

ADC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -127dB

0000 0010 = -126.5dB

... 0.5dB steps up to

ADC Digital

Volume

1111 1111 = 0dB

8

ADCVU

Not

latched

ADC volume does not update until a 1 is

written to ADCVU

Table 16 ADC Digital Volume Control

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INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)

The WM8976 has an automatic PGA gain control circuit, which can function as an input peak limiter

or as an automatic level control (ALC).

The Automatic Level Control (ALC) provides continuous adjustment of the input PGA in response to

the amplitude of the input signal. A digital peak detector monitors the input signal amplitude and

compares it to a register defined threshold level (ALCLVL).

If the signal is below the threshold, the ALC will increase the gain of the PGA at a rate set by

ALCDCY. If the signal is above the threshold, the ALC will reduce the gain of the PGA at a rate set

by ALCATK.

The ALC has two modes selected by the ALCMODE register: normal mode and peak limiter mode.

The ALC/limiter function is enabled by setting the register bit R32[8] ALCSEL.

REGISTER

ADDRESS

BIT

LABEL

ALCMIN

DEFAULT

DESCRIPTION

R32 (20h)

2:0

000 (-12dB)

Set minimum gain of PGA

000 = -12dB

ALC Control

1

[2:0]

001 = -6dB

010 = 0dB

011 = +6dB

100 = +12dB

101 = +18dB

110 = +24dB

111 = +30dB

5:3

ALCMAX

[2:0]

111

(+35.25dB)

Set Maximum Gain of PGA

111 = +35.25dB

110 = +29.25dB

101 = +23.25dB

100 = +17.25dB

011 = +11.25dB

010 = +5.25dB

001 = -0.75dB

000 = -6.75dB

8:7

3:0

ALCSEL

00

ALC function select

00 = ALC disabled

01 = Right channel ALC enabled

10 = Left channel ALC enabled

11 = Both channels ALC enabled

R33 (21h)

ALCLVL

[3:0]

1011

ALC target – sets signal level at ADC

input

ALC Control

2

(-6dB)

1111 = -1.5dBFS

1110 = -1.5dBFS

1101 = -3dBFS

1100 = -4.5dBFS

1011 = -6dBFS

1010 = -7.5dBFS

1001 = -9dBFS

1000 = -10.5dBFS

0111 = -12dBFS

0110 = -13.5dBFS

0101 = -15dBFS

0100 = -16.5dBFS

0011 = -18dBFS

0010 = -19.5dBFS

0001 = -21dBFS

0000 = -22.5dBFS

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REGISTER

ADDRESS

BIT

LABEL

ALCZC

DEFAULT

DESCRIPTION

8

0 (zero

cross off)

ALC uses zero cross detection circuit.

0 = Disabled (recommended)

1 = Enabled

7:4

ALCHLD

[3:0]

0000

ALC hold time before gain is

increased.

(0ms)

0000 = 0ms

0001 = 2.67ms

0010 = 5.33ms

0011 = 10.66ms

0100 = 21.32ms

0101 = 42.64ms

0110 = 85.28ms

0111 = 0.17s

1000 = 0.34s

1001 = 0.68s

1010 or higher = 1.36s

R34 (22h)

8

ALCMODE

0

Determines the ALC mode of

operation:

ALC Control

3

0 = ALC mode (Normal Operation)

1 = Limiter mode.

7:4

ALCDCY

[3:0]

0011

Decay (gain ramp-up) time

(ALCMODE ==0)

(26ms/6dB)

Per

step

Per

6dB

90% of

range

0000

0001

0010

410us

820us

1.64ms

3.38ms

6.56ms

13.1ms

23.6ms

47.2ms

94.5ms

… (time doubles with every step)

1010

or

420ms

3.36s

24.2s

higher

0011

Decay (gain ramp-up) time

(ALCMODE ==1)

(5.8ms/6dB)

Per

step

Per

6dB

90% of

range

0000

0001

0010

90.8us

182us

363us

726us

5.23ms

10.5ms

20.9ms

1.45ms

2.91ms

… (time doubles with every step)

1010 93ms 744ms 5.36s

3:0

ALCATK

[3:0]

0010

ALC attack (gain ramp-down) time

(ALCMODE == 0)

(3.3ms/6dB)

Per

step

Per

6dB

90% of

range

0000

0001

0010

104us

208us

416us

832us

1.66ms

3.33ms

6ms

12ms

24ms

… (time doubles with every step)

1010

or

106ms

852ms

6.13s

higher

0010

ALC attack (gain ramp-down) time

(ALCMODE == 1)

(726us/6dB)

Per

step

Per

6dB

90% of

range

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000

0001

0010

22.7us 182.4us 1.31ms

45.4us

90.8us

363us

726us

2.62ms

5.23ms

… (time doubles with every step)

1010

or

23.2ms

186ms 1.34s

higher

Table 17 ALC Control Registers

When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input

gain update must be made by writing to the INPPGAVOLL/R register bits.

NORMAL MODE

In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing

the gain of the PGA. The following diagram shows an example of this.

Figure 11 ALC Normal Mode Operation

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LIMITER MODE

In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the

PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is

enabled in limiter mode. If the ALC is started in limiter mode, this is the gain setting of the PGA at

start-up. If the ALC is switched into limiter mode after running in ALC mode, the starting gain will be

the gain at switchover. The diagram below shows an example of limiter mode.

Figure 12 ALC Limiter Mode Operation

ATTACK AND DECAY TIMES

The attack and decay times set the update times for the PGA gain. The attack time is the time

constant used when the gain is reducing. The decay time is the time constant used when the gain is

increasing. In limiter mode, the time constants are faster than in ALC mode. The time constants

are shown below in terms of a single gain step, a change of 6dB and a change of 90% of the PGAs

gain range.

Note that, these times will vary slightly depending on the sample rate used (specified by the SR

register).

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NORMAL MODE

ALCMODE = 0 (Normal Mode)

Attack Time (s)

t_ATK6dB

t_ATK

t_ATK90%

ALCATK

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

104µs

208µs

416µs

832µs

1.66ms

3.33ms

6.66ms

13.3ms

26.6ms

53.2ms

106ms

213.2ms

426ms

852ms

6ms

12ms

24ms

48ms

96ms

192ms

384ms

767ms

1.53s

3.07s

6.13s

832µs

1.66ms

3.33ms

6.66ms

13.3ms

26.6ms

53.2ms

106ms

ALCMODE = 0 (Normal Mode)

Decay Time (s)

t_DCY6dB

t_DCY

t_DCY90%

ALCDCY

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

410µs

820µs

3.28ms

6.56ms

13.1ms

26.2ms

52.5ms

105ms

210ms

420ms

840ms

1.68s

23.6ms

47.2ms

94.5ms

189ms

378ms

756ms

1.51s

3.02s

6.05s

12.1s

24.2s

1.64ms

3.28ms

6.56ms

13.1ms

26.2ms

52.5ms

105ms

210ms

420ms

3.36s

Table 18 ALC Normal Mode (Attack and Decay times)

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LIMITER MODE

ALCMODE = 1 (Limiter Mode)

Attack Time (s)

t_ATKLIM6dB

t_ATKLIM

22.7µs

t_ATKLIM90%

1.31ms

ALCATK

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

182µs

363µs

726µs

1.45ms

2.91ms

5.81ms

11.6ms

23.2ms

46.5ms

93ms

45.4µS

90.8µS

182µS

363µS

726µS

1.45ms

2.9ms

5.81ms

11.6ms

23.2ms

2.62ms

5.23ms

10.5ms

20.9ms

41.8ms

83.7ms

167ms

335ms

669ms

1.34s

186ms

ALCMODE = 1 (Limiter Mode)

Attack Time (s)

t_DCYLIM6dB

t_DCYLIM

90.8µs

t_DCYLIM90%

ALCDCY

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

726µs

1.45ms

2.91ms

5.81ms

11.6ms

23.2ms

46.5ms

93ms

5.23ms

10.5ms

20.9ms

41.8ms

83.7ms

167ms

335ms

669ms

1.34s

182µS

363µS

726µS

1.45ms

2.91ms

5.81ms

11.6ms

23.2ms

46.5ms

93ms

186ms

372ms

744ms

2.68s

5.36s

Table 19 ALC Limiter Mode (Attack and Decay times)

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MINIMUM AND MAXIMUM GAIN

The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be

set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R32

5:3

2:0

ALCMAX

ALCMIN

111

000

Set Maximum Gain of PGA

Set minimum gain of PGA

ALC Control

1

Table 20 ALC Max/Min Gain

In normal mode, ALCMAX sets the maximum boost which can be applied to the signal. In limiter

mode, ALCMAX will normally have no effect (assuming the starting gain value is less than the

maximum gain specified by ALCMAX) because the maximum gain is set at the starting gain level.

ALCMIN sets the minimum gain value which can be applied to the signal.

Figure 13 ALC Min/Max Gain

ALCMAX

111

110

101

100

Maximum Gain (dB)

35.25

29.25

23.25

17.25

11.25

5.25

011

010

001

000

-0.75

-6.75

Table 21 ALC Max Gain Values

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ALCMIN

000

001

Minimum Gain (dB)

-12

-6

010

0

011

6

100

101

110

111

12

18

24

30

Table 22 ALC Min Gain Values

Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC

outside of the range or changing the ALCMAX or ALCMIN settings during operation, the ALC will

immediately adjust the gain to return to the ALC operating range. It is recommended that the ALC

starting gain is set between the ALCMAX and ALCMIN limits.

ALC HOLD TIME (NORMAL MODE ONLY)

In Normal mode, the ALC has an adjustable hold time which sets a time delay before the ALC

begins its decay phase (gain increasing). The hold time is set by the ALCHLD register.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R33

7:4

ALCHLD

0000

ALC hold time before gain is increased.

ALC Control

2

Table 23 ALC Hold Time

If the hold time is exceeded this indicates that the signal has reached a new average level and the

ALC will increase the gain to adjust for that new average level. If the signal goes above the

threshold during the hold period, the hold phase is abandoned and the ALC returns to normal

operation.

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Figure 14 ALCLVL

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Figure 15 ALC Hold Time

t_HOLD(s)

ALCHLD

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

0

2.67ms

5.34ms

10.7ms

21.4ms

42.7ms

85.4ms

171ms

342ms

684ms

1.37s

Table 24 ALC Hold Time Values

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PEAK LIMITER

To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a

limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is

ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls

below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.

Note: If ALCATK = 0000, then the limiter makes no difference to the operation of the ALC. It is

designed to prevent clipping when long attack times are used.

NOISE GATE (NORMAL MODE ONLY)

When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise

pumping”, i.e. loud hissing noise during silence periods. The WM8976 has a noise gate function that

prevents noise pumping by comparing the signal level at the input pins against a noise gate

threshold, NGTH. The noise gate cuts in when:

Signal level at ADC [dBFS] < NGTH [dBFS] + PGA gain [dB] + Mic Boost gain [dB]

This is equivalent to:

Signal level at input pin [dBFS] < NGTH [dBFS]

The PGA gain is then held constant (preventing it from ramping up as it normally would when the

signal is quiet).

The table below summarises the noise gate control register. The NGTH control bits set the noise

gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps.

Levels at the extremes of the range may cause inappropriate operation, so care should be taken with

set–up of the function. The noise gate only operates in conjunction with the ALC and cannot be used

in limiter mode.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

000

DESCRIPTION

R35 (23h)

2:0 NGTH

Noise gate threshold:

ALC Noise Gate

Control

000 = -39dB

001 = -45dB

010 = -51db

011 = -57dB

100 = -63dB

101 = -69dB

110 = -75dB

111 = -81dB

Noise gate function enable

1 = enable

3

NGATEN

0

0 = disable

Table 25 ALC Noise Gate Control

The diagrams below show the response of the system to the same signal with and without noise

gate.

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Figure 16 ALC Operation Above Noise Gate Threshold

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Figure 17 Noise Gate Operation

OUTPUT SIGNAL PATH

The WM8976 output signal paths consist of digital application filters, up-sampling filters, stereo Hi-Fi

DACs, analogue mixers, speaker, stereo headphone and stereo line/mono/midrail output drivers.

The digital filters and DAC are enabled by register bits DACENL And DACENR. The mixers and

output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is

possible to utilise the analogue mixing and amplification provided by the WM8976, irrespective of

whether the DACs are enabled or not.

The WM8976 DACs receive digital input data on the DACDAT pin. The digital filter block processes

the data to provide the following functions:

§

Digital volume control

Graphic equaliser

Digital peak limiter.

Sigma-Delta Modulation

High performance sigma-delta 24-bit audio DAC converts the digital data into an analogue signal.

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Figure 18 DAC Digital Filter Path

The analogue outputs from the DACs can then be mixed with the aux analogue inputs and the ADC

analogue inputs. The mix is fed to the output drivers for headphone (LOUT1/ROUT1), speaker

(LOUT2/ROUT2) or line (OUT3/OUT4). OUT3 and OUT4 have additional mixers which allow them

to output different signals to the headphone and speaker outputs.

DIGITAL PLAYBACK (DAC) PATH

Digital data is passed to the WM8976 via the flexible audio interface and is then passed through a

variety of advanced digital filters (as shown in Figure 18) to the hi-fi DACs. The DACs are enabled

by the DACENL/R register bits.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3

0

DACENL

0

Left channel DAC enable

0 = DAC disabled

Power

Management 3

1 = DAC enabled

1

DACENR

0

Right channel DAC enable

0 = DAC disabled

1 = DAC enabled

Table 26 DAC Enable Control

The WM8976 also has a Soft Mute function, which, when enabled, gradually attenuates the volume

of the digital signal to zero. When disabled, the gain will ramp back up to the digital gain setting. This

function is enabled by default. To play back an audio signal, this function must first be disabled by

setting the SOFTMUTE bit to zero.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R10

DAC Control

0

DACPOLL

0

Left DAC output polarity:

0 = non-inverted

1 = inverted (180 degrees phase shift)

Right DAC output polarity:

0 = non-inverted

1

2

3

6

DACPOLR

AMUTE

0

1 = inverted (180 degrees phase shift)

Automute enable

0 = Amute disabled

1 = Amute enabled

DACOSR

SOFTMUTE

DAC oversampling rate:

0=64x (lowest power)

1=128x (best performance)

Softmute enable:

0=Enabled

1=Disabled

Table 27 DAC Control Register

The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital

interpolation filters. The bitstream data enters the multi-bit, sigma-delta DACs, which convert it to a

high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and

sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and

low distortion.

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The DAC output phase defaults to non-inverted. Setting DACPOLL will invert the DAC output phase

on the left channel and DACPOLR inverts the phase on the right channel.

AUTO-MUTE

The DAC has an auto-mute function which applies an analogue mute when 1024 consecutive zeros

are detected. The mute is released as soon as a non-zero sample is detected. Automute can be

disabled using the AMUTE control bit.

DIGITAL HI-FI DAC VOLUME (GAIN) CONTROL

The signal volume from each Hi-Fi DAC can be controlled digitally. The gain and attenuation range

is –127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by:

0.5 × (X-255) dB for 1 ≤ X ≤ 255;

MUTE for X = 0

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R11

7:0

DACVOLL

[7:0]

11111111

( 0dB )

Left DAC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -127dB

Left DAC

Digital Volume

0000 0010 = -126.5dB

... 0.5dB steps up to

1111 1111 = 0dB

8

DACVU

Not

latched

DAC left and DAC right volume do

not update until a 1 is written to

DACVU (in reg 11 or 12)

R12

7:0

DACVOLR

[7:0]

11111111

( 0dB )

Right DAC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -127dB

Right DAC

Digital Volume

0000 0010 = -126.5dB

... 0.5dB steps up to

1111 1111 = 0dB

8

DACVU

Not

latched

DAC left and DAC right volume do

not update until a 1 is written to

DACVU (in reg 11 or 12)

Table 28 DAC Digital Volume Control

Note: An additional gain of up to +12dB can be added using the gain block embedded in the

digital peak limiter circuit (see DAC OUTPUT LIMITER section).

5-BAND EQUALISER

A 5-band graphic equaliser function which can be used to change the output frequency levels to suit

the environment. This can be applied to the ADC or DAC path and is described in the 5-BAND

EQUALISER section for further details on this feature.

3-D ENHANCEMENT

The WM8976 has an advanced digital 3-D enhancement feature which can be used to vary the

perceived stereo separation of the left and right channels. See the 3-D STEREO ENHANCEMENT

section for further details on this feature.

DAC DIGITAL OUTPUT LIMITER

The WM8976 has a digital output limiter function. The operation of this is shown in Figure 19. In

this diagram the upper graph shows the envelope of the input/output signals and the lower graph

shows the gain characteristic.

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Figure 19 DAC Digital Limiter Operation

The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 19, in

normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the

limiter. Signals above the upper threshold are attenuated at a specific attack rate (set by the

LIMATK register bits) until the signal falls below the threshold. The limiter also has a lower threshold

1dB below the upper threshold. When the signal falls below the lower threshold the signal is

amplified at a specific decay rate (controlled by LIMDCY register bits) until a gain of 0dB is reached.

Both threshold levels are controlled by the LIMLVL register bits. The upper threshold is 0.5dB above

the value programmed by LIMLVL and the lower threshold is 0.5dB below the LIMLVL value.

VOLUME BOOST

The limiter has programmable upper gain which boosts signals below the threshold to compress the

dynamic range of the signal and increase its perceived loudness. This operates as an ALC function

with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the

LIMBOOST register bits.

The output limiter volume boost can also be used as a stand alone digital gain boost when the limiter

is disabled.

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REGISTER

ADDRESS

BIT

LABEL

LIMATK

DEFAULT

DESCRIPTION

R24

3:0

0010

Limiter Attack time (per 6dB gain

change) for 44.1kHz sampling. Note

that these will scale proportionally with

sample rate.

DAC digital

limiter control

1

0000=94us

0001=188s

0010=375us

0011=750us

0100=1.5ms

0101=3ms

0110=6ms

0111=12ms

1000=24ms

1001=48ms

1010=96ms

1011 to 1111=192ms

7:4

LIMDCY

0011

Limiter Decay time (per 6dB gain

change) for 44.1kHz sampling. Note

that these will scale proportionally with

sample rate:

0000=750us

0001=1.5ms

0010=3ms

0011=6ms

0100=12ms

0101=24ms

0110=48ms

0111=96ms

1000=192ms

1001=384ms

1010=768ms

1011 to 1111=1.536s

Enable the DAC digital limiter:

0=disabled

8

LIMEN

0

1=enabled

R25

3:0

LIMBOOST

0000

Limiter volume boost (can be used as a

stand alone volume boost when

LIMEN=0):

DAC digital

limiter control

2

0000=0dB

0001=+1dB

0010=+2dB

… (1dB steps)

1011=+11dB

1100=+12dB

1101 to 1111=reserved

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Programmable signal threshold level

6:4

LIMLVL

000

(determines level at which the limiter

starts to operate)

000=-1dB

001=-2dB

010=-3dB

011=-4dB

100=-5dB

101 to 111=-6dB

Table 29 DAC Digital Limiter Control

5-BAND GRAPHIC EQUALISER

A 5-band graphic equaliser (EQ) is provided, which can be applied to the ADC or DAC path, together

with 3D enhancement, under control of the EQ3DMODE register bit.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R18

EQ Control 1

8

EQ3DMODE

1

0 = Equaliser applied to ADC path

1 = Equaliser and 3D Enhancement

applied to DAC path

Table 30 EQ and 3D Enhancement DAC or ADC Path Select

The equaliser consists of low and high frequency shelving filters (Band 1 and 5) and three peak

filters for the centre bands. Each has adjustable cut-off or centre frequency, and selectable boost

(+/- 12dB in 1dB steps). The peak filters have selectable bandwidth.

REGISTER

ADDRESS

BIT

LABEL

EQ1G

EQ1C

DEFAULT

DESCRIPTION

R18

4:0

01100

(0dB)

01

Band 1 Gain Control. See Table 36 for

details.

EQ Band 1

Control

6:5

Band 1 Cut-off Frequency:

00=80Hz

01=105Hz

10=135Hz

11=175Hz

Table 31 EQ Band 1 Control

REGISTER

ADDRESS

BIT

LABEL

EQ2G

DEFAULT

DESCRIPTION

R19

4:0

01100

(0dB)

01

Band 2 Gain Control. See Table 36 for

details.

EQ Band 2

Control

6:5

EQ2C

Band 2 Centre Frequency:

00=230Hz

01=300Hz

10=385Hz

11=500Hz

8

EQ2BW

0

Band 2 Bandwidth Control

0=narrow bandwidth

1=wide bandwidth

Table 32 EQ Band 2 Control

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REGISTER

ADDRESS

BIT

LABEL

EQ3G

DEFAULT

DESCRIPTION

R20

4:0

01100

(0dB)

01

Band 3 Gain Control. See Table 36 for

details.

EQ Band 3

Control

6:5

EQ3C

Band 3 Centre Frequency:

00=650Hz

01=850Hz

10=1.1kHz

11=1.4kHz

8

EQ3BW

0

Band 3 Bandwidth Control

0=narrow bandwidth

1=wide bandwidth

Table 33 EQ Band 3 Control

REGISTER

ADDRESS

BIT

LABEL

EQ4G

DEFAULT

DESCRIPTION

R21

4:0

01100

(0dB)

01

Band 4 Gain Control. See Table 36 for

details

EQ Band 4

Control

6:5

EQ4C

Band 4 Centre Frequency:

00=1.8kHz

01=2.4kHz

10=3.2kHz

11=4.1kHz

8

EQ4BW

0

Band 4 Bandwidth Control

0=narrow bandwidth

1=wide bandwidth

Table 34 EQ Band 4 Control

REGISTER

ADDRESS

BIT

LABEL

EQ5G

EQ5C

DEFAULT

DESCRIPTION

R22

4:0

01100

(0dB)

01

Band 5 Gain Control. See Table 36 for

details.

EQ Band 5

Gain Control

6:5

Band 5 Cut-off Frequency:

00=5.3kHz

01=6.9kHz

10=9kHz

11=11.7kHz

Table 35 EQ Band 5 Control

GAIN REGISTER

GAIN

+12dB

+11dB

+10dB

00000

00001

00010

…. (1dB steps)

01100

0dB

-1dB

01101

11000

-12dB

11001 to 11111

Table 36 Gain Register Table

Reserved

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3D STEREO ENHANCEMENT

The WM8976 has a digital 3D enhancement option to increase the perceived separation between the

left and right channels. Selection of 3D for playback is controlled by register bit EQ3DMODE.

Switching this bit from record to playback or from playback to record may only be done when ADC

and DAC are disabled. The WM8976 control interface will only allow EQ3DMODE to be changed

when ADC and DAC are disabled (ie ADCENL = 0, ADCENR = 0, DACENL = 0 and DACENR = 0).

The DEPTH3D setting controls the degree of stereo expansion.

When 3D enhancement is used, it may be necessary to attenuate the signal by 6dB to avoid limiting.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Stereo depth

R41 (29h)

3D

3:0

DEPTH3D[3:0]

0000

0000: 0% (minimum 3D effect)

0001: 6.67%

....

1110: 93.3%

1111: 100% (maximum 3D effect)

Table 37 3D Stereo Enhancement Function

ANALOGUE OUTPUTS

The WM8976 has three sets of stereo analogue outputs. These are:

•

LOUT1 and ROUT1 which are normally used to drive a headphone load.

LOUT2 and ROUT2 – normally used to drive an 8ꢀ BTL speaker.

OUT3 and OUT4 – can be configured as a stereo line out (OUT3 is left output and

OUT4 is right output). OUT4 can also be used to provide a mono mix of left and right

channels.

LOUT2, ROUT2, OUT3 and OUT4 are supplied from SPKVDD and are capable of driving up to

1.5Vrms signals as shown in Figure 20. LOUT1 and ROUT1 are supplied from AVDD and can only

drive out a 1V rms signal (AVDD/3.3).

LOUT1, ROUT1, LOUT2 and ROUT2 have individual analogue volume PGAs with -57dB to +6dB

ranges.

There are four output mixers in the output signal path, the left and right channel mixers which control

the signals to speaker, headphone (and optionally the line outputs) and also dedicated OUT3 and

OUT4 mixers.

LEFT AND RIGHT OUTPUT CHANNEL MIXERS

The left and right output channel mixers are shown in Figure 20. These mixers allow the AUX

inputs, the ADC bypass and the DAC left and right channels to be combined as desired. This

allows a mono mix of the DAC channels to be done as well as mixing in external line-in from the

AUX or speech from the input bypass path.

The AUX and bypass inputs have individual volume control from -15dB to +6dB and the DAC volume

can be adjusted in the digital domain if required. The output of these mixers is connected to both

the headphone (LOUT1 and ROUT1) and speaker (LOUT2 and ROUT2) and can optionally be

connected to the OUT3 and OUT4 mixers.

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Figure 20 Left/Right Output Channel Mixers

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R49

5

DACR2LMIX

0

Right DAC output to left output

mixer

Output mixer

control

0 = not selected

1 = selected

6

0

1

DACL2RMIX

DACL2LMIX

BYPL2LMIX

0

1

0

Left DAC output to right output mixer

0 = not selected

1 = selected

R50

Left DAC output to left output mixer

0 = not selected

Left channel

output mixer

control

1 = selected

Bypass path (from the input boost

output) to left output mixer

0 = not selected

1 = selected

4:2

BYPLMIXVOL

000

Bypass volume contol to output

channel mixer:

000 = -15dB

001 = -12dB

…

101 = 0dB

110 = +3dB

111 = +6dB

5

AUXL2LMIX

0

Left Auxilliary input to left channel

output mixer:

0 = not selected

1 = selected

8:6

AUXLMIXVOL

000

Aux left channel input to left mixer

volume control:

000 = -15dB

001 = -12dB

…

101 = 0dB

110 = +3dB

111 = +6dB

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R51

0

DACR2RMIX

1

Right DAC output to right output

mixer

Right channel

output mixer

control

0 = not selected

1 = selected

4:2

BYPRMIXVOL

000

Right bypass volume control to

output channel mixer:

000 = -15dB

001 = -12dB

…

101 = 0dB

110 = +3dB

111 = +6dB

5

AUXR2RMIX

0

Right Auxiliary input to right channel

output mixer:

0 = not selected

1 = selected

8:6

AUXRMIXVOL

000

Aux right channel input to right mixer

volume control:

000 = -15dB

001 = -12dB

…

101 = 0dB

110 = +3dB

111 = +6dB

R3

2

3

LMIXEN

RMIXEN

0

Left output channel mixer enable:

0 = disabled

Power

management

3

1= enabled

Right output channel mixer enable:

0 = disabled

1 = enabled

Table 38 Left and Right Output Mixer Control

HEADPHONE OUTPUTS (LOUT1 AND ROUT1)

The headphone outputs, LOUT1 and ROUT1 can drive a 16Ω or 32Ω headphone load, either

through DC blocking capacitors, or DC coupled without any capacitor. Each headphone output has

an analogue volume control PGA with a gain range of -57dB to +6dB as shown in Figure 23.

Figure 21 Headphone Outputs LOUT1 and ROUT1

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DESCRIPTION

REGISTER

ADDRESS

BIT

LABEL

LOUT1ZC

DEFAULT

R52

7

0

Headphone volume zero cross

enable:

LOUT1

1 = Change gain on zero cross only

0 = Change gain immediately

Left headphone output mute:

0 = Normal operation

1 = Mute

Volume

control

6

LOUT1MUTE

LOUT1VOL

0

5:0

111001

Left headphone output volume:

000000 = -57dB

...

111001 = 0dB

...

111111 = +6dB

8

7

HPVU

Not latched LOUT1 and ROUT1 volumes do not

update until a 1 is written to HPVU

(in reg 52 or 53)

R53

ROUT1ZC

0

Headphone volume zero cross

enable:

ROUT1

Volume

control

1 = Change gain on zero cross only

0 = Change gain immediately

Right headphone output mute:

0 = Normal operation

1 = Mute

6

ROUT1MUTE

ROUT1VOL

0

5:0

111001

Right headphone output volume:

000000 = -57dB

...

111001 = 0dB

...

111111 = +6dB

8

HPVU

Not latched LOUT1 and ROUT1 volumes do not

update until a 1 is written to HPVU

(in reg 52 or 53)

Table 39 OUT1 Volume Control

Headphone Output using DC Blocking Capacitors:

DC Coupled Headphone Output:

Figure 22 Recommended Headphone Output Configurations

When DC blocking capacitors are used, then their capacitance and the load resistance together

determine the lower cut-off frequency, f_c. Increasing the capacitance lowers f_c, improving the bass

response. Smaller capacitance values will diminish the bass response. Assuming a 16Ω load and

C1, C2 = 220µF:

f_c= 1 / 2π R_LC₁= 1 / (2π x 16Ω x 220µF) = 45 Hz

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In the DC coupled configuration, the headphone “ground” is connected to the VMID pin. The

OUT3/4 pins can be configured as a DC output driver by setting the OUT3MUTE and OUT4MUTE

register bit. The DC voltage on VMID in this configuration is equal to the DC offset on the LOUT1

and ROUT1 pins therefore no DC blocking capacitors are required. This saves space and material

cost in portable applications.

Note that OUT3 and OUT4 have an optional output boost of 1.5x. When these are configured in this

output boost mode (OUT3BOOST/OUT4BOOST=1) then the VMID value of these outputs will be

equal to 1.5xAVDD/2 and will not match the VMID of the headphone drivers. Do not use the DC

coupled output mode in this configuration.

It is recommended to connect the DC coupled outputs only to headphones, and not to the line input

of another device. Although the built-in short circuit protection will prevent any damage to the

headphone outputs, such a connection may be noisy, and may not function properly if the other

device is grounded.

SPEAKER OUTPUTS (LOUT2 AND ROUT2)

The outputs LOUT2 and ROUT2 are designed to drive an 8ꢀ BTL speaker but can optionally drive

two headphone loads of 16Ω/32Ω or a line output (see Headphone Output and Line Output sections,

respectively). Each output has an individual volume control PGA, an output boost/level shift bit, a

mute and an enable as shown in Figure 23. LOUT2 and ROUT2 output the left and right channel

mixer outputs respectively.

The ROUT2 signal path also has an optional invert. The amplifier used for this invert can be used to

mix in the AUXR signal with an adjustable gain range of -15dB -> +6dB. This allows a ‘beep’ signal

to be applied only to the speaker output without affecting the HP or line outputs.

Figure 23 Speaker Outputs LOUT2 and ROUT2

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REGISTER

ADDRESS

BIT

LABEL

LOUT2ZC

DEFAULT

DESCRIPTION

R54

7

0

Speaker volume zero cross enable:

1 = Change gain on zero cross only

0 = Change gain immediately

Left speaker output mute:

0 = Normal operation

1 = Mute

LOUT2 (SPK)

Volume

control

6

LOUT2MUTE

LOUT2VOL

0

5:0

111001

Left speaker output volume:

000000 = -57dB

...

111001 = 0dB

...

111111 = +6dB

8

7

SPKVU

Not latched LOUT2 and ROUT2 volumes do not

update until a 1 is written to SPKVU

(in reg 54 or 55)

R55

ROUT2ZC

0

Speaker volume zero cross enable:

1 = Change gain on zero cross only

0 = Change gain immediately

Right speaker output mute:

0 = Normal operation

1 = Mute

ROUT2 (SPK)

Volume

control

6

ROUT2MUTE

ROUT2VOL

0

5:0

111001

Right speaker output volume:

000000 = -57dB

...

111001 = 0dB

...

111111 = +6dB

8

SPKVU

Not latched LOUT2 and ROUT2 volumes do not

update until a 1 is written to SPKVU

(in reg 54 or 55)

Table 40 Speaker Volume Control

The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any

combination of the DAC output, the Bypass path (output of the input boost stage) and the AUX input.

The LOUT2/ROUT2 volume is controlled by the LOUT2VOL/ ROUT2VOL register bits. Gains over

0dB may cause clipping if the signal is large. The LOUT2MUTE/ ROUT2MUTE register bits cause

the speaker outputs to be muted (the output DC level is driven out). The output pins remain at the

same DC level (DCOP), so that no click noise is produced when muting or un-muting

The speaker output stages also have a selectable gain boost of 1.5x (3.52dB). When this boost is

enabled the output DC level is also level shifted (from AVDD/2 to 1.5xAVDD/2) to prevent the signal

from clipping. A dedicated amplifier BUFDCOP, as shown in Figure 23, is used to perform the DC

level shift operation. This buffer must be enabled using the BUFDCOPEN register bit for this

operating mode. It should also be noted that if SPKVDD is not equal to or greater than 1.5xAVDD

this boost mode may result in signals clipping. Table 42 summarises the effect of the SPKBOOST

control bits.

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0 = speaker gain = -1;

R49

2

SPKBOOST

0

Output control

DC = AVDD / 2

1 = speaker gain = +1.5;

DC = 1.5 x AVDD / 2

R1

8

BUFDCOPEN

0

Dedicated buffer for DC level shifting

output stages when in 1.5x gain

boost configuration.

Power

management

1

0=Buffer disabled

1=Buffer enabled (required for 1.5x

gain boost)

Table 41 Speaker Boost Stage Control

SPKBOOST

OUTPUT

STAGE GAIN

OUTPUT DC

LEVEL

OUTPUT STAGE

CONFIGURATION

0

1

1x (0dB)

AVDD/2

Inverting

1.5x (3.52dB)

1.5xAVDD/2

Non-inverting

Table 42 Output Boost Stage Details

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R43

Beep control

5

MUTERPGA2INV

INVROUT2

0

Mute input to INVROUT2 mixer

Invert ROUT2 output

AUXR input to ROUT2 inverter gain

000 = -15dB

4

3:1

BEEPVOL

000

...

111 = +6dB

0

BEEPEN

0

0 = mute AUXR beep input

1 = enable AUXR beep input

Table 43 AUXR – ROUT2 BEEP Mixer Function

ZERO CROSS TIMEOUT

A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output

PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This

is enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital

and is equal to 2²¹* input clock period.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7

0

SLOWCLKEN

0

Slow clock enable. Used for both the

jack insert detect debounce circuit and

the zero cross timeout.

Additional

Control

0 = slow clock disabled

1 = slow clock enabled

Table 44 Timeout Clock Enable Control

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OUT3/OUT4 MIXERS AND OUTPUT STAGES

The OUT3/OUT4 pins can provide an additional stereo line output, a mono output, or a pseudo

ground connection for headphones. There is a dedicated analogue mixer for OUT3 and one for

OUT4 as shown in Figure 24.

The OUT3 and OUT4 output stages are powered from SPKVDD and SPKGND. The individually

controllable outputs also incorporate an optional 1.5x boost and level shifting stage.

Figure 24 OUT3 and OUT4 Mixers

OUT3 can provide a buffered midrail headphone pseudo-ground, or a left line output.

OUT4 can provide a buffered midrail headphone pseudo-ground, a right line output, or a mono mix

output.

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R56

6

OUT3MUTE

0

0 = Output stage outputs OUT3 mixer

OUT3 mixer

control

1 = Output stage muted – drives out

VMID. Can be used as VMID buffer in

this mode.

3

2

1

0

6

OUT4_2OUT3

BYPL2OUT3

LMIX2OUT3

LDAC2OUT3

OUT4MUTE

0

1

0

OUT4 mixer output to OUT3

0 = disabled

1= enabled

ADC input to OUT3

0 = disabled

1= enabled

Left DAC mixer to OUT3

0 = disabled

1= enabled

Left DAC output to OUT3

0 = disabled

1= enabled

R57

0 = Output stage outputs OUT4 mixer

OUT4 mixer

control

1 = Output stage muted – drives out

VMID. Can be used as VMID buffer in

this mode.

5

4

HALFSIG

0

0=OUT4 normal output

1=OUT4 attenuated by 6dB

Left DAC mixer to OUT4

0 = disabled

LMIX2OUT4

1= enabled

3

1

0

LDAC2OUT4

RMIX2OUT4

RDAC2OUT4

0

1

Left DAC to OUT4

0 = disabled

1= enabled

Right DAC mixer to OUT4

0 = disabled

1= enabled

Right DAC output to OUT4

0 = disabled

1= enabled

Table 45 OUT3/OUT4 Mixer Registers

The OUT3 and OUT4 output stages each have a selectable gain boost of 1.5x (3.52dB). When this

boost is enabled the output DC level is also level shifted (from AVDD/2 to 1.5xAVDD/2) to prevent

the signal from clipping. A dedicated amplifier BUFDCOP, as shown in Figure 25, is used to perform

the DC level shift operation. This buffer must be enabled using the BUFDCOPEN register bit for this

operating mode. It should also be noted that if SPKVDD is not equal to or greater than 1.5xAVDD

this boost mode may result in signals clipping. Table 42 summarises the effect of the OUT3BOOST

and OUT4BOOST control bits.

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Figure 25 Outputs OUT3 and OUT4

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R49

Output control

3

OUT3BOOST

0

0 = OUT3 output gain = -1;

DC = AVDD / 2

1 = OUT3 output gain = +1.5

DC = 1.5 x AVDD / 2

4

8

OUT4BOOST

BUFDCOPEN

0

0 = OUT4 output gain = -1;

DC = AVDD / 2

1 = OUT4 output gain = +1.5

DC = 1.5 x AVDD / 2

R1

0

Dedicated buffer for DC level shifting

output stages when in 1.5x gain

boost configuration.

Power

management

1

0=Buffer disabled

1=Buffer enabled (required for 1.5x

gain boost)

Table 46 OUT3 and OUT4 Boost Stages Control

OUT3BOOST/

OUTPUT

STAGE GAIN

OUTPUT DC

LEVEL

OUTPUT STAGE

CONFIGURATION

OUT4BOOST

0

1

1x

AVDD/2

Inverting

1.5x

1.5xAVDD/2

Non-inverting

Table 47 OUT3/OUT4 Output Boost Stage Details

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OUTPUT PHASING

The relative phases of the analogue outputs will depend upon the following factors:

1. DACPOLL and DACPOLR invert bits: Setting these bits to 1 will invert the DAC output.

2. Mixer configuration: The polarity of the signal will depend upon the route through the mixer path.

For example, DACL can be directly input to the OUT3 mixer, giving a 180° phase shift at the OUT3

mixer output. However, if DACL is input to the OUT3 mixer via the left mixer, an additional phase

shift will be introduced, giving 0° phase shift at the OUT3 mixer output.

3. Output boost set-up: When 1.5x boost is enabled on an output, no phase shift occurs. When 1.5x

boost is not enabled, a 180° phase shift occurs.

Figure 20 shows where these phase inversions can occur in the output signal path.

Figure 26 Output Signal Path Phasing

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Table 48 shows the polarities of the outputs in various configurations.

Unless otherwise stated, polarity is shown with respect to left DAC output in non-inverting mode.

Note that only registers relating to the mixer paths are shown here (Mixer enables, volume settings,

output enables etc are not shown).

CONFIGURATION

MIXER PATH

REGISTERS

DIFFERENT

FROM DEFAULT

Default:

0

0°

1

0°

1

0°

1

0°

1

180°

1

180°

1

Stereo DAC playback

to LOUT1/ROUT1,

LOUT2/ROUT2 and

OUT4/OUT3

DACs inverted

1

0

1

0

1

0

180°

0°

1

Stereo DAC playback

to LOUT1/ROUT1 and

LOUT2/ROUT2 and

0°

1

1.5

OUT4/OUT3

(Speaker boost

enabled)

Stereo DAC playback

to LOUT1/ROUT1 and

LOUT2/ROUT2 and

0

1

0

1

0

180°

1.5

180°

1.5

0°

1

0°

1

180°

1

180°

1

OUT4/OUT3

(OUT3 and OUT4

boost enabled)

Stereo playback to

OUT3/OUT4 (DACs

input to OUT3/OUT4

mixers via left/right

mixers)

LDAC2OUT3=0

RDAC2OUT4=0

LMIX2OUT3=1

RMIX2OUT4=1

180°

1

180°

1

0°

1

0°

1

180°

1

180°

1

Differential output of

mono mix of DACs via

LOUT2/ROUT2 (e.g.

BTL speaker drive)

0

1

0

1

0

0°

1

0°

1

0°

1

0°

1

180°

1

0°

1

High power speaker

drive

0°

1

0°

1

0°

1

0°

1

0°

180°

1.5

Table 48 Relative Output Phases

Note that differential output should not be set up by combining outputs in boost mode with outputs

which are not in boost mode as this would cause a DC offset current on the outputs.

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ENABLING THE OUTPUTS

Each analogue output of the WM8976 can be separately enabled or disabled. The analogue mixer

associated with each output has a separate enable. All outputs are disabled by default. To save

power, unused parts of the WM8976 should remain disabled.

Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled

(BUFIOEN=0) or when BUFDCOP is disabled (BUFDCOPEN=0) when configured in output boost

mode, as this may cause pop noise (see “Power Management” and “Applications Information”

sections).

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1

2

BUFIOEN

0

Unused input/output tie off buffer enable

OUT3 mixer enable

Power

Management

1

6

7

8

7

6

OUT3MIXEN

OUT4MIXEN

BUFDCOPEN

ROUT1EN

LOUT1EN

SLEEP

OUT4 mixer enable

Output stage 1.5xAVDD/2 driver enable

ROUT1 output enable

R2

Power

Management

2

LOUT1 output enable

0 = normal device operation

1 = residual current reduced in device

standby mode if clocks still running

R3

2

3

5

6

7

8

LMIXEN

0

Left mixer enable

Right mixer enable

ROUT2 output enable

LOUT2 output enable

OUT3 enable

Power

Management

3

RMIXEN

ROUT2EN

LOUT2EN

OUT3EN

OUT4EN

OUT4 enable

Note: All “Enable” bits are 1 = ON, 0 = OFF

Table 49 Output Stages Power Management Control

THERMAL SHUTDOWN

The speaker outputs can drive very large currents. To protect the WM8976 from overheating a

thermal shutdown circuit is included. If the device temperature reaches approximately 125⁰C and the

thermal shutdown circuit is enabled (TSDEN=1) then the speaker amplifiers will be disabled if

TSDEN is set. The thermal shutdown may also be configured to generate an interrupt. See the GPIO

and Interrupt Controller section for details.

REGISTER

ADDRESS

BIT

LABEL

TSDEN

DEFAULT

DESCRIPTION

R49

1

Thermal Shutdown Enable

0 : thermal shutdown disabled

1 : thermal shutdown enabled

Output

control

Table 50 Thermal Shutdown

UNUSED ANALOGUE INPUTS/OUTPUTS

Whenever an analogue input/output is disabled, it remains connected to a voltage source (either

AVDD/2 or 1.5xAVDD/2 as appropriate) through a resistor. This helps to prevent pop noise when the

output is re-enabled. The resistance between the voltage buffer and the output pins can be

controlled using the VROI control bit. The default impedance is low, so that any capacitors on the

outputs can charge up quickly at start-up. If a high impedance is desired for disabled outputs, VROI

can then be set to 1, increasing the resistance to about 30kΩ.

REGISTER

ADDRESS

BIT

LABEL

VROI

DEFAULT

DESCRIPTION

R49

0

VREF (AVDD/2 or 1.5xAVDD/2) to

analogue output resistance

0: approx 1kΩ

1: approx 30 kΩ

Table 51 Disabled Outputs to VREF Resistance

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A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 27. This

buffer can be enabled using the BUFIOEN register bit.

If the SPKBOOST, OUT3BOOST or OUT4BOOST bits are set then the relevant outputs will be tied

to the output of the DC level shift buffer at 1.5xAVDD/2 when disabled.

Figure 27 summarises the tie-off options for the speaker and mono output pins.

Figure 27 Unused Input/Output Pin Tie-off Buffers

L/ROUT2EN/

OUT3/4EN

OUT3BOOST/

VROI

OUTPUT CONFIGURATION

OUT4BOOST/

SPKBOOST

0

1

0

1

0

1

0

1

0

1

X

1kꢀ tie-off to AVDD/2

30kꢀ tie-off to AVDD/2

1kꢀ tie-off to 1.5xAVDD/2

30kꢀ tie-off to 1.5xAVDD/2

Output enabled (DC level=AVDD/2)

Output enabled (DC level=1.5xAVDD/2)

Table 52 Unused Output Pin Tie-off Options

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DIGITAL AUDIO INTERFACES

The audio interface has four pins:

•

ADCDAT: ADC data output

DACDAT: DAC data input

LRC: Data Left/Right alignment clock

BCLK: Bit clock, for synchronisation

The clock signals BCLK, and LRC can be outputs when the WM8976 operates as a master, or inputs

when it is a slave (see Master and Slave Mode Operation, below).

Five different audio data formats are supported:

•

Left justified

Right justified

I²S

DSP mode A

DSP mode B

All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the

Electrical Characteristic section for timing information.

MASTER AND SLAVE MODE OPERATION

The WM8976 audio interface may be configured as either master or slave. As a master interface

device the WM8976 generates BCLK and LRC and thus controls sequencing of the data transfer on

ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In

slave mode (MS=0), the WM8976 responds with data to clocks it receives over the digital audio

interfaces.

AUDIO DATA FORMATS

In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRC

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRC transition.

Figure 28 Left Justified Audio Interface (assuming n-bit word length)

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In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition.

All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and

sample rate, there may be unused BCLK cycles after each LRC transition.

Figure 29 Right Justified Audio Interface (assuming n-bit word length)

In I²S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The

other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency

and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of

the next.

Figure 30 I²S Audio Interface (assuming n-bit word length)

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In DSP/PCM mode, the left channel MSB is available on either the 1^st(mode B) or 2^nd(mode A)

rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data

immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,

there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

Figure 31 DSP/PCM Mode Audio Interface (mode A, LRP=0)

Figure 32 DSP/PCM Mode Audio Interface (mode B, LRP=1)

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4

0

DACMONO

0

Selects between stereo and mono DAC

operation:

Audio

Interface

Control

0=Stereo device operation

1=Mono device operation. DAC data

appears in ‘left’ phase of LRC

1

2

ADCLRSWAP

DACLRSWAP

0

Controls whether ADC data appears in

‘right’ or ‘left’ phases of LRC clock:

0=ADC data appear in ‘left’ phase of

LRC

1=ADC data appears in ‘right’ phase of

LRC

Controls whether DAC data appears in

‘right’ or ‘left’ phases of LRC clock:

0=DAC data appear in ‘left’ phase of

LRC

1=DAC data appears in ‘right’ phase of

LRC

4:3

6:5

FMT

WL

10

Audio interface Data Format Select:

00=Right Justified

01=Left Justified

10=I²S format

11= DSP/PCM mode

Word length

00=16 bits

01=20 bits

10=24 bits

11=32 bits (see note)

LRC clock polarity

0=normal

7

8

LRP

BCP

1=inverted

BCLK polarity

0=normal

1=inverted

Table 53 Audio Interface Control

Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected,

the device will operate in 24-bit mode.

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised

below. The audio interfaces can be controlled individually.

Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK,

and LRC are outputs. The frequency of BCLK in master mode are controlled with BCLKDIV. These

are divided down versions of master clock.

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6

0

MS

0

Sets the chip to be master over LRC

and BCLK

Clock

Generation

Control

0=BCLK and LRC clock are inputs

1=BCLK and LRC clock are outputs

generated by the WM8976 (MASTER)

4:2

7:5

8

BCLKDIV

MCLKDIV

CLKSEL

000

010

1

Configures the BCLK output frequency,

for use when the chip is master over

BCLK.

000=divide by 1 (BCLK=SYSCLK)

001=divide by 2 (BCLK=SYSCLK)

010=divide by 4

011=divide by 8

100=divide by 16

101=divide by 32

110=reserved

111=reserved

Sets the scaling for either the MCLK or

PLL clock output (under control of

CLKSEL)

000=divide by 1

001=divide by 1.5

010=divide by 2

011=divide by 3

100=divide by 4

101=divide by 6

110=divide by 8

111=divide by 12

Controls the source of the clock for all

internal operation:

0=MCLK

1=PLL output

Table 54 Clock Control

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AUDIO SAMPLE RATES

The WM8976 sample rates for the ADC and the DACs are set using the SR register bits. The

cutoffs for the digital filters and the ALC attack/decay times stated are determined using these

values and assume a 256fs master clock rate.

If a sample rate that is not explicitly supported by the SR register settings is required then the

closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack,

decay and hold times will scale appropriately.

REGISTER

ADDRESS

BIT

LABEL

SR

DEFAULT

000

DESCRIPTION

R7

3:1

Approximate sample rate (configures the

coefficients for the internal digital filters):

Additional

Control

000=48kHz

001=32kHz

010=24kHz

011=16kHz

100=12kHz

101=8kHz

110-111=reserved

Table 55 Sample Rate Control

MASTER CLOCK AND PHASE LOCKED LOOP (PLL)

The WM8976 has an on-chip phase-locked loop (PLL) circuit that can be used to:

Generate master clocks for the WM8976 audio functions from another external clock, e.g. in

telecoms applications.

Generate and output (on pin CSB/GPIO1 and/or GPI04) a clock for another part of the system that is

derived from an existing audio master clock.

Figure 33 shows the PLL and internal clocking arrangment on the WM8976.

The PLL can be enabled or disabled by the PLLEN register bit.

Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are

set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1

5

PLLEN

0

PLL enable

0=PLL off

1=PLL on

Power

management 1

Table 56 PLLEN Control Bit

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Figure 33 PLL and Clock Select Circuit

The PLL frequency ratio R = f₂/f₁(see Figure 33) can be set using the register bits PLLK and PLLN:

PLLN = int R

PLLK = int (2²⁴(R-PLLN))

EXAMPLE:

MCLK=12MHz, required clock = 12.288MHz.

R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a

selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement.

Enabling the divide by 2 sets the required f₂= 4 x 2 x 12.288MHz = 98.304MHz.

R = 98.304 / 12 = 8.192

PLLN = int R = 8

k = int ( 2²⁴x (8.192 – 8)) = 3221225 = 3126E9h

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R36

4

PLLPRESCALE

0

0 = MCLK input not divided (default)

PLL N value

1 = Divide MCLK by 2 before input

to PLL

3:0

5:0

PLLN

1000

0Ch

Integer (N) part of PLL input/output

frequency ratio. Use values greater

than 5 and less than 13.

R37

PLLK [23:18]

Fractional (K) part of PLL1

input/output frequency ratio (treat as

one 24-digit binary number).

PLL K value

1

R38

8:0

PLLK [17:9]

PLLK [8:0]

093h

0E9h

PLL K Value

2

R39

PLL K Value

3

Table 57 PLL Frequency Ratio Control

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The PLL performs best when f₂is around 90MHz. Its stability peaks at N=8. Some example settings

are shown in Table 58.

MCLK

(MHz)

(F1)

12

DESIRED

OUTPUT

(MHz)

F2

PRESCALE

DIVIDE

POSTSCALE

DIVIDE

R

N

K

(MHz)

(Hex)

11.29

12.288

11.29

90.3168

98.304

90.3168

98.304

90.3168

98.304

90.3168

98.304

90.3168

98.304

90.3168

98.304

90.3168

98.304

90.3168

98.304

90.3168

98.304

1

2

7.5264

8.192

7

8

6

7

6

9

A

9

7

8

6

7

6

7

86C226

3126E8

F28BD4

8FD525

45A1CA

D3A06E

6872AF

3D70A3

2DB492

FD809F

1F76F7

EE009E

86C226

3126E8

F28BD4

8FD525

BOAC93

482296

12

13

6.947446

7.561846

6.272

13

12.288

11.29

14.4

19.2

19.68

19.8

24

12.288

11.29

6.826667

9.408

12.288

11.29

10.24

9.178537

9.990243

9.122909

9.929697

7.5264

12.288

11.29

12.288

11.29

24

12.288

11.29

8.192

26

6.947446

7.561846

6.690133

7.281778

26

12.288

11.29

27

12.288

Table 58 PLL Frequency Examples

LOOPBACK

Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data

from the ADC audio interface is fed directly into the DAC data input.

COMPANDING

The WM8976 supports A-law and µ-law and companding and linear mode on both transmit (ADC)

and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by

writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively.

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R5

0

LOOPBACK

0

Digital loopback function

0=No loopback

Companding

Control

1=Loopback enabled, ADC data output

is fed directly into left DAC data input.

2:1

4:3

5

ADC_COMP

DAC_COMP

WL8

0

ADC companding

00=off (linear mode)

01=reserved

10=µ-law

11=A-law

DAC companding

00=off (linear mode)

01=reserved

10=µ-law

11=A-law

0=off

1=device operates in 8-bit mode

Table 59 Companding Control

Companding involves using a piecewise linear approximation of the following equations (as set out

by ITU-T G.711 standard) for data compression:

µ-law (where µ=255 for the U.S. and Japan):

F(x) = ln( 1 + µ|x|) / ln( 1 + µ)

A-law (where A=87.6 for Europe):

F(x) = A|x| / ( 1 + lnA)

-1

x

1

} for x 1/A

} for 1/A 1

F(x) = ( 1 + lnA|x|) / (1 + lnA)

x

The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted

for µ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB’s

of data.

Companding converts 13 bits (µ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The

input data range is separated into 8 levels, allowing low amplitude signals better precision than that

of high amplitude signals. This is to exploit the operation of the human auditory system, where

louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8-

bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).

Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to

use 8 BCLK’s per LRC frame. When using DSP mode B, this allows 8-bit data words to be output

consecutively every 8 BCLK’s and can be used with 8-bit data words using the A-law and u-law

companding functions.

BIT7

BIT[6:4]

BIT[3:0]

SIGN

EXPONENT

MANTISSA

Table 60 8-bit Companded Word Composition

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u-law Companding

1

120

100

80

60

40

20

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Normalised Input

Figure 34 u-Law Companding

A-law Companding

1

120

100

80

60

40

20

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.2

0.4

0.6

0.8

1

Normalised Input

Figure 35 A-Law Companding

GENERAL PURPOSE INPUT/OUTPUT

The WM8976 has two dual purpose input/output pins.

•

CSB/GPIO1: CSB / GPIO pin

L2/GPIO2: Line input / headphone detection input

The GPIO2 function is provided for use as a jack detection input.

The GPIO1 function is provided for use as a jack detection input or a general purpose output.

The default configuration for the CSB/GPIO1 pin is to be an input.

When setup as an input, the CSB/GPIO1 pin can either be used as CSB or for jack detection,

depending on how the MODE pin is set.

Table 49 illustrates the functionality of the GPIO1 pin when used as a general purpose output.

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8

2:0

GPIO1SEL

000

CSB/GPIO1 pin function select:

GPIO

000= input (CSB/jack detection:

depending on MODE setting)

Control

001= reserved

010=Temp ok

011=Amute active

100=PLL clk o/p

101=PLL lock

110=logic 0

111=logic 1

3

GPIO1POL

OPCLKDIV

0

GPIO1 Polarity invert

0=Non inverted

1=Inverted

5:4

00

PLL Output clock division ratio

00=divide by 1

01=divide by 2

10=divide by 3

11=divide by 4

Table 61 CSB/GPIO Control

Note: If MODE is set to 3 wire mode, CSB/GPIO1 shall be used as CSB input irrespective of the

GPIO1SEL[2:] bits.

Note that SLOWCLKEN must be enabled when using the Jack Detect function.

For further details of the Jack detect operation see the OUTPUT SWITCHING section.

OUTPUT SWITCHING (JACK DETECT)

When the device is operated using a 2-wire interface the CSB/GPIO1 pin can be used as a switch

control input to automatically disable one set of outputs and enable another the most common use

for this functionality is as jack detect circuitry. The L2/GPIO2 and R2/GPIO3 pins can also be used

for this purpose.

The GPIO pins have an internal de-bounce circuit when in this mode in order to prevent the output

enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a

slow clock with period 2²¹x MCLK and is enabled by the SLOWCLKEN bit.

Notes:

1. The SLOWCLKEN bit must be enabled for the jack detect circuitry to operate.

2. The GPIOPOL bit is not relevant for jack detection, it is the signal detected at the pin which is

used

Switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2, OUT3

and OUT4 has 2 associated enables. OUT1_EN_0, OUT2_EN_0, OUT3_EN_0 and OUT4_EN_0

are the output enable signals which are used if the selected jack detection pin is at logic 0 (after de-

bounce). OUT1_EN_1, OUT2_EN_1, OUT3_EN_1 and OUT4_EN_1 are the output enable signals

which are used if the selected jack detection pin is at logic 1 (after de-bounce).

The jack detection enables operate as follows:

All OUT_EN signals have an AND function performed with their normal enable signals (in Table 49).

When an output is normally enabled as per Table 49 the selected jack detection enable (controlled

by selected jack detection pin polarity) is set 0; it will turn the output off. If the normal enable signal is

already OFF (0), the jack detection signal will have no effect due to the AND function.

During jack detection if the user desires an output to be un-changed whether the jack is in or not,

both the JD_EN settings i.e. JD_EN0 and JD_EN1, should be set to 0000.

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The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the

VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should

set to 0 for all JD_EN0 or JD_EN1 settings.

If jack detection is not enabled (JD_EN=0), the output enables default to all 1’s, allowing the outputs

to be controlled as normal via the normal output enables found in Table 50.

BIT

LABEL

DEFAULT

DESCRIPTION

REGISTER

ADDRESS

R9

GPIO control

5:4

JD_SEL

00

Pin selected as jack detection input

00 = GPIO1

01 = GPIO2

10 = GPIO3

11 = Reserved

6

JD_EN

0

Jack Detection Enable

0 = disabled

1 = enabled

8:7

3:0

JD_VMID

JD_EN0

00

[7] VMID_EN_0

[8] VMID_EN_1

R13

0000

Output enables when selected jack

detection input is logic 0.

[0]= OUT1_EN_0

[1]= OUT2_EN_0

[2]= OUT3_EN_0

[3]= OUT4_EN_0

7:4

JD_EN1

0000

Output enables when selected jack

detection input is logic 1

0000-0011 = Reserved

[4]= OUT1_EN_1

[5]= OUT2_EN_1

[6]= OUT3_EN_1

[7]= OUT4_EN_1

Table 62 Jack Detect Register Control Bits

CONTROL INTERFACE

SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS

The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin

determines the 2 or 3 wire mode as shown in Table 63.

The WM8976 is controlled by writing to registers through a serial control interface. A control word

consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is

accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each

control register.

MODE

Low

INTERFACE FORMAT

2 wire

3 wire

High

Table 63 Control Interface Mode Selection

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3-WIRE SERIAL CONTROL MODE

In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on

CSB/GPIO1 pin latches in a complete control word consisting of the last 16 bits.

Figure 36 3-Wire Serial Control Interface

2-WIRE SERIAL CONTROL MODE

The WM8976 supports software control via a 2-wire serial bus. Many devices can be controlled by

the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit

address of each register in the WM8976).

The WM8976 operates as a slave 2-wire device only. The controller indicates the start of data

transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device

address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in

the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address

received matches the address of the WM8976, then the WM8976 responds by pulling SDIN low on

the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’ when operating in

write only mode, the WM8976 returns to the idle condition and wait for a new start condition and

valid address.

During a write, once the WM8976 has acknowledged a correct address, the controller sends the first

byte of control data (B15 to B8, i.e. the WM8976 register address plus the first bit of register data).

The WM8976 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The

controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register

data), and the WM8976 acknowledges again by pulling SDIN low.

Transfers are complete when there is a low to high transition on SDIN while SCLK is high. After a

complete sequence the WM8976 returns to the idle state and waits for another start condition. If a

start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN

changes while SCLK is high), the device jumps to the idle condition.

DEVICE ADDRESS RD / WR

(7 BITS) BIT

ACK

(LOW)

CONTROL BYTE 1

(BITS 15 TO 8)

ACK

(LOW)

CONTROL BYTE 1

(BITS 7 TO 0)

ACK

(LOW)

SDIN

SCLK

START

STOP

register address and

1st register data bit

remaining 8 bits of

register data

Figure 37 2-Wire Serial Control Interface

In 2-wire mode the WM8976 has a fixed device address, 0011010.

RESETTING THE CHIP

The WM8976 can be reset by performing a write of any value to the software reset register (address

0 hex). This will cause all register values to be reset to their default values. In addition to this there

is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the

device is powered up.

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POWER SUPPLIES

The WM8976 can use up to four separate power supplies:

AVDD and AGND: Analogue supply, powers all analogue functions except the speaker output and

mono output drivers. AVDD can range from 2.5V to 3.6V and has the most significant impact on

overall power consumption (except for power consumed in the headphone). A large AVDD slightly

improves audio quality.

SPKVDD and SPKGND: Headphone and Speaker supplies, power the speaker and mono output

drivers. SPKVDD can range from 2.5V to 5V. SPKVDD can be tied to AVDD, but it requires separate

layout and decoupling capacitors to curb harmonic distortion. With a larger SPKVDD, louder

headphone and speaker outputs can be achieved with lower distortion. If SPKVDD is lower than

AVDD, the output signal may be clipped.

DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces.

DCVDD can range from 1.71V to 3.6V, and has no effect on audio quality. The return path for

DCVDD is DGND, which is shared with DBVDD.

DBVDD can range from 1.71V to 3.6V. DBVDD return path is through DGND.

It is possible to use the same supply voltage for all four supplies. However, digital and analogue

supplies should be routed and decoupled separately on the PCB to keep digital switching noise out

of the analogue signal paths.

DCVDD should be greater than or equal to 1.9V when using the PLL.

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RECOMMENDED POWER UP/DOWN SEQUENCE

In order to minimise output pop and click noise, it is recommended that the WM8976 device is

powered up and down using one of the following sequences:

Power-up when NOT using the output 1.5x boost stage:

1. Turn on external power supplies. Wait for supply voltage to settle.

2. Mute all analogue outputs.

3. Set L/RMIXEN = 1 and DACENL/R = 1 in register R3.

4. Set BUFIOEN = 1 and VMIDSEL[1:0] to required value in register R1. Wait for the VMID supply

to settle. *Refer notes 1 and 2.

5. Set BIASEN = 1 in register R1.

6. Set L/ROUT1EN = 1 in register R2.

7. Enable other mixers as required.

8. Enable other outputs as required.

9. Set remaining registers.

Power-up when using the output 1.5x boost stage:

1. Turn on external power supplies. Wait for supply voltage to settle.

2. Mute all analogue outputs.

3. Enable unused output chosen from L/ROUT2, OUT3 or OUT4. If unused output not available,

chose one of these outputs not required at power up.

4. Set BUFDCOPEN = 1 and BUFIOEN = 1 in register R1.

5. Set SPKBOOST = 1 in register R49.

6. Set VMIDSEL[1:0] to required value in register R1. Wait for the VMID supply to settle. *Refer

notes 1 and 2.

7. Set L/RMIXEN = 1 and DACENL/R = 1 in register R3.

8. Set BIASEN = 1 in register R1.

9. Set L/ROUT2EN = 1 in register R3. *Note 3.

10. Enable other mixers as required.

11. Enable other outputs as required.

12. Set remaining registers.

Power Down (all cases):

1. Mute all analogue outputs.

2. Disable Power Management Register 1. R1 = 0x00.

3. Disable Power Management Register 2. R2 = 0x00.

4. Disable Power Management Register 3. R3 = 0x00.

5. Remove external power supplies.

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Notes:

1. This step enables the internal device bias buffer and the VMID buffer for unassigned

inputs/outputs. This will provide a startup reference voltage for all inputs and outputs. This will

cause the inputs and outputs to ramp towards VMID (NOT using output 1.5x boost) or 1.5 x

(AVDD/2) (using output 1.5x boost) in a way that is controlled and predictable (see note 2).

2. Choose the value of the VMIDSEL bits based on the startup time (VMIDSEL=10 for slowest

startup, VMIDSEL=11 for fastest startup). Startup time is defined by the value of the VMIDSEL

bits (the reference impedance) and the external decoupling capacitor on VMID.

3. Setting DACEN to off while operating in x1.5 boost mode will cause the VMID voltage to drop to

AVDD/2 midrail level and cause an output pop.

In addition to the power on sequence, it is recommended that the zero cross functions are used

when changing the volume in the PGAs to avoid any audible pops or clicks.

V_{por_on}

V_pora

V_{por_off}

Power Supply

POR

DGND

No Power

POR Undefined

Device Ready

DNC

Internal POR active

POR

I²S Clocks

DNC

t_adcint

ADC Internal

State

Power down

Init

Normal Operation

PD

Init

Normal Operation

Power down

t_{midrail_on}

t_{midrail_off}

(Note 1)

(Note 2)

AVDD/2

Analogue Inputs

GD

ADCDAT pin

(Note 3)

ADC enabled

ADC off

INPPGA enabled

VMID enabled

ADC enabled

ADCEN bit

INPPGAEN bit

VMIDSEL/

BIASEN bits ^{(Note 4)}

Figure 38 ADC Power Up and Down Sequence (not to scale)

SYMBOL

t_{midrail_on}

MIN

TYPICAL

500

MAX

UNIT

ms

s

t_{midrail_off}

>10

t_adcint

2/fs

n/fs

ADC Group Delay

29/fs

Table 64 Typical POR Operation (typical values, not tested)

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Notes:

1. The analogue input pin charge time, t_{midrail_on,}is determined by the VMID pin charge time. This

time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance

and AVDD power supply rise time.

2. The analogue input pin discharge time, t_{midrail_off,}is determined by the analogue input coupling

capacitor discharge time. The time, t_{midrail_off}, is measured using a 1µF capacitor on the

analogue input but will vary dependent upon the value of input coupling capacitor.

3. While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system

noise but no significant digital output will be present.

4. The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for

normal ADC operation.

5. ADCDAT data output delay from power up - with power supplies starting from 0V - is determined

primarily by the VMID charge time. ADC initialisation and power management bits may be set

immediately after POR is released; VMID charge time will be significantly longer and will dictate

when the device is stabilised for analogue input.

6. ADCDAT data output delay at power up from device standby (power supplies already applied) is

determined by ADC initialisation time, 2/fs.

Figure 39 DAC Power Up and Down Sequence (not to scale)

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SYMBOL

t_{line_midrail_on}

t_{line_midrail_off}

t_{hp_midrail_on}

MIN

TYPICAL

500

1

MAX

UNIT

ms

s

500

6

ms

s

t_{hp__midrail_off}

t_dacint

2/fs

29/fs

n/fs

DAC Group Delay

Table 65 Typical POR Operation (typical values, not tested)

Notes:

1. The lineout charge time, t_{line_midrail_on,}is mainly determined by the VMID pin charge time. This

time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance

and AVDD power supply rise time. The values above were measured using a 4.7µF capacitor.

2. It is not advisable to allow DACDAT data input during initialisation of the DAC. If the DAC data

value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue

outputs. The same is also true if the DACDAT is removed at a non-zero value, and no mute

function has been applied to the signal beforehand.

3. The lineout discharge time, t_{line_midrail_off,}is dependent upon the value of the lineout coupling

capacitor and the leakage resistance path to ground. The values above were measured using a

10µF output capacitor.

4. The headphone charge time, t_{hp_midrail_on,}is dependent upon the value of VMID decoupling

capacitor and VMID pin input resistance and AVDD power supply rise time. The values above

were measured using a 4.7µF VMID decoupling capacitor.

5. The headphone discharge time, t_{hp_midrail_off,}is dependent upon the value of the headphone

coupling capacitor and the leakage resistance path to ground. The values above were

measured using a 100µF capacitor.

6. The VMIDSEL and BIASEN bits must be set to enable analogue output midrail voltage and for

normal DAC operation.

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WM8976

POWER MANAGEMENT

SAVING POWER BY REDUCING OVERSAMPLING RATE

The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode.

Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x

oversampling results in a slight decrease in noise performance compared to 128x but lowers the

power consumption of the device.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R10

3

DACOSR128

0

DAC oversample rate select

0 = 64x (lowest power)

1 = 128x (best SNR)

DAC control

R14

ADCOSR128

0

ADC oversample rate select

0 = 64x (lowest power)

1 = 128x (best SNR)

ADC control

Table 66 ADC and DAC Oversampling Rate Selection

VMID

The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance

of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the

startup time of the VMID circuit.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1

1:0

VMIDSEL

00

Reference string impedance to VMID pin

(detemines startup time):

Power

management 1

00=off (open circuit)

01=75kꢀ

10=300kꢀ

11=5kꢀ (for fastest startup)

Table 67 VMID Impedance Control

BIASEN

The analogue amplifiers will not operate unless BIASEN is enabled.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1

3

BIASEN

0

Analogue amplifier bias control

0=disabled

Power

management 1

1=enabled

Table 68 Analogue Bias Control

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REGISTER MAP

REGISTER

NAME

B8

B7

B6

B5

B4

B3

B2

B1

B0

DEF’T

VAL

ADDR

B[15:9]

DEC HEX

(HEX)

0

1

00

01

Software Reset

Software reset

Power manage’t 1 BUFDCOP OUT4MIX OUT3MIX PLLEN

EN EN EN

Power manage’t 2 ROUT1EN LOUT1EN SLEEP

MICBEN BIASEN BUFIOEN

VMIDSEL

000

2

02

0

BOOST

ENL

0

INPPGA

ENL

0

ADCENL

3

4

03

04

Power manage’t 3

Audio Interface

OUT4EN

BCP

OUT3EN LOUT2EN ROUT2EN

RMIXEN LMIXEN DACENR DACENL

000

050

LRP

WL

FMT

DAC

ADC

DAC

MONO

LRSWAP LRSWAP

5

6

7

8

9

05

06

07

08

09

Companding ctrl

Clock Gen ctrl

Additional ctrl

GPIO Stuff

0

WL8

0

DAC_COMP

BCLKDIV

ADC_COMP

LOOPBACK

MS

000

140

CLKSEL

MCLKDIV

0

SR

LOWCLKEN 000

0

OPCLKDIV

GPIO1POL

0

GPIO1SEL[2:0]

0

000

Jack detect control

JD_VMID

JD_EN

SOFT

MUTE

0

JD_SEL

0

10 0A DAC Control

0

DACOSR AMUTE DACPOLR DACPOLL

128

11 0B Left DAC digital Vol DACVU

12 0C Right DAC dig’l Vol DACVU

DACVOLL

DACVOLR

0FF

000

100

13 0D

ack Detect Control

JD_EN1

HPFCUT

JD_EN0

14 0E ADC Control

HPFEN

HPFAPP

ADCOSR

128

ADCVOLL

0

ADCLPOL

15 0F ADC Digital Vol

ADCVU

EQ3DMODE

EQ2BW

EQ3BW

EQ4BW

0

0FF

12C

02C

032

000

038

00B

032

000

008

18 12

19 13

20 14

21 15

22 16

24 18

25 19

EQ1 – low shelf

EQ2 – peak 1

EQ3 – peak 2

EQ4 – peak 3

EQ5 – high shelf

DAC Limiter 1

DAC Limiter 2

0

EQ1C

EQ1G

EQ2G

EQ3G

EQ4G

EQ5G

EQ2C

EQ3C

EQ4C

EQ5C

LIMEN

0

LIMDCY

LIMATK

LIMBOOST

0

LIMLVL

27 1B Notch Filter 1

28 1C Notch Filter 2

29 1D Notch Filter 3

30 1E Notch Filter 4

NFU

NFEN

NFA0[13:7]

NFA0[6:0]

NFA1[13:7]

NFA1[6:0]

NFU

0

NFU

32 20

33 21

34 22

35 23

36 24

ALC control 1

ALC control 2

ALC control 3

Noise Gate

PLL N

ALCSEL

0

ALCMAXGAIN

ALCMINGAIN

ALCHLD

ALCDCY

ALCLVL

ALCATK

ALCMODE

0

NGEN

NGTH

0

PLLPRE

SCALE

PLLN[3:0]

37 25

38 26

39 27

41 29

PLL K 1

PLL K 2

PLL K 3

3D control

0

PLLK[23:18]

00C

093

0E9

000

PLLK[17:9]

PLLK[8:0]

0

DEPTH3D

43 2B Beep control

0

MUTER INVROUT2

PGA2INV

BEEPVOL

L2_2

BEEPEN

LIP2

44 2C Input ctrl

MBVSEL

0

LIN2

033

010

INPPGA INPPGA INPPGA

45 2D INP PGA gain ctrl

47 2F ADC Boost ctrl

INPPGA NPPGAZCL INPPGA

INPPGAVOLL

UPDATE

PGABOOSTL

0

MUTEL

0

L2_2BOOSTVOL

DACR2

0

AUXL2BOOSTVOL

SPK TSDEN VROI

100

002

49 31

Output ctrl

DACL2

OUT4

OUT3

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RMIX

LMIX

BOOST

BYPLMIXVOL

0

BOOST

50 32

51 33

52 34

Left mixer ctrl

AUXLMIXVOL

AUXRMIXVOL

AUXL2LMIX

UXR2RMIX

BYPL2LMIX DACL2LMIX

001

039

Right mixer ctrl

0

DACR2RMIX

LOUT1 (HP)

volume ctrl

HPVU

SPKVU

0

LOUT1ZC LOUT1

MUTE

LOUT1VOL

53 35

54 36

55 37

56 38

57 39

ROUT1 (HP)

volume ctrl

ROUT1ZC ROUT1

MUTE

ROUT1VOL

LOUT2VOL

ROUT2VOL

039

001

LOUT2 (SPK)

volume ctrl

LOUT2ZC LOUT2

MUTE

ROUT2 (SPK)

volume ctrl

ROUT2ZC ROUT2

MUTE

OUT3 mixer ctrl

0

OUT3

MUTE

OUT4

MUTE

0

OUT4_

BYPL2

OUT3

0

LMIX2

OUT3

RMIX2

OUT4

LDAC2

OUT3

2OUT3

LDAC2

OUT4

OUT4 (MONO)

mixer ctrl

0

HALFSIG

LMIX2

OUT4

RDAC2

OUT4

Table 69 WM8976 Register Map

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REGISTER BITS BY ADDRESS

Notes

1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits).

2. Register bits marked as "Reserved" should not be changed from the default.

REGISTER

ADDRESS

BIT

[8:0]

8

LABEL

RESET

DEFAULT

DESCRIPTION

REFER TO

0 (00h)

N/A

0

Software reset

Resetting the

Chip

1 (01h)

BUFDCOPEN

Dedicated buffer for DC level shifting output

stages when in 1.5x gain boost configuration.

Analogue

Outputs

0=Buffer disabled

1=Buffer enabled (required for 1.5x gain boost)

OUT4 mixer enable

0=disabled

7

6

5

OUT4MIXEN

OUT3MIXEN

PLLEN

0

Power

Management

1=enabled

OUT3 mixer enable

0=disabled

Power

Management

1=enabled

PLL enable

Master Clock

and Phase

Locked Loop

(PLL)

0=PLL off

1=PLL on

4

MICBEN

BIASEN

0

Microphone Bias Enable

0 = OFF (high impedance output)

1 = ON

Input Signal

Path

3

0

Analogue amplifier bias control

0=disabled

Power

Management

1=enabled

2

BUFIOEN

VMIDSEL

0

Unused input/output tie off buffer enable

0=disabled

Power

Management

1=enabled

1:0

00

Reference string impedance to VMID pin

00=off (open circuit)

01=75kꢀ

Power

Management

10=300kꢀ

11=5kꢀ

2 (02h)

8

7

6

ROUT1EN

LOUT1EN

SLEEP

0

ROUT1 output enable

0=disabled

Power

Management

1=enabled

LOUT1 output enable

0=disabled

Power

Management

1=enabled

0 = normal device operation

Power

Management

1 = residual current reduced in device standby

mode

5

4

0

Reserved

BOOSTENL

INPPGAENL

Input BOOST enable

0 = Boost stage OFF

1 = Boost stage ON

Reserved

Power

Management

3

2

0

Input PGA enable

0 = disabled

Power

Management

1 = enabled

1

0

Reserved

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REGISTER

ADDRESS

BIT

LABEL

ADCENL

DEFAULT

DESCRIPTION

REFER TO

0

Enable ADC:

Analogue to

Digital

Converter

(ADC)

0 = ADC disabled

1 = ADC enabled

3 (03h)

8

OUT4EN

OUT3EN

LOUT2EN

ROUT2EN

RMIXEN

LMIXEN

DACENR

DACENL

BCP

0

10

OUT4 enable

0 = disabled

1 = enabled

OUT3 enable

0 = disabled

1 = enabled

LOUT2 enable

0 = disabled

1 = enabled

ROUT2 enable

0 = disabled

1 = enabled

Power

Management

7

Power

Management

6

Power

Management

5

Power

Management

3

Right output channel mixer enable:

0 = disabled

Analogue

Outputs

1 = enabled

2

Left output channel mixer enable:

0 = disabled

Analogue

Outputs

1 = enabled

1

Right channel DAC enable

0 = DAC disabled

1 = DAC enabled

Left channel DAC enable

0 = DAC disabled

1 = DAC enabled

BCLK polarity

Analogue

Outputs

0

Analogue

Outputs

4 (04h)

8

Digital Audio

Interfaces

0=normal

1=inverted

7

LRP

LRC clock polarity

0=normal

Digital Audio

Interfaces

1=inverted

6:5

WL

Word length

Digital Audio

Interfaces

00=16 bits

01=20 bits

10=24 bits

11=32 bits

4:3

FMT

10

Audio interface Data Format Select:

00=Right Justified

01=Left Justified

10=I²S format

Digital Audio

Interfaces

11= DSP/PCM mode

2

1

DACLRSWAP

ADCLRSWAP

0

Controls whether DAC data appears in ‘right’ or

‘left’ phases of LRC clock:

Digital Audio

Interfaces

0=DAC data appear in ‘left’ phase of LRC

1=DAC data appears in ‘right’ phase of LRC

Controls whether ADC data appears in ‘right’ or

‘left’ phases of LRC clock:

Digital Audio

Interfaces

0=ADC data appear in ‘left’ phase of LRC

1=ADC data appears in ‘right’ phase of LRC

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REFER TO

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0

DACMONO

0

Selects between stereo and mono DAC operation:

0=Stereo device operation

Digital Audio

Interfaces

1=Mono device operation. DAC data appears in

‘left’ phase of LRC

5 (05h)

8:6

5

000

0

Reserved

WL8

Companding Control 8-bit mode

0=off

Digital Audio

Interfaces

1=device operates in 8-bit mode

DAC companding

00=off (linear mode)

01=reserved

4:3

2:1

DAC_COMP

00

Digital Audio

Interfaces

10=µ-law

11=A-law

ADC_COMP

ADC companding

00=off (linear mode)

01=reserved

Digital Audio

Interfaces

10=µ-law

11=A-law

0

LOOPBACK

CLKSEL

0

Digital loopback function

0=No loopback

Digital Audio

Interfaces

1=Loopback enabled, ADC data output is fed

directly into DAC data input.

6 (06h)

8

1

Controls the source of the clock for all internal

operation:

Digital Audio

Interfaces

0=MCLK

1=PLL output

7:5

MCLKDIV

010

Sets the scaling for either the MCLK or PLL clock

output (under control of CLKSEL)

Digital Audio

Interfaces

000=divide by 1

001=divide by 1.5

010=divide by 2

011=divide by 3

100=divide by 4

101=divide by 6

110=divide by 8

111=divide by 12

4:2

BCLKDIV

000

Configures the BCLK output frequency, for use

when the chip is master over BCLK.

Digital Audio

Interfaces

000=divide by 1 (BCLK=MCLK)

001=divide by 2 (BCLK=MCLK/2)

010=divide by 4

011=divide by 8

100=divide by 16

101=divide by 32

110=reserved

111=reserved

1

0

Reserved

MS

Sets the chip to be master over LRC and BCLK

0=BCLK and LRC clock are inputs

Digital Audio

Interfaces

1=BCLK and LRC clock are outputs generated by

the WM8976 (MASTER)

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

7 (07h)

8:4

3:1

00000

000

Reserved

SR

Approximate sample rate (configures the

coefficients for the internal digital filters):

Audio Sample

Rates

000=48kHz

001=32kHz

010=24kHz

011=16kHz

100=12kHz

101=8kHz

110-111=reserved

0

SLOWCLKEN

0

Slow clock enable. Used for both the jack insert

detect debounce circuit and the zero cross

timeout.

Analogue

Outputs

0 = slow clock disabled

1 = slow clock enabled

Reserved

8 (08h)

8:6

5:4

000

00

OPCLKDIV

GPIO1POL

PLL Output clock division ratio

00=divide by 1

General

Purpose

Input/Output

(GPIO)

01=divide by 2

10=divide by 3

11=divide by 4

3

0

GPIO1 Polarity invert

0=Non inverted

General

Purpose

Input/Output

(GPIO)

1=Inverted

2:0

GPIO1SEL

[2:0]

000

CSB/GPIO1 pin function select:

General

Purpose

Input/Output

(GPIO)

000= input (CSB/jack detection: depending on

MODE setting)

001= reserved

010=Temp ok

011=Amute active

100=PLL clk o/p

101=PLL lock

110=logic 1

111=logic 0

9 (09h)

8:7

6

JD_VMID

JD_EN

00

0

[7] VMID_EN_0

[8] VMID_EN_1

Output

Switching

(Jack Detect)

Jack Detection Enable

0=disabled

Output

Switching

(Jack Detect)

1=enabled

5

4

0

Reserved

JD_SEL

Pin selected as jack detection input

Output

Switching

(Jack Detect)

0 = GPIO1

1 = GPIO2

Reserved

3:0

0

10 (0Ah)

8:7

6

00

0

Reserved

SOFTMUTE

Softmute enable:

0=Disabled

1=Enabled

Reserved

Output Signal

Path

5:4

00

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REFER TO

Power

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DAC oversample rate select

3

DACOSR128

0

Management

0 = 64x (lowest power)

1 = 128x (best SNR)

2

1

0

8

AMUTE

0

Automute enable

Output Signal

Path

0 = Amute disabled

1 = Amute enabled

DACPOLR

DACPOLL

DACVU

0

Right DAC output polarity:

0 = non-inverted

Output Signal

Path

1 = inverted (180 degrees phase shift)

Left DAC output polarity:

0 = non-inverted

0

Output Signal

Path

1 = inverted (180 degrees phase shift)

11 (0Bh)

N/A

DAC left and DAC right volume do not update until

a 1 is written to DACVU (in reg 11 or 12)

Digital to

Analogue

Converter

(DAC)

7:0

DACVOLL

11111111

Left DAC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -127dB

Digital to

Analogue

Converter

(DAC)

0000 0010 = -126.5dB

... 0.5dB steps up to

1111 1111 = 0dB

12 (0Ch)

8

DACVU

N/A

DAC left and DAC right volume do not update until

a 1 is written to DACVU (in reg 11 or 12)

Output Signal

Path

7:0

DACVOLR

11111111

Right DAC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -127dB

Output Signal

Path

0000 0010 = -126.5dB

... 0.5dB steps up to

1111 1111 = 0dB

13 (0Dh)

8

0

Reserved

7:4

JD_EN1

JD_EN0

0000

Output enabled when selected jack detection input Output

is logic 1

Switching

(Jack Detect)

[4]= OUT1_EN_1

[5]= OUT2_EN_1

[6]= OUT3_EN_1

[7]= OUT4_EN_1

3:0

0000

Output enabled when selected jack detection input Output

is logic 0.

Switching

(Jack Detect)

[0]= OUT1_EN_0

[1]= OUT2_EN_0

[2]= OUT3_EN_0

[3]= OUT4_EN_0

14 (0Eh)

8

HPFEN

1

Analogue to

Digital

Converter

(ADC)

High Pass Filter Enable

0=disabled

1=enabled

7

HPFAPP

HPFCUT

0

Select audio mode or application mode

0=Audio mode (1^storder, fc = ~3.7Hz)

1=Application mode (2^ndorder, fc = HPFCUT)

Analogue to

Digital

Converter

(ADC)

6:4

000

Application mode cut-off frequency

See Table 14 for details.

Analogue to

Digital

Converter

(ADC)

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

ADC oversample rate select

REFER TO

3

ADCOSR

128

0

Power

Management

0 = 64x (lowest power)

1 = 128x (best SNR)

Reserved

2:1

0

00

0

ADCLPOL

ADCVU

ADC polarity adjust:

0=normal

Analogue to

Digital

Converter

(ADC)

1=inverted

15 (0Fh)

8

N/A

ADC volume does not update until a 1 is written to

ADCVU

Analogue to

Digital

Converter

(ADC)

7:0

ADCVOLL

11111111

ADC Digital Volume Control

0000 0000 = Digital Mute

0000 0001 = -127dB

0000 0010 = -126.5dB

... 0.5dB steps up to

Analogue to

Digital

Converter

(ADC)

1111 1111 = 0dB

16 (10h)

18 (12h)

8:0

8

11111111

1

Reserved

EQ3DMODE

EQ1C

0 = Equaliser and 3D Enhancement applied to

ADC path

Output Signal

Path

1 = Equaliser and 3D Enhancement applied to

DAC path

7

0

Reserved

6:5

EQ Band 1 Cut-off Frequency:

00=80Hz

Output Signal

Path

01=105Hz

10=135Hz

11=175Hz

4:0

8

EQ1G

01100

0

EQ Band 1 Gain Control. See Table 36 for details.

Output Signal

Path

19 (13h)

EQ2BW

EQ Band 2 Bandwidth Control

0=narrow bandwidth

1=wide bandwidth

Output Signal

Path

7

0

Reserved

6:5

EQ2C

01

EQ Band 2 Centre Frequency:

Output Signal

Path

00=230Hz

01=300Hz

10=385Hz

11=500Hz

4:0

8

EQ2G

01100

0

EQ Band 2 Gain Control. See Table 36 for details.

Output Signal

Path

20 (14h)

EQ3BW

EQ Band 3 Bandwidth Control

0=narrow bandwidth

1=wide bandwidth

Output Signal

Path

7

0

Reserved

6:5

EQ3C

EQ3G

01

EQ Band 3 Centre Frequency:

Output Signal

Path

00=650Hz

01=850Hz

10=1.1kHz

11=1.4kHz

4:0

01100

EQ Band 3 Gain Control. See Table 36 for details.

Output Signal

Path

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REGISTER

ADDRESS

BIT

LABEL

EQ4BW

DEFAULT

DESCRIPTION

21 (15h)

8

0

EQ Band 4 Bandwidth Control

0=narrow bandwidth

1=wide bandwidth

Output Signal

Path

7

0

Reserved

6:5

EQ4C

01

EQ Band 4 Centre Frequency:

Output Signal

Path

00=1.8kHz

01=2.4kHz

10=3.2kHz

11=4.1kHz

4:0

EQ4G

EQ5C

01100

EQ Band 4 Gain Control. See Table 36 for details.

Output Signal

Path

22 (16h)

8:7

6:5

00

01

Reserved

EQ Band 5 Cut-off Frequency:

00=5.3kHz

Output Signal

Path

01=6.9kHz

10=9kHz

11=11.7kHz

4:0

8

EQ5G

LIMEN

01100

0

EQ Band 5 Gain Control. See Table 36 for details.

Output Signal

Path

24 (18h)

Output Signal

Path

Enable the DAC digital limiter:

0=disabled

1=enabled

7:4

LIMDCY

0011

Output Signal

Path

DAC Limiter Decay time (per 6dB gain change) for

44.1kHz sampling. Note that these will scale with

sample rate:

0000=750us

0001=1.5ms

0010=3ms

0011=6ms

0100=12ms

0101=24ms

0110=48ms

0111=96ms

1000=192ms

1001=384ms

1010=768ms

3:0

LIMATK

0010

DAC Limiter Attack time (per 6dB gain change) for

44.1kHz sampling. Note that these will scale with

sample rate.

Output Signal

Path

0000=94us

0001=188s

0010=375us

0011=750us

0100=1.5ms

0101=3ms

0110=6ms

0111=12ms

1000=24ms

1001=48ms

1010=96ms

1011 to 1111=192ms

25 (19h)

8:7

00

Reserved

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REGISTER

ADDRESS

BIT

LABEL

LIMLVL

DEFAULT

DESCRIPTION

REFER TO

6:4

000

Output Signal

Path

Programmable signal threshold level (determines

level at which the DAC limiter starts to operate)

000=-1dB

001=-2dB

010=-3dB

011=-4dB

100=-5dB

101 to 111=-6dB

3:0

LIMBOOST

0000

Output Signal

Path

DAC Limiter volume boost (can be used as a

stand alone volume boost when LIMEN=0):

0000=0dB

0001=+1dB

0010=+2dB

… (1dB steps)

1011=+11dB

1100=+12dB

1101 to 1111=reserved

27 (1Bh)

8

NFU

0

Notch filter update. The notch filter values used

internally only update when one of the NFU bits is

set high.

Analogue to

Digital

Converter

(ADC)

7

NFEN

NFA0[13:7]

NFU

0

Analogue to

Digital

Converter

(ADC)

Notch filter enable:

0=Disabled

1=Enabled

6:0

8

0000000

0

Notch Filter a0 coefficient, bits [13:7]

Analogue to

Digital

Converter

(ADC)

28 (1Ch)

29 (1Dh)

30 (1Eh)

Notch filter update. The notch filter values used

internally only update when one of the NFU bits is

set high.

Analogue to

Digital

Converter

(ADC)

7

0

Reserved

6:0

NFA0[6:0]

NFU

0000000

Notch Filter a0 coefficient, bits [6:0]

Analogue to

Digital

Converter

(ADC)

8

0

Notch filter update. The notch filter values used

internally only update when one of the NFU bits is

set high.

Analogue to

Digital

Converter

(ADC)

7

0

Reserved

6:0

NFA1[13:7]

NFU

0000000

Notch Filter a1 coefficient, bits [13:7]

Analogue to

Digital

Converter

(ADC)

8

0

Notch filter update. The notch filter values used

internally only update when one of the NFU bits is

set high.

Analogue to

Digital

Converter

(ADC)

7

0

Reserved

6:0

NFA1[6:0]

0000000

Notch Filter a1 coefficient, bits [6:0]

Analogue to

Digital

Converter

(ADC)

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REFER TO

REGISTER

ADDRESS

BIT

LABEL

ALCSEL

DEFAULT

DESCRIPTION

ALC function select:

32 (20h)

8

0

Input Limiter/

Automatic

Level Control

(ALC)

0=ALC off

1=ALC on

7:6

5:3

00

Reserved

ALCMAXGAIN 111

Set Maximum Gain of PGA

111=+35.25dB

110=+29.25dB

101=+23.25dB

100=+17.25dB

011=+11.25dB

010=+5.25dB

Input Limiter/

Automatic

Level Control

(ALC)

001=-0.75dB

000=-6.75dB

2:0

ALCMINGAIN

000

Set minimum gain of PGA

000=-12dB

Input Limiter/

Automatic

Level Control

(ALC)

001=-6dB

010=0dB

011=+6dB

100=+12dB

101=+18dB

110=+24dB

111=+30dB

33 (21h)f

7:4

3:0

ALCHLD

ALCLVL

0000

1011

ALC hold time before gain is increased.

0000 = 0ms

Input Limiter/

Automatic

Level Control

(ALC)

0001 = 2.67ms

0010 = 5.33ms

… (time doubles with every step)

1111 = 43.691s

ALC target – sets signal level at ADC input

Input Limiter/

Automatic

Level Control

(ALC)

1111 : -1.5dBFS

1110 : -1.5dBFS

1101 : -3dBFS

1100 : -4.5dBFS

...... (-1.5dB steps)

0001 : -21dBFS

0000 : -22.5dBFS

34 (22h)

8

ALCMODE

0

Determines the ALC mode of operation:

0=ALC mode

Input Limiter/

Automatic

Level Control

(ALC)

1=Limiter mode

7:4

ALCDCY

[3:0]

0011

Decay (gain ramp-up) time

(ALCMODE ==0)

Input Limiter/

Automatic

Level Control

(ALC)

Per step

Per 6dB

90% of

range

0000

0001

0010

410us

820us

1.64ms

3.3ms

6.6ms

13.1ms

24ms

48ms

192ms

… (time doubles with every step)

1010 or

higher

420ms

3.36s

24.576s

0011

Decay (gain ramp-up) time

(ALCMODE ==1)

Per step

Per 6dB

726.4us

90% of

range

0000

90.8us

5.26ms

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REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

0001

0010

181.6us

363.2us

1.453ms

2.905ms

10.53ms

21.06ms

… (time doubles with every step)

1010 93ms 744ms

5.39s

3:0

ALCATK

0010

ALC attack (gain ramp-down) time

(ALCMODE == 0)

Input Limiter/

Automatic

Level Control

(ALC)

Per step

Per 6dB

90% of

range

0000

0001

0010

104us

208us

416us

832us

6ms

1.664ms

3.328ms

12ms

24.1ms

… (time doubles with every step)

1010 or

higher

106ms

852ms

6.18s

0010

ALC attack (gain ramp-down) time

(ALCMODE == 1)

Per step

Per 6dB

90% of

range

0000

0001

0010

22.7us

45.4us

90.8us

182.4us

363.2us

726.4us

1.31ms

2.62ms

5.26ms

… (time doubles with every step)

1010

23.2ms

186ms

1.348s

35 (23h)

8:4

3

00000

0

Reserved

NGEN

NGTH

ALC Noise gate function enable

1 = enable

Input Limiter/

Automatic

Level Control

(ALC)

0 = disable

2:0

000

ALC Noise gate threshold:

000=-39dB

Input Limiter/

Automatic

Level Control

(ALC)

001=-45dB

010=-51db

… (6dB steps)

111=-81dB

36 (24h)

8:5

4

0000

0

Reserved

PLL

0 = MCLK input not divided (default)

Master Clock

and Phase

Locked Loop

(PLL)

PRESCALE

1 = Divide MCLK by 2 before input to PLL

3:0

PLLN[3:0]

1000

Integer (N) part of PLL input/output frequency

ratio. Use values greater than 5 and less than 13.

Master Clock

and Phase

Locked Loop

(PLL)

37 (25h)

8:6

5:0

000

Reserved

PLLK[23:18]

PLLK[17:9]

PLLK[8:0]

01100

Fractional (K) part of PLL1 input/output frequency

ratio (treat as one 24-digit binary number).

Master Clock

and Phase

Locked Loop

(PLL)

38 (26h)

39 (27h)

8:0

01001001

1

Fractional (K) part of PLL1 input/output frequency

ratio (treat as one 24-digit binary number).

Master Clock

and Phase

Locked Loop

(PLL)

01110100

1

Fractional (K) part of PLL1 input/output frequency

ratio (treat as one 24-digit binary number).

Master Clock

and Phase

Locked Loop

(PLL)

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REFER TO

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

40 (28h)

8:0

00000000

0

Reserved

41 (29h)

8:4

3:0

00000

0000

Reserved

DEPTH3D

Stereo depth

3D Stereo

Enhancement

0000: 0% (minimum 3D effect)

0001: 6.67%

....

1110: 93.3%

1111: 100% (maximum 3D effect)

43 (2Bh)

8:6

5

000

0

Reserved

MUTERPGA

2INV

Mute input to INVROUT2 mixer

Analogue

Outputs

4

INVROUT2

0

Mute input to INVROUT2 mixer

Analogue

Outputs

3:1

BEEPVOL

000

AUXR input to ROUT2 inverter gain

000 = -15dB

Analogue

Outputs

...

111 = +6dB

0

8

BEEPEN

MBVSEL

0

0 = mute AUXR beep input

1 = enable AUXR beep input

Microphone Bias Voltage Control

0 = 0.9 * AVDD

Analogue

Outputs

44 (2Ch)

Input Signal

Path

1 = 0.6 * AVDD

7:3

2

00000

0

Reserved

L2_2INP

PGA

Connect L2 pin to input PGA positive terminal.

0=L2 not connected to input PGA

Input Signal

Path

1=L2 connected to input PGA amplifier positive

terminal (constant input impedance).

1

0

LIN2INP

PGA

1

Connect LIN pin to input PGA negative terminal.

0=LIN not connected to input PGA

Input Signal

Path

1=LIN connected to input PGA amplifier negative

terminal.

LIP2INP

PGA

Connect LIP pin to input PGA amplifier positive

terminal.

Input Signal

Path

0 = LIP not connected to input PGA

1 = input PGA amplifier positive terminal

connected to LIP (constant input impedance)

45 (2Dh)

8

7

INPPGA

UPDATE

N/A

0

INPPGAVOLL and INPPGAVOLR volume do not

update until a 1 is written to INPPGAUPDATE (in

reg 45 or 46)

Input Signal

Path

INPPGAZCL

Input PGA zero cross enable:

Input Signal

Path

0=Update gain when gain register changes

1=Update gain on 1^stzero cross after gain register

write.

6

INPPGA

MUTEL

0

Mute control for input PGA:

Input Signal

Path

0=Input PGA not muted, normal operation

1=Input PGA muted (and disconnected from the

following input BOOST stage).

5:0

INPPGA

VOLL

010000

Input PGA volume

000000 = -12dB

000001 = -11.25db

.

Input Signal

Path

010000 = 0dB

.

111111 = 35.25dB

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REGISTER

ADDRESS

BIT

8:0

8

LABEL

DEFAULT

DESCRIPTION

REFER TO

46 (2Eh)

00001000

0

Reserved

47 (2Fh)

PGA

1

Boost enable for input PGA:

Input Signal

Path

BOOSTL

0 = PGA output has +0dB gain through input

BOOST stage.

1 = PGA output has +20dB gain through input

BOOST stage.

7

0

Reserved

6:4

L2_2

000

Controls the L2 pin to the input boost stage:

000=Path disabled (disconnected)

001=-12dB gain through boost stage

010=-9dB gain through boost stage

…

Input Signal

Path

BOOSTVOL

111=+6dB gain through boost stage

3

0

Reserved

2:0

AUXL2

000

Controls the auxilliary amplifer to the input boost

stage:

Input Signal

Path

BOOSTVOL

000=Path disabled (disconnected)

001=-12dB gain through boost stage

010=-9dB gain through boost stage

…

111=+6dB gain through boost stage

48 (30h)

49 (31h)

8:0

10000000

0

Reserved

8:7

6

00

0

Reserved

DACL2RMIX

DACR2LMIX

Left DAC output to right output mixer

0 = not selected

Analogue

Outputs

1 = selected

5

4

0

Right DAC output to left output mixer

0 = not selected

Analogue

Outputs

1 = selected

OUT4

0 = OUT4 output gain = -1;

DC = AVDD / 2

Analogue

Outputs

BOOST

1 = OUT4 output gain = +1.5

DC = 1.5 x AVDD / 2

0 = OUT3 output gain = -1;

DC = AVDD / 2

3

2

OUT3

0

Analogue

Outputs

BOOST

1 = OUT3 output gain = +1.5

DC = 1.5 x AVDD / 2

0 = speaker gain = -1;

DC = AVDD / 2

SPKBOOST

Analogue

Outputs

1 = speaker gain = +1.5;

DC = 1.5 x AVDD / 2

1

0

TSDEN

VROI

1

0

Thermal Shutdown Enable

0 : thermal shutdown disabled

1 : thermal shutdown enabled

Analogue

Outputs

VREF (AVDD/2 or 1.5xAVDD/2) to analogue

output resistance

Analogue

Outputs

0: approx 1kΩ

1: approx 30 kΩ

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REFER TO

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

50 (32h)

8:6

AUXLMIX

VOL

000

Aux left channel input to left mixer volume control:

Analogue

Outputs

000 = -15dB

001 = -12dB

…

101 = 0dB

110 = +3dB

111 = +6dB

5

AUXL2L

MIX

0

Left Auxilliary input to left channel output mixer:

0 = not selected

Analogue

Outputs

1 = selected

4:2

BYPLMIX

VOL

000

Bypass volume contol to left output channel mixer: Analogue

Outputs

000 = -15dB

001 = -12dB

…

101 = 0dB

110 = +3dB

111 = +6dB

1

BYPL2L

MIX

0

Bypass path (from the input boost output) to left

output mixer

Analogue

Outputs

0 = not selected

1 = selected

0

DACL2L

MIX

1

Left DAC output to left output mixer

0 = not selected

Analogue

Outputs

1 = selected

51 (33h)

8:6

AUXRMIX

VOL

000

Aux right channel input to right mixer volume

control:

Analogue

Outputs

000 = -15dB

001 = -12dB

…

101 = 0dB

110 = +3dB

111 = +6dB

5

AUXR2R

MIX

0

Right Auxilliary input to right channel output mixer:

Analogue

Outputs

0 = not selected

1 = selected

4:1

0

0000

1

Reserved

DACR2R

MIX

Right DAC output to right output mixer

0 = not selected

1 = selected

Analogue

Outputs

52 (34h)

8

7

HPVU

N/A

0

LOUT1 and ROUT1 volumes do not update until a

1 is written to HPVU (in reg 52 or 53)

Analogue

Outputs

LOUT1ZC

Headphone volume zero cross enable:

1 = Change gain on zero cross only

0 = Change gain immediately

Left headphone output mute:

0 = Normal operation

1 = Mute

Analogue

Outputs

6

LOUT1

MUTE

0

Analogue

Outputs

5:0

LOUT1VOL

111001

Left headphone output volume:

000000 = -57dB

Analogue

Outputs

...

111001 = 0dB

...

111111 = +6dB

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REGISTER

ADDRESS

BIT

LABEL

HPVU

DEFAULT

DESCRIPTION

REFER TO

53 (35h)

54 (36h)

55 (37h)

56 (38h)

8

N/A

0

LOUT1 and ROUT1 volumes do not update until a

1 is written to HPVU (in reg 52 or 53)

Analogue

Outputs

7

ROUT1ZC

Headphone volume zero cross enable:

1 = Change gain on zero cross only

0 = Change gain immediately

Right headphone output mute:

0 = Normal operation

1 = Mute

Analogue

Outputs

6

ROUT1

MUTE

0

Analogue

Outputs

5:0

ROUT1VOL

111001

Right headphone output volume:

000000 = -57dB

Analogue

Outputs

...

111001 = 0dB

...

111111 = +6dB

8

7

SPKVU

N/A

0

LOUT2 and ROUT2 volumes do not update until a

1 is written to SPKVU (in reg 54 or 55)

Analogue

Outputs

LOUT2ZC

Speaker volume zero cross enable:

1 = Change gain on zero cross only

0 = Change gain immediately

Left speaker output mute:

0 = Normal operation

1 = Mute

Analogue

Outputs

6

LOUT2

MUTE

0

Analogue

Outputs

5:0

LOUT2VOL

111001

Left speaker output volume:

000000 = -57dB

Analogue

Outputs

...

111001 = 0dB

...

111111 = +6dB

8

7

SPKVU

N/A

0

LOUT2 and ROUT2 volumes do not update until a

1 is written to SPKVU (in reg 54 or 55)

Analogue

Outputs

ROUT2ZC

Speaker volume zero cross enable:

1 = Change gain on zero cross only

0 = Change gain immediately

Right speaker output mute:

0 = Normal operation

1 = Mute

Analogue

Outputs

6

ROUT2

MUTE

0

Analogue

Outputs

5:0

ROUT2VOL

111001

Right speaker output volume:

000000 = -57dB

Analogue

Outputs

...

111001 = 0dB

...

111111 = +6dB

8:7

6

00

0

Reserved

OUT3MUTE

0 = Output stage outputs OUT3 mixer

Analogue

Outputs

1 = Output stage muted – drives out VMID. Can

be used as VMID buffer in this mode.

5:4

3

00

0

Reserved

OUT4_2OUT3

BYPL2OUT3

OUT4 mixer output to OUT3

0 = disabled

Analogue

Outputs

1= enabled

2

0

ADC input to OUT3

0 = disabled

Analogue

Outputs

1= enabled

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REFER TO

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Left DAC mixer to OUT3

1

LMIX2OUT3

0

Analogue

Outputs

0 = disabled

1= enabled

0

LDAC2OUT3

OUT4MUTE

1

Left DAC output to OUT3

0 = disabled

Analogue

Outputs

1= enabled

57 (39h)

8:7

6

00

0

Reserved

0 = Output stage outputs OUT4 mixer

Analogue

Outputs

1 = Output stage muted – drives out VMID. Can

be used as VMID buffer in this mode.

5

4

HALFSIG

0

0=OUT4 normal output

1=OUT4 attenuated by 6dB

Left DAC mixer to OUT4

0 = disabled

Analogue

Outputs

LMIX2OUT4

Analogue

Outputs

1= enabled

3

LDAC2OUT4

0

Left DAC to OUT4

0 = disabled

Analogue

Outputs

1= enabled

2

1

0

Reserved

RMIX2OUT4

RDAC2OUT4

Right DAC mixer to OUT4

0 = disabled

Analogue

Outputs

1= enabled

0

1

Right DAC output to OUT4

0 = disabled

Analogue

Outputs

1= enabled

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DIGITAL FILTER CHARACTERISTICS

PARAMETER

ADC Filter

TEST CONDITIONS

MIN

TYP

MAX

0.454fs

+/- 0.025

UNIT

Passband

+/- 0.025dB

-6dB

0

0.5fs

Passband Ripple

Stopband

dB

0.546fs

-60

Stopband Attenuation

Group Delay

f > 0.546fs

21/fs

ADC High Pass Filter

High Pass Filter Corner

Frequency

-3dB

3.7

Hz

-0.5dB

10.4

-0.1dB

21.6

DAC Filter

Passband

+/- 0.035dB

-6dB

0

0.454fs

0.5fs

Passband Ripple

Stopband

+/-0.035

dB

0.546fs

-55

Stopband Attenuation

Group Delay

f > 0.546fs

29/fs

Table 70 Digital Filter Characteristics

TERMINOLOGY

1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)

2. Pass-band Ripple – any variation of the frequency response in the pass-band region

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DAC FILTER RESPONSES

3.05

3

20

0

2.95

2.9

-20

-40

2.85

2.8

-60

-80

2.75

2.7

-100

-120

-140

-160

2.65

2.6

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.5

1

1.5

Frequency (fs)

2

2.5

Frequency (fs)

Figure 40 DAC Digital Filter Frequency Response

(128xOSR)

Figure 41 DAC Digital Filter Ripple (128xOSR)

3.05

3

20

0

2.95

2.9

-20

-40

2.85

2.8

-60

-80

2.75

2.7

-100

-120

-140

-160

2.65

2.6

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.5

1

1.5

Frequency (fs)

2

2.5

Frequency (fs)

Figure 42 DAC Digital Filter Frequency Response (64xOSR) Figure 43 DAC Digital Filter Ripple (64xOSR)

ADC FILTER RESPONSES

0.2

0

0.15

-20

-40

0.1

0.05

0

-60

-0.05

-0.1

-0.15

-0.2

-80

-100

-120

0

0.1

0.2

0.3

0.4

0.5

0

0.5

1

1.5

2

2.5

3

Frequency (Fs)

Figure 44 ADC Digital Filter Frequency Response

Figure 45 ADC Digital Filter Ripple

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HIGHPASS FILTER

The WM8976 has a selectable digital highpass filter in the ADC filter path. This filter has two

modes, audio and applications. In audio mode the filter is a 1^storder IIR with a cut-off of around

3.7Hz. In applications mode the filter is a 2^ndorder high pass filter with a selectable cut-off

frequency.

5

0

-5

-10

-15

-20

-25

-30

-35

-40

0

5

10

15

20

25

30

35

40

45

Frequency (Hz)

Figure 46 ADC Highpass Filter Response, HPFAPP=0

10

0

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-10

-20

-30

-40

-50

-60

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

Frequency (Hz)

Figure 47 ADC Highpass Filter Responses (48kHz),

HPFAPP=1, all cut-off settings shown.

Figure 48 ADC Highpass Filter Responses (24kHz),

HPFAPP=1, all cut-off settings shown.

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

0

200

400

600

800

1000

1200

Frequency (Hz)

Figure 49 ADC Highpass Filter Responses (12kHz),

HPFAPP=1, all cut-off settings shown.

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5-BAND EQUALISER

The WM8976 has a 5-band equaliser which can be applied to either the ADC path or the DAC path.

The plots from Figure 50 to Figure 63 show the frequency responses of each filter with a sampling

frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of ±12dB, and

secondly a sweep of the gain from -12dB to +12dB for the lowest cut-off/centre frequency of each

filter.

15

10

5

15

10

5

0

-5

-10

-15

10^-1

10⁰

10¹

10²

10³

10⁴

10⁵

10^-1

10⁰

10¹

10²

10³

10⁴

10⁵

Frequency (Hz)

Figure 50 EQ Band 1 Low Frequency Shelf Filter Cut-offs

Figure 51 EQ Band 1 Gains for Lowest Cut-off Frequency

15

10

5

15

10

5

0

-5

-10

-15

10^-1

10⁰

10¹

10²

10³

10⁴

10⁵

10^-1

10⁰

10¹

10²

10³

10⁴

10⁵

Frequency (Hz)

Figure 52 EQ Band 2 – Peak Filter Centre Frequencies,

EQ2BW=0

Figure 53 EQ Band 2 – Peak Filter Gains for Lowest Cut-off

Frequency, EQ2BW=0

15

10

5

0

-5

-10

-15

10^-2

10^-1

10⁰

10¹

10²

10³

10⁴

Frequency (Hz)

Figure 54 EQ Band 2 – EQ2BW=0, EQ2BW=1

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15

10

5

15

10

5

0

-5

-10

-15

10^-1

10⁰

10¹

10²

10³

10⁴

10⁵

10^-1

10⁰

10¹

10²

10³

10⁴

10⁵

Frequency (Hz)

Figure 55 EQ Band 3 – Peak Filter Centre Frequencies, EQ3BFigure 56 EQ Band 3 – Peak Filter Gains for Lowest Cut-off

Frequency, EQ3BW=0

15

10

5

0

-5

-10

-15

10^-2

10^-1

10⁰

10¹

10²

10³

10⁴

Frequency (Hz)

Figure 57 EQ Band 3 – EQ3BW=0, EQ3BW=1

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15

10

5

15

10

5

0

-5

-10

-15

10^-1

10⁰

10¹

10²

10³

10⁴

10⁵

10^-1

10⁰

10¹

10²

10³

10⁴

10⁵

Frequency (Hz)

Figure 58 EQ Band 4 – Peak Filter Centre Frequencies, EQ3BFigure 59 EQ Band 4 – Peak Filter Gains for Lowest Cut-off

Frequency, EQ4BW=0

15

10

5

0

-5

-10

-15

10^-2

10^-1

10⁰

10¹

10²

10³

10⁴

Frequency (Hz)

Figure 60 EQ Band 4 – EQ3BW=0, EQ3BW=1

15

10

5

15

10

5

0

-5

-10

-15

10^-1

10⁰

10¹

10²

10³

10⁴

10⁵

10^-1

10⁰

10¹

10²

10³

10⁴

10⁵

Frequency (Hz)

Figure 61 EQ Band 5 High Frequency Shelf Filter Cut-offs Figure 62 EQ Band 5 Gains for Lowest Cut-off Frequency

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Figure 63 shows the result of having the gain set on more than one channel simultaneously. The

blue traces show each band (lowest cut-off/centre frequency) with ±12dB gain. The red traces show

the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EqxBW=0 for the

peak filters.

20

15

10

5

0

-5

-10

-15

10^-1

10⁰

10¹

10²

10³

10⁴

10⁵

Frequency (Hz)

Figure 63 Cumulative Frequency Boost/Cut

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APPLICATION INFORMATION

RECOMMENDED EXTERNAL COMPONENTS

Figure 64 Recommended External Component Diagram

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WM8976

PACKAGE DIAGRAM

FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH

DM033.D

D

DETAIL 1

D2

32

25

L

1

24

INDEX AREA

(D/2 X E/2)

4

EXPOSED

GROUND

PADDLE

6

A

E2

E

17

8

aaa

C

2 X

16 15

9

1

bbb

b

aaa

C

2 X

B

M

C

A

B

e

TOP VIEW

BOTTOM VIEW

ccc

C

A3

A

5

0.08

C

R = 0.3MM

A1

C

SIDE VIEW

SEATING PLANE

EXPOSED

GROUND

DETAIL 2

PADDLE

W

T

A3

DETAIL 1

G

H

b

Exposed lead

Half etch tie bar

DETAIL 2

Dimensions (mm)

Symbols

NOM

0.90

0.02

0.20 REF

0.25

MIN

0.80

MAX

1.00

0.05

NOTE

A

A1

A3

b

0

1

0.18

3.30

0.30

3.55

D

5.00

2

D2

E

E2

3.45

5.00

3.45

3.55

e

0.50 BSC

0.213

G

H

L

0.1

0.40

0.1

0.30

0.50

T

W

0.2

Tolerances of Form and Position

aaa

bbb

ccc

0.15

0.10

REF:

JEDEC, MO-220, VARIATION VHHD-5.

NOTES:

1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP.

2. FALLS WITHIN JEDEC, MO-220, VARIATION VHHD-5.

3. ALL DIMENSIONS ARE IN MILLIMETRES.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002.

5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.

7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

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IMPORTANT NOTICE

Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or

service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing

orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale

supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation

of liability.

WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s

standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support

this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by

government requirements.

In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used

by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical

components in life support devices or systems without the express written approval of an officer of the company. Life

support devices or systems are devices or systems that are intended for surgical implant into the body, or support or

sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be

reasonably expected to result in a significant injury to the user. A critical component is any component of a life support

device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that

any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual

property right of WM covering or relating to any combination, machine, or process in which such products or services might

be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s

approval, license, warranty or endorsement thereof.

Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and

is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this

information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive

business practice, and WM is not responsible nor liable for any such use.

Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that

product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and

deceptive business practice, and WM is not responsible nor liable for any such use.

ADDRESS:

Wolfson Microelectronics plc

Westfield House

26 Westfield Road

Edinburgh

EH11 2QB

United Kingdom

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Email :: sales@wolfsonmicro.com

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型号：	WM8976_06
厂家：	WOLFSON MICROELECTRONICS PLC
描述：	Stereo CODEC With Speaker Driver 立体声编解码器，扬声器驱动器解码器驱动器编解码器
文件：	总108页 (文件大小：1227K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

WM8976_06 [WOLFSON]

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