WPMDB1600362Q [WURTH]
Variable Step Down Regulator Module;
| 型号： | WPMDB1600362Q |
| 厂家： | 
WURTH ELEKTRONIK GMBH & CO. KG, GERMANY. |
| 描述： | Variable Step Down Regulator Module |
| 文件： | 总29页 (文件大小：1921K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WPMDB1400362Q / 171040302
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
2.95 – 6V / 4A / 0.8 – 3.6V Output
DESCRIPTION
FEATURES
Peak efficiency up to 96%
The Magi3C 171020302, 171040302 and 171060302
Power Module family provide a fully integrated DC-DC
power supply including the switching regulator, regulation
loop, power mosfets and shielded inductor in one
package. This modules require as few as 3 external
components
Current capability up to 4A
Output voltage range: 0.8 to 3.6V
Current Mode control
Synchronuos operation
1% reference accuracy over temperature
Adjustable switching frequency (0.5 to 2 MHz)
Continuous output power: 14.4W
No derating within the operating temperature range
Integrated shielded inductor
The 171040302 offers high efficiency and delivers up to
4A of output current. It operates from 2.95 to 6V input
voltage and is designed for fast transient response.
Under-voltage lockout protection
Programmable soft-start and voltage tracking
Frequency synchronization to external clock
Thermal shutdown
It is available in a standard industrial high power density
QFN package (11mm x 9mm x 2.8mm) with very good
thermal performance.
Operating ambient temperature up to 85°C
Inrush current protection
This module has an on-board protection circuitry to guard
against thermal overstress and electrical damage
featuring thermal shut-down, over-current, short-circuit,
over-voltage and under-voltage protections.
Adjustable soft start and sequencing
Cycle by cycle short circuit protection
Under-voltage and over-voltage Power Good
Pin compatible with WE171040302 & WE171060302
Complies with EN55022 class B radiated emissions
standard
TYPICAL APPLICATIONS
Point-of-load DC-DC applications from 5V and 3.3V
rails
Industrial, test & measurement, medical applications
System power supplies
DSPs, FPGAs, MCUs and MPU supply
I/O interface power supply
Communication infrastructure
High density distributed power systems
TYPICAL CIRCUIT DIAGRAM
VIN
VIN
VOUT
VSENSE+
VADJ
VOUT
27
28
6
36
PG
35
ENABLE
SS/TR
INTSS
RT/CLK
CIN
RSET
COUT
7
AGND
PGND
4
RRT
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WPMDB1400362Q / 171040302
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
PACKAGE
VIN 30
VIN 31
18 SW
39 SW
17 SW
VIN 32
37
16 NC
GND
15 NC
AGND 33
AGND 34
VADJ/FB 35
VSENSE+ 36
14 VOUT
13 VOUT
12 VOUT
38 VOUT
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WPMDB1400362Q / 171040302
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
PIN DESCRIPTION
SYMBOL
PIN
TYPE
DESCRIPTION
VIN
30,31,32
Power Input Voltage. Place input capacitors as close as possible
8,9,10,11,
12,13,14,38
Output voltage. Place output capacitors as close as possible. For thermal
performance use copper plane(s) at these pins.
VOUT
Power
AGND
PGND
5,7,33,34
Supply Analog ground for internal circuitry. Connect to power ground
Power ground for the internal switching circuitry. Connect to copper plane(s) with
37
Power
thermal vias for thermal performance.
Connect to positive terminal of the output capacitor. An internal resistor of 1430 Ω is
VSENSE+
36
Input
connected internally between VSENSE+ and VADJ. This is the upper resistor of the
feedback voltage divider.
A resistor (RSET) from VADJ to AGND is needed to select the output voltage. This is
the lower resistor of the feedback voltage divider.
An external resistor from RT/CLK to AGND adjusts the switching frequency of the
device.
VADJ
35
4
Input
Input
RT/CLK
INTRRT
RCOMP
5
1
analog Internal resistor which defines the default switching frequency.
analog Internal resistor of the compensation network. Must be connected to AGND.
OPTIONAL
SYMBOL
PIN
TYPE
DESCRIPTION
An internal under-voltage lock out resistor of 34kΩ is connected to the enable pin. If
connected to analog ground, the internal UVLO resistor divider will be activated. For
input voltages below 3.3V this pin should be left open and optional a resistor from
enable to analog ground sets the UVLO to values between 2.95 and 3.3 V.
Enable pin. Internally pull up source. Pull to analog ground to disable. Float to
Enable.
UVLO
29
Input
ENABLE
PGOOD
28
27
Input
Open drain output. The PGOOD pin pulls low during thermal shutdown, over-
Output current, output over-voltage or under-voltage or disabled device. A pull up resistor is
required.
Internal current source. Connect an external capacitor to optionally increase the soft
start time. A voltage applied to this pin allows tracking and sequencing.
SS/TR
INTSS
6
7
Input
An internal 3.3nF capacitor is connected to this pin. If pin 7 is connected to analog
ground, a 1.1ms soft start time is selected.
analog
AUXILIARY
SYMBOL
PIN
TYPE
DESCRIPTION
Output of the error amplifier. If an external compensation is used, pin 1 must be left
open.
COMP
3
Output
CCOMP
BOOT
2
analog Internal capacitor of the compensation network. Do not connect.
Supply Internal bootstrap pin for the high side mosfet.
26
17,18,19,20
,21,22,23,
24,25,39
SWITCH
NC
Power Internal switch node. Do not connect these pins.
Not connected to internal circuitry.
15,16
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WPMDB1400362Q / 171040302
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
ORDERING INFORMATION
ORDER CODE
PART DESCRIPTION
SPECIFICATIONS
PACKAGE
PACKAGING UNIT
171040302
WPMDB1400362Q
4A / 14.5W version
BQFN-39
Tape and Reel with 250 units
PIN COMPATIBLE FAMILY MEMBERS
ORDER CODE
171020302
PART DESCRIPTION
WPMDB1200362Q
WPMDB1600362Q
SPECIFICATIONS
2A / 7.2W version
6A / 21.6W version
PACKAGE
BQFN-39
BQFN-39
PACKAGING UNIT
Tape and Reel with 250 units
Tape and Reel with 250 units
171060302
PACKAGE SPECIFICATIONS
Weight
Flammability
MTBF
0.85g
Meets UL 94 V-O
32.8Mhrs, Bellcore TR-332, 50% stress, TA=40°C, ground benign
SALES INFORMATION
SALES CONTACTS
Würth Elektronik eiSos GmbH & Co. KG
EMC & Inductive Solutions
Max-Eyth-Str. 1
74638 Waldenburg
Germany
Tel. +49 (0) 7942 945 0
www.we-online.com
powermodules@we-online.com
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WPMDB1400362Q / 171040302
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
ABSOLUTE MAXIMUM RATINGS
Caution:
Exceeding the listed absolute maximum ratings may affect the device negatively and may cause permanent damage.
LIMITS
SYMBOL
PARAMETER
UNIT
MIN (1)
-0.3
-0.6
-0.3
-0.3
-0.3
-
MAX (1)
VIN
VOUT
VADJ
Input voltage
7
VIN
3
V
V
Output voltage
Feedback voltage
V
UVLO
Under-voltage lockout pin voltage
Enable pin Voltage
3.3
7
V
V
EN
Enable source current
100
6
µA
V
RT/CLK pin voltage
-0.3
-
RT/CLK
SS/TR
PGOOD
COMP
RT/CLK source current
±100
3
µA
V
SS/TR pin voltage
-0.3
-
SS/TR pin sink current
±100
7
µA
V
Power Good pin voltage
Power Good sink current
Output of the error amplifier
COMP sink current
-0.3
-
10
3
mA
V
-0.3
-
100
3
µA
V
INTSS
INTRRT
RCOMP
CCOMP
VSENSE+
VSW
Internal soft start capacitor
Internal resistor for the initial switching frequency
Resistor of the compensation network
Capacitor of the compensation network
Sense for the output voltage.
Switch node voltage
-0.3
-0.3
-0.3
-0.3
-0.3
-0.6
-2
6
V
3
V
3
V
Vout
7
V
V
SW
10ns transient
7
V
VSW
+8V
BOOT
Tstorage
TSOLR
Internal supply for the high mosfet driver
-
-65
-
V
Storage temperature
150
°C
°C
Peak case/leads temperature during reflow soldering, max. 30sec.
(JEDEC J-STD020) Maximum three cycles!
245±5
Mechanical shock: Mil-STD-883D, Method 2002.2, 1ms, ½ sine, mounted
Mechanical vibration: Mil-STD-883D, Method 2007.2, 20-2000Hz
-
-
1500
20
G
G
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WPMDB1400362Q / 171040302
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
OPERATING CONDITIONS
Operating conditions are conditions under which operation of the device is intended to be functional. All values are
referenced to GND.
MIN and MAX limits are valid for the recommended ambient temperature range of -40°C to 85°C. Typical values represents
statistically the utmost probability at following conditions: VIN = 3.3V, VOUT = 1.8V, IOUT = 2A, CIN1 = 47µF ceramic, CIN2
220µF poly-tantalum, COUT1 = 47µ ceramic, COUT2 = 100µF poly-tantalum unless otherwise noted.
=
SYMBOL
PARAMETER
MIN (1)
TYP (2)
MAX (1)
UNIT
VIN
Input voltage
2.95
-
6
V
Output voltage (depending on input voltage and switching
frequency)
VOUT
0.8
-
3.6
V
85 (3)
125
TA
Ambient temperature range
Junction temperature range
-40
-40
-
-
°C
°C
TJOP
THERMAL SPECIFICATIONS
SYMBOL
PARAMETER
TYP (2)
12
UNIT
°C/W
°C/W
°C/W
°C
Junction-to-ambient thermal resistance (4)
Junction-to-top(5)
Junction-to-board(6)
ӨJA
ΨJT
ΨJB
2.2
9.7
Thermal shutdown, rising
175
15
TSD
Thermal shutdown hysteresis, falling
°C
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WPMDB1400362Q / 171040302
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
ELECTRICAL SPECIFICATIONS
MIN and MAX limits are valid for the recommended ambient temperature range of -40°C to 85°C. Typical values represents
statistically the utmost probability at following conditions: VIN = 3.3V, VOUT = 1.8V, IOUT = 2A, CIN1 = 47µF ceramic, CIN2
220µF poly-tantalum, COUT1 = 47µ ceramic, COUT2 = 100µF poly-tantalum unless otherwise noted.
=
SYMBOL
PARAMETER
TEST CONDITIONS
Output current
MIN (1)
TYP (2)
MAX (1)
UNIT
IOCP
Output current protection
-
7
-
A
Accuracy
TA = 25°C, IOUT = 0A
with internal feedback resistor
±1(7)
Internal accuracy
Temperature variation
Line regulation
-
-
-
-
%
%
%
VREF
-40°C≤TA≤85°C, IOUT = 0A
±0.3
±0.1
-
-
Over VIN range, TA = 25°C, IOUT
= 0A
Load regulation
Total output voltage variation
Output voltage ripple
Over IOUT range, TA = 25°C
-
-
-
±0.1
-
±1.5
-
%
%
VOUT
-
10µF ceramic, 20MHz BW (8)
9
mVpp
Switching frequency
Using RT mode
500
400
-
2000
600
kHz
kHz
fSW
Switching frequency
RT/CLK pin open
500
Synchronization clock
frequency range
500
-
2000
kHz
fCLK
Using CLK mode
Relative to AGND
Minimum CLK pulse width
RT/CLK high threshold
RT/CLK low threshold
RT/CLK to switch node delay
PLL lock-in-time
75
2.2
-0.3
-
-
-
-
3.3
0.4
-
ns
V
VCLK-H
VCLK-L
-
V
90
14
ns
µs
fCLK
-
-
Enable and under-voltage lockout
VIN increasing, UVLO pin
connected to AGND
-
3.05
2.75
3.135
-
V
V
VUVLO
VIN under-voltage threshold
Enable threshold trip point
VIN decreasing, UVLO pin
connected to AGND
2.5
Enable logic high voltage
Enable logic low voltage
-
1.25
-
-
V
V
VENABLE
-0.3
1.0
Power Good
VOUT rising, VOUT GOOD
VOUT rising, VOUT FAULT
VOUT falling, VOUT GOOD
VOUT falling, VOUT FAULT
IPG = 0.33mA
-
-
-
-
-
93
107
105
91
-
%
%
%
%
V
-
-
Power Good threshold
Power Good low voltage
PG
-
-
0.3
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
SYMBOL
PARAMETER
TEST CONDITIONS
Efficiency
MIN (1)
TYP (2)
MAX (1)
UNIT
VOUT = 3.3V, fSW = 1.0MHz
VOUT = 2.5V, fSW = 1.0MHz
VOUT = 1.8V, fSW = 1.0MHz
VOUT = 1.5V, fSW = 1.0MHz
VOUT = 1.2V, fSW = 750kHz
VOUT = 1.0V, fSW = 650kHz
VOUT = 0.8V, fSW = 650kHz
VOUT = 1.8V, fSW = 1.0MHz
VOUT = 1.5V, fSW = 1.0MHz
VOUT = 1.2V, fSW = 750kHz
VOUT = 1.0V, fSW = 650kHz
VOUT = 0.8V, fSW = 650kHz
-
-
-
-
-
-
-
-
-
-
-
-
95
93
91
89
97
85
84
90
88
87
84
82
-
-
-
-
-
-
-
-
-
-
-
-
%
%
%
%
%
%
%
%
%
%
%
%
VIN = 5V
IOUT = 1A
η
Efficiency
VIN = 3.3V
IOUT = 1A
Input and output capacitors
ceramic
47 (9)
-
-
µF
µF
CIN
External input capacitor
220 (9)
Non ceramic
-
-
47 (10)
650 (11)
100 (10) 2000(11)
ceramic
150
µF
External output cpacitor
Output capacitor ESR
COUT
Non ceramic
-
-
µF
-
25
mΩ
Transient Response
Recovery time
1A/µs load step from 1.0A to 3A
VOUT over/undershoot
TTR
TTR
-
-
80
90
-
-
µs
Transient Response
mV
1A/µs load step from 1.0A to 3A
Input standby current
IQ
Input quiescent current
Enable logic low
-
70
100
µA
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WPMDB1400362Q / 171040302
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
NOTES
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed
through correlation using Statistical Quality Control (SQC) methods.
(2) Typical numbers are valid at 25°C ambient temperature and represent statistically the utmost probability assuming the
Gaussian distribution.
(3) Depending on heat sink design, number of PCB layers, copper thickness and air flow.
(4) Measured on a 100 x 100mm two layer board, with 35µm (1 ounce) copper, no air flow
(5) The junction-to-top characterization parameter, ΨJT, estimates the junction temperature, TJ, of a device in a real system,
using a procedure described in JESD51-2A (sections 6 and 7). TJ = ΨJT * Pdis + TT; where Pdis is the power dissipated in
the device and TT is the temperature of the top of the device.
(6) The junction-to-board characterization parameter, ΨJB, estimates the junction temperature, TJ, of a device in a real
system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ΨJB * Pdis + TB; where Pdis is the power
dissipated in the device and TB is the temperature of the board 1mm from the device.
(7) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the
internal adjustment resistor. The overall output voltage tolerance is affected by the tolerance of the external RSET
resistor.
(8) The industry standard for comparison of the output voltage ripple between switching regulators or modules requires a
10µF ceramic (sometimes additional 1µF ceramic in parallel) at the point of load where the voltage measurement is
done using an oscilloscope with its probe and probe jack for low voltage/high frequency (low impedance) measurement.
The oscilloscopes bandwidth is limited at 20MHz.
(9) A minimum of 47µF of ceramic capacitance is required across the input for proper operation. Locate the capacitor
directly at VIN of the device. An additional 220µF of bulk capacitance is recommended.
(10) The amount of required output capacitance varies depending on the output voltage. The amount of required
capacitance must include at least 47µF of ceramic capacitance. Locate the capacitance close to the device. Adding
additional capacitance close to the load improves the response of the regulator to load transients.
(11) When using both ceramic and non-ceramic output capacitance, the combined maximum must not exceed 1200µF.
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WPMDB1400362Q / 171040302
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
TYPICAL PERFORMANCE CURVES
If not otherwise specified, the following conditions apply: VIN = 3.3V - 5V; CIN = 2 x 47µF X7R ceramic; COUT = 2x 47µF X7R
ceramic, TAMB = 25°C.
RADIATED EMISSIONS EN55022 (CISPR-22) CLASS B COMPLIANT
Measured on module with PCB and without external filters at 3m antenna distance
70
Radiated Emissions
VIN = 5V, VOUT = 1.8V, fSW = 1MHz, ILOAD = 4A
60
EN55022 Class B
Horizontal
Vertical
50
40
30
20
10
0
30
100
1000
FREQUENCY [MHz]
Measured on module with PCB and without external filters at 3m antenna distance
70
Radiated Emissions
VIN = 3.3V, VOUT = 1.8V, fSW = 1MHz, ILOAD = 4A
60
EN55022 Class B
Horizontal
Vertical
50
40
30
20
10
0
30
100
1000
FREQUENCY [MHz]
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WPMDB1400362Q / 171040302
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
INPUT VOLTAGE 5V
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
INPUT VOLTAGE 3.3V
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
BLOCK DIAGRAM
Cboot
1µH
VOUT
VIN
CIN
VOUT
VSENSE+
36
35
48.7k
100n
34k
Controller/
Power Control/
Protection
COUT
1430Ω
VADJ
28
29
27
ENABLE
Circuitry
RSET
UVLO
PG
REF
7 6 5 4
1 2 3
CIRCUIT DESCRIPTION
The MagI³C Power Module 171020302 is based on a synchronous step down regulator with integrated MOSFETs and a
power inductor. The control scheme is based on a Current Mode (CM) regulation loop.
The VOUT of the regulator is divided with the feedback resistor network of internal 1430Ω and external RSET and fed into the
VADJ pin. The error amplifier compares this signal with the internal 0.803V reference. The error signal is amplified and
controls the on-time of a fixed frequency pulse with generator. This signal drives the power mosfets.
The Current Mode architecture features a constant frequency during load steps. Only the on-time is modulated. It is
internally compensated and stable with low ESR output capacitors and requires no external compensation network.
This architecture supports fast transient response and very small output ripple values of 10ths of millivolts are achieved.
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WPMDB1400362Q / 171040302
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
DESIGN FLOW
The next 10 simple steps will show how to select the external components to design your power application.
Essential Steps
1.
2.
3.
4.
Set output voltage
Set operating frequency
Select input capacitor
Select output capacitor
Optional Steps
5.
6.
7.
Select soft start capacitor
Select under-voltage lockout divider
Enable / Disable
8.
Voltage tracking
9.
10.
Synchronization to an external clock
Power Good
VIN
VIN
VOUT
VSENSE+
VADJ
VOUT
27
28
6
36
35
RUVLO1
10
9
PG
7
3
ENABLE
SS/TR
INTSS
RT/CLK
4
CIN
8
1
RSET
COUT
7
RUVLO2
6
AGND
PGND
4
5
CSS
RRT
2
Step 1 Setting the output voltage (VOUT
)
The output voltage is selected with a resistor divider across VADJ pin and AGND. The upper resistor of 1430 Ω of the
feedback voltage resistor divider is internal to the module. The output voltage adjustment range is from 0.8V to 3.6V.
0.8V∗1430Ω
푅푆퐸푇
=
(Ω) (1)
V
OUT
−0.8V
VOUT
3.3V
3.0V
2.5V
1.8V
1.5V
1620Ω
1.2V
1.0V
0.8V
open
RSET (E96)
453Ω
523Ω
665Ω
1130Ω
2870Ω
5620Ω
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WPMDB1400362Q / 171040302
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
Step 2 Setting the operating frequency (fSW
)
The switching frequency must be selected according to input voltage, output voltage and load current for the best
performance in loop regulation and transient response.
Note: RRT open (fSW = 500 kHz) is only allowed under specific conditions per below table!
VIN = 5V
VIN = 3.3V
IOUT = 0 to 4A
VOUT RANGE [V]
IOUT = 0 to 3.5A
VOUT RANGE [V]
IOUT > 3.5A
OPERATING
FREQUENCY
[kHz]
VOUT RANGE [V]
RRT [kΩ]
open
3400
1800
1200
887
MIN
0.8
0.8
0.8
0.8
0.8
0.9
0.9
1.0
1.2
1.4
1.7
2.0
2.3
MAX
MIN
0.8
0.8
0.8
0.8
0.8
0.9
0.9
1.0
1.2
1.4
1.7
2.0
2.3
MAX
1.0
1.1
1.2
1.4
1.6
1.8
2.1
3.6
3.6
3.6
3.6
3.6
3.3
MIN
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
1.0
1.1
1.3
1.5
MAX
2.2
2.4
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.4
2.3
2.2
2.2
500
550
1.4
1.6
1.8
2.1
2.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.4
600
650
700
750
715
800
590
900
511
1000
1250
1500
1750
2000
348
232
174
137
113
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VDRM – Variable Step Down Regulator Module
Step 3 Select input capacitor (CIN)
The 171020302 MagI³C power module contains an 100nF internal input capacitor for good EMI performance. Additional
input capacitance is required external to the MagI3C power module to handle the input ripple current of the application.
Therefore an external input capacitance placed directly at the VIN pin is required to handle the input ripple current of the
application. The input capacitor can be several capacitors in parallel. Input capacitor selection is generally directed to satisfy
the input ripple current requirements rather than by capacitance value. Input ripple current rating is dictated by the equation:
1
퐷
푉
ꢄꢅꢆ
퐼퐶
≈ ∗ 퐼푂푈푇 ∗ √1−퐷 (2) where ꢃ ≈
2 푉
ꢀ푁ꢁ푀ꢂ
ꢀ푁
As a point of reference, the worst case ripple current will occur when the module is presented with full load current and when
VIN = 2 x VOUT
.
Recommended minimum input capacitance is 4.4µF X7R ceramic with a voltage rating at least 25% higher than the
maximum applied input voltage for the application. It is also recommended that attention be paid to the voltage and
temperature deratings of the capacitor selected. It should be noted that ripple current rating of ceramic capacitors may be
missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating.
If the system design requires a certain minimum value of peak-to-peak input ripple voltage (ΔVIN) be maintained then the
following equation may be used:
ꢈ
∗퐷∗(1−퐷)
푉
ꢄꢅꢆ
ꢄꢅꢆ
ꢇꢈꢉ
≥
(3)
where ꢃ ≈
푉
ꢀ푁
CCM = continuous conduction mode
푓
∗∆푉
ꢂ푊
ꢀ푁
ꢊꢊ푀
Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and
parasitic inductance of the incoming supply lines.
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Step 4 Select output capacitor (COUT
)
None of the required output capacitance is integrated within the module. At a minimum, the output capacitor must meet the
worst case RMS current rating of ꢋ.5 ∗ 퐼퐿ꢌ푃푃 , as calculated in equation (4).
푉
∗(푉 −푉
ꢀ푁
)
ꢄꢅꢆ
ꢄꢅꢆ
∗푉
퐼퐿ꢌ
=
(4)
푃푃
1µ퐻∗푓
ꢂ푊 ꢀ푁
Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value
of 10µF is generally required. Please consider the derating of the nominal capacitance value dependent on the DC voltage
applied across it. Experimentation will be required if attempting to operate with a minimum value. Low ESR capacitors, such
as ceramic and polymer electrolytic capacitors are recommended.
∆ꢈ
∗푉 ∗퐿∗푉
ꢄꢅꢆ 퐴ꢍ퐽 ꢀ푁
ꢇ푂푈푇
≥
(5)
(
)
∗∆푉
4∗푉
∗ 푉 −푉
ꢄꢅꢆ
ꢀ푁
ꢄꢅꢆ
ꢄꢅꢆ
where ΔIOUT is the load step in A, and ΔVOUT is the maximum allowed voltage drop at the output voltage.
The ESR of the output capacitor affects the output voltage ripple. High ESR will result in larger VOUT peak-to-peak ripple
voltage. Furthermore, high output voltage ripple caused by excessive ESR can trigger the over-voltage protection monitored
at the VSENSE+ pin. The ESR should be chosen to satisfy the maximum desired VOUT peak-to-peak ripple voltage and to avoid
over-voltage protection during normal operation. The following equations can be used:
푉
ꢄꢅꢆ
ꢁꢀꢒꢒꢓꢔ
ꢎꢏ푅ꢐꢑ푋
≤
(6)
ꢈ
ꢓ
ꢁꢀꢒꢒꢓꢔ
Where ꢕ푂푈푇
is the maximal wanted output ripple generated by ESR and 퐼퐿
is the inductor ripple current
ꢌꢈ푃푃퐿퐸
ꢌꢈ푃푃퐿퐸
calculated in equation (4).
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Step 5 Select soft-start capacitor (CSS)
Connecting the INTSS pin to AGND and leaving SS/TR pin open enables the internal soft start capacitor with a soft-start
interval of approximately 1.1 ms. Adding additional capacitance between the SS/TR pin and AGND increases the soft-start
time according to the table below.
6
SS/TR
CSS
7
INTSS
CSS [nF]
Open
1.1
2.2
1.9
4.7
2.8
10
15
22
25
Soft Start [ms]
4.6
6.4
8.8
9.8
Step 6 Select under-voltage lockout divider
Pin 29 connected to analog ground
This connects the internal under-voltage lockout resistor divider. The enable rising threshold is typ. 1.25V. The enable falling
threshold is at 1V max. Use at least 10% safety tolerance. For 3.3V input voltage use a rising threshold of below 3V which is
achievable with pin 29 left open. An external under-voltage lockout resistor will set the rising threshold below 3V.
VIN
48.7kΩ
SHUTDOWN
LOGIC
28
29
VIN(UVLO) rising threshold typ. [V]
Hysteresis [mV]
3.14V
300
ENABLE
34kΩ
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Pin 29 connected to AGND with additional resistor to adjust under-voltage lockout.
VIN
48.7kΩ
SHUTDOWN
LOGIC
28
29
ENABLE
RUVLO
34kΩ
VIN(UVLO) rising threshold typ. [V]
RUVLO [kΩ]
3.25
294
325
3,5
133
335
3,75
4,0
63.4
355
4,25
49.9
365
4,5
42.2
375
4,75
35.7
385
86.6
345
Hysteresis [mV]
Pin 29 open with additional resistor to adjust under-voltage lockout for lower values.
VIN
48.7kΩ
SHUTDOWN
LOGIC
28
29
ENABLE
RUVLO
not used
VIN(UVLO) rising threshold typ. [V]
RUVLO [kΩ]
3.0
34.0
170
2.75
39.7
156
2.5
2.25
60.4
126
47.5
142
Hysteresis [mV]
Step 7 Enable
Apply a voltage ≤ 1V to the enable pin to disable the device. Left open or set to ≥ 1.5V will enable the device. When
disabeling use short leads to connect to AGND of the module. If not applicable use a transistor as below. The EN pin
provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold voltage, the device starts
operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low quiescent
current state.
28
ENABLE
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Step 8 Voltage tracking
Many of the common power supply sequencing methods can be implemented using the SS/TR, ENABLE and PG pins. The
sequential voltage tracking is illustrated below using two devices. The PG pin of the first device is coupled to the ENABLE
pin of the second device which enables the second power supply once the primary supply reaches regulation.
28
6
27
28
6
27
PG
ENABLE
SS/TR
PG
ENABLE
SS/TR
CSS
CSS
7
7
INTSS
INTSS
Simultaneous tracking
Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 as shown
below to the output of the power supply that needs to be tracked or to another voltage reference source.
28
ENABLE
VOUT1
SS/TR
INTSS
6
7
CSS
28
ENABLE
VOUT2
SS/TR
INTSS
R1
R2
6
7
CSS
푉
0.803∗ꢌ
ꢗ
∗12.6 (kΩ) (7)
푅2 =
−0.803 (kΩ) (8)
ꢄꢅꢆꢖ
푅1 =
0.803
푉
ꢄꢅꢆꢖ
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VDRM – Variable Step Down Regulator Module
Step 9 Synchronizing to an external clock
An internal phase locked loop (PLL) has been implemented to allow synchronization between 500 kHz and 2 MHz, and to
easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to
the RT/CLK pin with a minimum pulse width of 75 ns. The maximum clock pulse width must be calculated using Equation 9.
The clock signal amplitude must transition lower than 0.4 V and higher than 2.2 V. The start of the switching cycle is
synchronized to the falling edge of RT/CLK pin. Applications requiring both RT mode and CLK mode, configure the device
as shown in Figure 1. Before the external clock is present, the device works in RT mode and the switching frequency is set
by the RT resistor (RRT). When the external clock is present, the CLK mode overrides the RT mode. The device switches
from RT mode to CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of
the external clock. The device will lock to the external clock frequency approximately 15 µs after a valid clock signal is
present. It is not recommended to switch from CLK mode back to RT mode because the internal switching frequency drops
to a lower frequency before returning to the switching frequency set by the RT resistor.
ꢙ
OUT
0.7ꢘ∗(1−
)
ꢙ
INMIN
Maximum clock pulse width =
(9)
f
SW
470pF
1kΩ
7
RT/CLK
EXTERNAL CLOCK
GENERATOR
RRT
Figure 1
Step 10 Power Good
The PG pin is an open drain output. Once the voltage on the SENSE+ pin is between 93% and 107% of the nominal value,
the PG pin pull-down is released and the pin floats. The recommended pull-up resistor value is between 10 kΩ and 100 kΩ
to a voltage source that is 6 V or less. The PG pin is in a defined state once VIN is greater than 1.2 V, but with reduced
current sinking capability. The PG pin achieves full current sinking capability once the VIN pin is above 2.95V. The PG pin is
pulled low when the voltage on SENSE+ is lower than 91% or greater than 109% of the nominal set voltage. Also, the Power
Good pin is pulled low if the input UVLO or thermal shutdown is asserted, or if the ENABLE pin is pulled low.
VCC
10kΩ
27 PG
VCC = VIN or other supply voltage below 6V
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PROTECTIVE FEATURES
Over temperature protection (OTP)
For protection against load faults, the MagI³C Power Module incorporates cycle-by-cycle current limiting. During an
overcurrent condition the output current is limited and the output voltage is reduced. As the output voltage drops more than
9% below the set point, the PG signal is pulled low. If the output voltage drops more than 25%, the switching frequency is
reduced to reduce power dissipation within the device. When the overcurrent condition is removed, the output voltage
returns to the established voltage.
Over current protection (OCP)
The junction temperature of the MagI³C power module should not be allowed to exceed its maximum ratings. Thermal
protection is implemented by an internal Thermal Shutdown circuit which activates at 175°C (typ) causing the device to enter
a low power standby state. In this state the main MOSFET remains off causing VOUT to fall, and additionally the CSS
capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for accidental device overheating.
When the junction temperature falls back below 160° the SS pin is released, VOUT rises smoothly, and normal operation
resumes.
Applications requiring maximum output current especially those at high input voltage may require additional derating at
elevated temperatures.
Short circuit protection (SCP)
The short circuit protection is realized via the cycle by cycle current limiting. The short circuit protection is indefi-
nite with a recovery at the following switching cycle if the short circuit is removed.
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TYPICAL SCHEMATIC
VIN
VIN
VOUT
VOUT
27
28
6
PG
RSET
ENABLE
SS/TR
INTSS
RT/CLK
35
CIN2
CIN1
VADJ
AGND
PGND
COUT1
COUT2
7
4
RRT
INPUT
5V
OUTPUT
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.8V
1.8V
1.5V
1.2V
1.0V
0.8V
CIN2
CIN1
RRT
RSET
COUT1
COUT2
-
220µ
220µ
220µ
220µ
220µ
220µ
220µ
220µ
220µ
220µ
220µ
220µ
47µF X5R
47µF X5R
47µF X5R
47µF X5R
47µF X5R
47µF X5R
47µF X5R
47µF X5R
47µF X5R
47µF X5R
47µF X5R
47µF X5R
174kΩ
174kΩ
348kΩ
348kΩ
715kΩ
715kΩ
459Ω
47µ X5R
47µ X5R
47µ X5R
47µ X5R
47µ X5R
47µ X5R
47µ X5R
47µ X5R
47µ X5R
47µ X5R
47µ X5R
47µ X5R
5V
673Ω
47µ X5R
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
5V
1150Ω
1650Ω
2870Ω
5830Ω
Open
5V
5V
5V
5V
1200kΩ
348kΩ
348kΩ
715kΩ
715kΩ
1200kΩ
3.3V
3.3V
3.3V
3.3V
3.3V
1150Ω
1650Ω
2870Ω
5830Ω
Open
CIN2 and COUT2 ≥ 100µF are polymer tantalum types.
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HANDLING RECOMMENDATIONS
1.
The power module is classified as MSL3 (JEDEC Moisture Sensitivity Level 3) and requires special handling due to
moisture sensitivity (JEDEC J-STD033).
2.
3.
The parts are delivered in a sealed bag (Moisture Barrier Bags = MBB) and should be processed within one year.
When opening the moisture barrier bag check the Humidity Indicator Card (HIC) for color status. Bake parts prior to
soldering in case indicator color has changed according to the notes on the card.
4.
Parts must be processed after 168 hour (7 days) of floor life. Once this time has been exceeded, bake parts prior to
soldering per JEDEC J-STD033 recommendation.
SOLDER PROFILE
1.
2.
3.
4.
5.
Only Pb-Free assembly is recommended according to JEDEC J-STD020.
Measure the peak reflow temperature of the MagI³C power module in the middle of the top view.
Ensure that the peak reflow temperature does not exceed 245°C ±5°C as per JEDEC J-STD020.
The reflow time period during peak temperature of 245°C ±5°C must not exceed 30 seconds.
Reflow time above liquidus (217°C) must not exceed 90 seconds.
Maximum ramp up is rate 3°C per second.
6.
7.
Maximum ramp down rate is 3°C per second.
8.
9.
Reflow time from room (25°C) to peak must not exceed 8 minutes as per JEDEC J-STD020.
Maximum numbers of reflow cycles is three.
10.
11.
12.
13.
14.
For minimum risk, solder the module in the last reflow cycle of the PCB production.
For soldering process please consider lead material copper (Cu) and lead finish tin (Sn).
For solder paste use a standard SAC Alloy such as SAC 305, type 3 or higher.
Below profile is valid for convection reflow only.
Other soldering methods (e.g.vapor phase) are not verified and have to be validated by the customer on his own
risk.
Max 10 - 30 sec
Peak
Max 250
245°C
Ramp Down Rate
Max 3°C/sec
Ramp Up Rate
Max 3°C/sec
Liquidus
217
180
Max 90 sec
Min 30 sec
150
Preheat
Max 120 sec
Min 60 sec
Max 3 solder cycles !
Time [sec]
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PHYSICAL DIMENSIONS
Bottom View
all dimensions in mm
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EXAMPLE STENCIL DESIGN
Stencil thickness 0.125mm
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DOCUMENT HISTORY
Revision
Date
Description
Comment
0.1
31.03.2015
Preliminary version
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VDRM – Variable Step Down Regulator Module
CAUTIONS AND WARNINGS
The following conditions apply to all goods within the product series of MagI³C of
Würth Elektronik eiSos GmbH & Co. KG:
General:
All recommendations according to the general technical specifications of the data-sheet have to be complied with.
The usage and operation of the product within ambient conditions which probably alloy or harm the component surface has
to be avoided.
The responsibility for the applicability of customer specific products and use in a particular customer design is always within
the authority of the customer. All technical specifications for standard products do also apply for customer specific products.
Residual washing varnish agent that is used during the production to clean the application might change the characteristics
of the body, pins or termination. The washing varnish agent could have a negative effect on the long term function of the
product.
Direct mechanical impact to the product shall be prevented as the material of the body, pins or termination could flake or in
the worst case it could break. As these devices are sensitive to electrostatic discharge customer shall follow proper IC
Handling Procedures.
Customer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related
requirements concerning its products, and any use of Würth Elektronik eiSos GmbH & Co. KG components in its
applications, notwithstanding any applications-related information or support that may be provided by Würth Elektronik eiSos
GmbH & Co. KG. Customer represents and agrees that it has all the necessary expertise to create and implement
safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences lessen the
likelihood of failures that might cause harm and take appropriate remedial actions. Customer will fully indemnify Würth
Elektronik eiSos and its representatives against any damages arising out of the use of any Würth Elektronik eiSos GmbH &
Co. KG components in safety-critical applications.
Product specific:
Follow all instructions mentioned in the datasheet, especially:
The solder profile has to comply with the technical reflow or wave soldering specification, otherwise this will void the
warranty.
All products are supposed to be used before the end of the period of 12 months based on the product date-code.
Violation of the technical product specifications such as exceeding the absolute maximum ratings will void the warranty.
It is also recommended to return the body to the original moisture proof bag and reseal the moisture proof bag again.
ESD prevention methods need to be followed for manual handling and processing by machinery.
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IMPORTANT NOTES
The following conditions apply to all goods within the product range of Würth Elektronik eiSos GmbH & Co. KG:
1. General Customer Responsibility
Some goods within the product range of Würth Elektronik eiSos GmbH & Co. KG contain statements regarding general
suitability for certain application areas. These statements about suitability are based on our knowledge and experience of
typical requirements concerning the areas, serve as general guidance and cannot be estimated as binding statements about
the suitability for a customer application. The responsibility for the applicability and use in a particular customer design is
always solely within the authority of the customer. Due to this fact it is up to the customer to evaluate, where appropriate to
investigate and decide whether the device with the specific product characteristics described in the product specification is
valid and suitable for the respective customer application or not. Accordingly, the customer is cautioned to verify that the
datasheet is current before placing orders.
2. Customer Responsibility related to Specific, in particular Safety-Relevant Applications
It has to be clearly pointed out that the possibility of a malfunction of electronic components or failure before the end of the
usual lifetime cannot be completely eliminated in the current state of the art, even if the products are operated within the
range of the specifications. In certain customer applications requiring a very high level of safety and especially in customer
applications in which the malfunction or failure of an electronic component could endanger human life or health it must be
ensured by most advanced technological aid of suitable design of the customer application that no injury or damage is
caused to third parties in the event of malfunction or failure of an electronic component.
3. Best Care and Attention
Any product-specific notes, warnings and cautions must be strictly observed.
4. Customer Support for Product Specifications
Some products within the product range may contain substances which are subject to restrictions in certain jurisdictions in
order to serve specific technical requirements. Necessary information is available on request. In this case the field sales
engineer or the internal sales person in charge should be contacted who will be happy to support in this matter.
5. Product R&D
Due to constant product improvement product specifications may change from time to time. As a standard reporting
procedure of the Product Change Notification (PCN) according to the JEDEC-Standard we inform about minor and major
changes. In case of further queries regarding the PCN, the field sales engineer or the internal sales person in charge should
be contacted. The basic responsibility of the customer as per Section 1 and 2 remains unaffected.
6. Product Life Cycle
Due to technical progress and economical evaluation we also reserve the right to discontinue production and delivery of
products. As a standard reporting procedure of the Product Termination Notification (PTN) according to the JEDEC-
Standard we will inform at an early stage about inevitable product discontinuance. According to this we cannot guarantee
that all products within our product range will always be available. Therefore it needs to be verified with the field sales
engineer or the internal sales person in charge about the current product availability expectancy before or when the product
for application design-in disposal is considered. The approach named above does not apply in the case of individual
agreements deviating from the foregoing for customer-specific products.
7. Property Rights
All the rights for contractual products produced by Würth Elektronik eiSos GmbH & Co. KG on the basis of ideas,
development contracts as well as models or templates that are subject to copyright, patent or commercial protection
supplied to the customer will remain with Würth Elektronik eiSos GmbH & Co. KG. Würth Elektronik eiSos GmbH & Co. KG
does not warrant or represent that any license, either expressed or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right relating to any combination, application, or process in which Würth
Elektronik eiSos GmbH & Co. KG components or services are used.
8. General Terms and Conditions
Unless otherwise agreed in individual contracts, all orders are subject to the current version of the “General Terms and
Conditions of Würth Elektronik eiSos Group”, last version available at www.we-online.com.
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