X1202S8-2.7A [XICOR]
Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO8, PLASTIC, SOIC-8;
| 型号： | X1202S8-2.7A |
| 厂家： | 
XICOR INC. |
| 描述： | Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO8, PLASTIC, SOIC-8 时钟 光电二极管 外围集成电路 |
| 文件： | 总23页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2-Wire™ RTC
X1202
Real Time Clock/Calendar/Alarms/CPU Supervisor
FEATURES
DESCRIPTION
• Selectable watchdog timer (0.25s, 0.75s, 1.75s, off)
• Power on reset (250ms)
• Programmable low voltage reset
• 2 polled alarms
The X1202 is a Real Time Clock with Clock/Calendar/
CPU Supervisor circuits and two polled alarms. The dual
port clock and alarm registers allow the clock to oper-
ate, without loss of accuracy, even during read and
write operations.
—Settable on the second, minute, hour, day,
month, or day of the week
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low-cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction and
automatic adjustment for months with less than 31
days.
• 2-wire interface interoperable with I2C
—400kHz data transfer rate
• Secondary power supply input with internal
switch-over circuitry
• Low power CMOS
—<1µA operating current
—<3mA active current during program
—<400µA active current during data read
• Single byte write capability
• Typical nonvolatile write cycle time: 5ms
• High reliability
The X1202 provides a watchdog timer with 3 selectable
time out periods and off. The watchdog activates a
RESET pin when it expires. The reset also goes active
when V
drops below a fixed trip point. There are two
CC
• Small package options
—8-lead SOIC package, 8-lead TSSOP package
alarms where a match is monitored by polling status bits.
The device offers a backup power input pin. This V
BACK
pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational from
1.8 to 5.5 volts.
BLOCK DIAGRAM
X1
Timer
Calendar
Logic
Frequency
Divider
1Hz
32.768kHz
Oscillator
Time
X2
Keeping
Registers
(SRAM)
Control
Control
Status
Compare
Registers
Decode
Registers
Alarm
(EEPROM)
Logic
(SRAM)
Serial
Interface
Decoder
SCL
SDA
Alarm Regs
(EEPROM)
8
Interrupt Enable
Alarm
RESET
Characteristics subject to change without notice. 1 of 23
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X1202
PIN CONFIGURATION
32.768kHz quartz crystal is used. Recommended crystal
is a Citizen CFS-206. The crystal supplies a timebase for
a clock/oscillator. The internal clock can be driven by an
external signal on X1, with X2 left unconnected.
X1202
8-Pin SOIC
X1
X2
V
V
1
2
8
7
6
5
CC
Figure 1. Recommended Crystal Connection
BACK
RESET
12pF
SCL
SDA
3
4
V
SS
X1
X2
10M
X1202
8-Pin TSSOP
360K
68pF
V
SCL
SDA
BACK
1
2
8
7
6
5
V
CC
V
SS
X1
X2
3
4
POWER CONTROL OPERATION
RESET
The Power control circuit accepts a V
and a V
CC
BACK
BACK
input. The power control circuit will switch to V
when V < V
PIN DESCRIPTIONS
Serial Clock (SCL)
– 0.2V. It will switch back to V
CC
BACK
CC
when V exceeds V
.
CC
BACK
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
Figure 2. Power Control
V
CC
Internal
Voltage
Serial Data (SDA)
V
BACK
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs.The input buffer is always active (not gated).
V
= V
-0.2V
BACK
CC
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of
the output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire inter-
face speeds.
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external,
32.768kHz quartz crystal to maintain an accurate inter-
nal representation of the year, month, day, date, hour,
minute, and seconds. The RTC has leap-year correc-
tion and century byte. The clock also corrects for
months having fewer than 31 days and has a bit that
controls 24-hour or AM/PM format. When the X1202
V
BACK
This input provides a backup supply voltage to the
device. V supplies power to the device in the
BACK
event the V supply fails.
powers up after the loss of both V
and V
, the
CC
CC
BACK
clock will not increment until at least one byte is written
to the clock register.
RESET Output—RESET
This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or
Reading the Real Time Clock
that the supply voltage V
has dropped below a fixed
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the real time clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change dur-
ing the course of a read operation. In this device, the
CC
V
threshold. It is an open drain active LOW output.
TRIP
X1, X2
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier that can be
configured for use as an on-chip oscillator. A
Characteristics subject to change without notice. 2 of 23
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X1202
time is latched by the read command (falling edge of
the clock on the ACK bit prior to RTC data output) into a
separate latch to avoid time changes during the read
operation. The clock continues to run. Alarms occurring
during a read are unaffected by the read operation.
sequential read or page write operation provides
access to the contents of only one section of the CCR
per operation. Access to another section requires a
new operation. Continued reads or writes, once reach-
ing the end of a section, will wrap around to the start of
the section. A read or page write can begin at any
address in the CCR.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC register by a stop bit at the
end of a valid write sequence. An invalid write opera-
tion aborts the time update procedure and the contents
of the buffer are discarded. After a valid write operation
the RTC will reflect the newly loaded data beginning
with the first “one second” clock cycle after the stop bit.
The RTC continues to update the time while an RTC
register write is in progress and the RTC continues to
run during any nonvolatile write sequences. A single
byte may be written to the RTC without affecting the
other bytes.
Section 5) is a volatile register. It is not necessary to
set the RWEL bit prior to writing the status register.
Section 5) supports a single byte read or write only.
Continued reads or writes from this section terminates
the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.The
read instruction latches all clock registers into a buffer,
so an update of the clock does not change the time
being read. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
ALARM REGISTERS
CLOCK/CONTROL REGISTERS (CCR)
There are two alarm registers whose contents mimic
the contents of the RTC register, but add enable bits
and exclude the 24-hour time selection bit. The enable
bits specify which registers to use in the comparison
between the Alarm and real time registers. For example:
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only acces-
sible following a slave byte of “1101111x” and reads or
writes to addresses [0000h:003Fh].
CCR Access
– The user can set the X1202 to alarm every Wednes-
day at 8:00AM by setting the EDWn, the EHRn and
EMNn enable bits to ‘1’ and setting the DWAn, HRAn
and MNAn Alarm registers to 8:00AM Wednesday.
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
– A daily alarm for 9:30PM results when the EHRn and
EMNn enable bits are set to ‘1’ and the HRAn and
MNAn registers set 9:30PM.
The CCR is divided into 5 sections.These are:
– Setting the EMOn bit in combination with other
enable bits and a specific alarm time, the user can
establish an alarm that triggers at the same time
once a year.
1. Alarm 0 (8 bytes)
2. Alarm 1 (8 bytes)
3. Control (1 byte)
4. Real Time Clock (8 bytes)
5. Status (1 byte)
When there is a match, an alarm flag is set. The occur-
rence of an alarm can only be determined by polling
the AL0 and AL1 bits.
Sections 1) through 3) are nonvolatile and Sections 4)
and 5) are volatile. Each register is read and written
through buffers. The nonvolatile portion (or the counter
portion of the RTC) is updated only if RWEL is set and
only after a valid write operation and stop bit. A
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
Characteristics subject to change without notice. 3 of 23
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X1202
Table 1. Clock/Control Memory Map
Bit
Reg
Name
Addr.
Type
Range
7
6
5
4
3
2
1
0 (optional)
003F
0037
0036
0035
0034
0033
0032
0031
0030
0010
Status
SR
Y2K
DW
YR
MO
DT
BAT
0
AL1
0
AL0
Y2K21
0
0
Y2K20
0
0
Y2K13
0
RWEL
0
WEL
0
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
0
01h
20h
00h
00h
00h
00h
00h
00h
00h
00h
RTC
(SRAM)
19/20
0-6
0
0
DY2
Y12
G12
D12
H12
M12
S12
0
DY1
Y11
G11
D11
H11
M11
S11
0
Y23
0
Y22
0
Y21
0
Y20
G20
D20
H20
M20
S20
WD1
Y13
G13
D13
H13
M13
S13
WD0
0-99
1-12
1-31
0-23
0-59
0-59
0
0
D21
H21
M21
S21
0
HR
MN
SC
BL
MIL
0
0
M22
S22
0
0
Control
(EEPROM)
0
000F
000E
000D
000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
Alarm1
(EEPROM)
Y2K0
0
0
0
A1Y2K21 A1Y2K20 A1Y2K13
0
0
A1Y2K10 19/20
20h
00h
DWA0 EDW1
YRA0
0
0
0
DY2
DY1
DY0
0-6
Unused - Default = RTC Year value
MOA0 EMO1
0
0
A1G20
A1D20
A1H20
A1M20
A1S20
A1G13
A1D13
A1H13
A1M13
A1S13
A1G12
A1D12
A1H12
A1M12
A1S12
0
A1G11
A1D11
A1H11
A1M11
A1S11
0
A1G10
A1D10
A1H10
A1M10
A1S10
1-12
1-31
0-23
0-59
0-59
00h
00h
00h
00h
00h
20h
00h
DTA0
HRA0
EDT1
EHR1
0
A1D21
A1H21
A1M21
A1S21
0
A1M22
A1S22
0
MNA0 EMN1
SCA0
Y2K1
ESC1
0
Alarm0
(EEPROM)
A0Y2K21 A0Y2K20 A0Y2K13
A0Y2K10 19/20
DWA1 EDW0
YRA1
0
0
0
0
DY2
DY1
DY0
0-6
Unused - Default = RTC Year value
MOA1 EMO0
0
0
0
A0G20
A0D20
A0H20
A0M20
A0S20
A0G13
A0D13
A0H13
A0M13
A0S13
A0G12
A0D12
A0H12
A0M12
A0S12
A0G11
A0D11
A0H11
A0M11
A0S11
A0G10
A0D10
A0H10
A0M10
A0S10
1-12
1-31
0-23
0-59
0-59
00h
00h
00h
00h
00h
DTA1
HRA1
EDT0
EHR0
A0D21
A0H21
A0M21
A0S21
0
MNA1 EMN0
SCA1 ESC0
A0M22
A0S22
REAL TIME CLOCK REGISTERS
Year 2000 (Y2K)
Day of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven days
of the week. The counter advances in the cycle 0-1-2-
3-4-5-6-0-1-2-... The assignment of a numerical value
to a specific day of the week is arbitrary and may be
decided by the system software designer. The Clock
Default values define 0 = Sunday.
The X1202 has a century byte that “rolls over” from 19
to 20 when the years byte changes from 99 to 00. The
Y2K byte can contain only the values of 19 or 20.
Characteristics subject to change without notice. 4 of 23
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X1202
Clock/Calendar Register (YR, MO, DT, HR, MN, SC)
Note: Only the AL bits that are set when an SR read
starts will be reset. An alarm bit that is set by an alarm
occurring during an SR read operation will remain set
after the read operation is complete.
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 0 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with MIL = 1), DT (Date)
is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both
the RWEL and WEL bits to be set in a specific
sequence. RWEL bit is reset after each high voltage or
reset by sending 00h to status register.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12-
hour format and bit H21 functions as an AM/PM indica-
tor with a ‘1’ representing PM. The clock defaults to
Standard Time with H21 = 0.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4.Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1202 does not correct for
the leap year in the year 2100.
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and mem-
ory array during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to the CCR or any array
address will be ignored (no acknowledge will be issued
after the Data Byte). The WEL bit is set by writing a “1”
to the WEL bit and zeroes to the other bits of the Status
Register. Once set, WEL remains set until either reset
to “0” (by writing a “0” to the WEL bit and zeroes to the
other bits of the Status Register) or until the part pow-
ers up again. Writes to WEL bit do not cause a nonvol-
atile write cycle, so the device is ready for the next
operation immediately after the stop condition.
STATUS REGISTER (SR)
The Status Register is located in the RTC area at
address 003Fh. This is a volatile register only and is
used to control the WEL and RWEL write enable
latches, read two power status and two alarm bits. This
register is separate from both the array and the Clock/
Control Registers (CCR).
RTCF: Real Time Clock Fail Bit—Volatile
Table 2. Status Register (SR)
This bit is set to a ‘1’ after a total power failure. This is a
read only bit that is set by hardware when the device
powers up after having lost all power to the device. The
Addr
003Fh BAT AL1 AL0
Default
7
6
5
4
3
2
1
0
0
0
0
0
RWEL WEL RTCF
bit is set regardless of whether V
or V
is
0
0
0
0
0
1
CC
BACK
applied first. The loss of one or the other supplies does
not result in setting the RTCF bit. The first valid write to
the RTC (writing one byte is sufficient) resets the
RTCF bit to ‘0’.
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from V , not V . It is a read only bit and is set/
BACK
CC
reset by hardware.
Unused Bits
These devices do not use bits 3 or 4, but must have a
zero in these bit positions. The Data Byte output during
a SR read will contain zeros in these bit locations.
AL1, AL0: Alarm bits—Volatile
These bits announce if either alarm 1 or alarm 2 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags.
CONTROL REGISTER
Watchdog Timer Control Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 3 for options.
Characteristics subject to change without notice. 5 of 23
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X1202
Table 3. Watchdog Timer Time Out Options
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
WD1 WD0
Watchdog Time Out Period
1.75 seconds
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
0
0
1
1
0
1
0
1
750 milliseconds
250 milliseconds
disabled
When V
exceeds the device V
threshold value
CC
TRIP
for 250ms the circuit releases RESET, allowing the
system to begin operation.
WATCHDOG TIMER OPERATION
WRITING TO THE CLOCK/CONTROL REGISTERS
The watchdog timer is selectable. By writing a value to
WD1 and WD0, the watchdog timer can be set to 3 dif-
ferent time out periods or off. When the watchdog timer
is set to off, the watchdog circuit is configured for low
power operation.
Changing any of the nonvolatile bits of the clock/control
register requires the following steps:
– Write a 02H to the status register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
Watchdog Timer Restart
– Write a 06H to the status register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
The Watchdog Timer is restarted by a falling edge of
SDA when the SCL line is high. This is also referred to
as start condition.The restart signal restarts the watch-
dog timer counter, resetting the period of the counter
back to the maximum. If another start fails to be
detected prior to the watchdog timer expiration, then
the RESET pin becomes active. In the event that the
restart signal occurs during a reset time out period, the
restart will have no effect.
– Write one to 8 bytes to the clock/control registers with
the desired clock, alarm, or control data.This sequence
starts with a start bit, requires a slave byte of
“11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect.The RWEL bit is reset
by the completion of a nonvolatile write cycle, so the
sequence must be repeated to again initiate another
change to the CCR contents. If the sequence is not
completed for any reason (by sending an incorrect
number of bits or sending a start instead of a stop, for
example) the RWEL bit is not reset and the device
remains in an active mode.
LOW VOLTAGE RESET OPERATION
When a power failure occurs, and the voltage to the part
drops below a fixed V
voltage, a reset pulse is
TRIP
issued to the host microcontroller. The circuitry monitors
the V line with a voltage comparator which senses a
CC
preset threshold voltage. Power up and power down
waveforms are shown in Figure 4. The low voltage reset
circuit is to be designed so the RESET signal is valid
down to 1.0V.
When the low voltage reset signal is active, the operation
of any in-progress nonvolatile write cycle is unaffected,
allowing a nonvolatile write to continue as long as possi-
ble (down to the power on reset voltage). The low voltage
reset signal, when active, terminates in-progress commu-
nications to the device and prevents new commands, to
reduce the likelihood of data corruption.
– The RWEL and WEL bits can be reset by writing a 0
to the status register.
– A read operation occurring between any of the previous
operations will not interrupt the register write operation.
POWER ON RESET
Application of power to the X1202 activates a power on
reset circuit that pulls the RESET pin active.This signal
provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
Characteristics subject to change without notice. 6 of 23
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X1202
Figure 3. Watchdog Restart/Time Out
t
t
>t
RSP
RSP WDO
t
t
>t
t
RST
t
<t
RST
RSP WDO
RSP WDO
SCL
SDA
RESET
Note: All inputs are ignored during the active reset period (t
).
RST
Figure 4. Power On Reset and Low Voltage Reset
V
TRIP
V
CC
t
t
PURST
PURST
t
RPD
t
F
t
R
RESET
V
RVALID
V
THRESHOLD RESET PROCEDURE
Setting the V
Voltage
CC
TRIP
This procedure is used to set the V
voltage value. It is necessary to reset the trip point
before setting the new value.
to a higher
TRIP
The X1202 is shipped with a standard V
threshold
CC
(V
) voltage. This value will not change over normal
TRIP
operating and storage conditions. However, in applica-
tions where the standard V is not exactly right, or if
TRIP
To set the new V
voltage, apply the desired V
TRIP
TRIP
higher precision is needed in the V
value, the
TRIP
threshold voltage to the V
pin and tie the RESET
CC
X1202 threshold may be adjusted. The procedure
is described below, and uses the application of a
nonvolatile write control signal.
pad pin to the programming voltage V .Then write data
P
00h to address 01h. The stop bit following a valid write
operation initiates the V
programming sequence.
TRIP
Bring RESET to V to complete the operation.
CC
Note: This operation also writes 00h to address 01h of
the EEPROM array.
Characteristics subject to change without notice. 7 of 23
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X1202
Figure 5. Set V
Level Sequence (V
= desired V
value)
TRIP
CC
TRIP
V
CC
V
= 15V
P
RESET
V
CC
0
1
2
3
4
5 6 7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4 5 6 7
SCL
SDA
AEh
00h
01h
00h
Resetting the V
Voltage
To reset the new V
voltage, apply more than 3V to
TRIP
TRIP
the V
pin and tie the RESET pin to the programming
CC
This procedure is used to set the V
voltage level. For example, if the current V
to a “native”
TRIP
voltage V . Then write 00h to address 03h. The stop bit of
P
is 4.4V
TRIP
a valid write operation initiates the V
sequence. Bring RESET to complete the operation.
programming
TRIP
and the new V
must be 4.0V, then the V
must
TRIP
TRIP
be reset. When V
is reset, the new V
is less
TRIP
TRIP
than 1.7V. This procedure must be used to set the volt-
age to a lower value.
Note: This operation also writes 00h to address 03h of
the EEPROM array.
Figure 6. Reset V
Level Sequence (V
> 3V)
TRIP
CC
V
= 15V
V
P
CC
RESET
V
CC
0
1 2 3 4 5 6 7
0
1
2 3
4
5 6
7
0
1
2 3
4
5 6
7
0 1 2 3 4 5 6 7
SCL
SDA
AEh
00h
03h
00h
Figure 7. Sample V
Reset Circuit
TRIP
V
P
4.7K
Adjust
Run
µC
RESET
1
8
7
6
5
X1202
(8-Pin SOIC)
2
3
4
V
TRIP
Adj.
SCL
SDA
Characteristics subject to change without notice. 8 of 23
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X1202
SERIAL COMMUNICATION
Interface Conventions
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family
operate as slaves in all applications.
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 8.
Figure 8. Valid Data Changes on the SDA Bus
SCL
SDA
Data Change
Data Stable
Data Stable
Start Condition
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 9.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 10.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
Figure 9. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Characteristics subject to change without notice. 9 of 23
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X1202
Figure 10. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Start
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct device
identifier and select bits are contained in the slave
address byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
WRITE OPERATIONS
Byte Write
For a byte write operation, the device requires the
slave address byte and the CCR address bytes. This
gives the master access to any one of the words in the
CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceeding operations to enable the write operation.
See “Writing to the Clock/Control Registers” on page 6.)
Upon receipt of each address byte, the X1202
responds with an acknowledge. After receiving both
address bytes the X1202 awaits the eight bits of data.
After receiving the 8 data bits, the X1202 again
responds with an acknowledge. The master then termi-
nates the transfer by generating a stop condition. The
X1202 then begins an internal write cycle of the data to
the nonvolatile memory. During the internal write cycle,
the device inputs are disabled, so the device will not
respond to any requests from the master. The SDA out-
put is at high impedance. See Figure 11.
– The slave address byte when the device identifier
and/or select bits are incorrect
– All data bytes of a write when the WEL in the write
protect register is LOW
– The 2nd data byte of a status register write operation
(only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to standby mode and place the
device into a known state.
Page Write
The X1202 has a page write operation. It is initiated in
the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit up to 7
more bytes to the clock/control registers.
Note: Prior to writing to the CCR, the master must
write a 02h, then 06h to the status register in two pre-
ceeding operations to enable the write operation. See
“Writing to the Clock/Control Registers” on page 6.)
Characteristics subject to change without notice. 10 of 23
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X1202
Figure 11. Byte Write Sequence
S
S
t
o
p
t
Slave
Address
Signals from
the Master
CCR
Address 1
CCR
Address 0
a
Data
r
t
SDA Bus
0 0 0 0 0 0 0 0
1 1 0 1 1 1 1 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 12. Page Write Sequence
(1 ≤ n 64)
S
t
a
r
Signals from
the Master
S
t
o
p
CCR
Address 1
Slave
Address
CCR
Address 0
Data
(n)
Data
(1)
t
SDA Bus
1 1 0 1 1 1 1 0
0 0 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
After the receipt of each byte, the X1202 responds with
an acknowledge, and the address is internally incrimi-
nated by one. When the counter reaches the end of the
page, it “rolls over” and goes back to the first address
on the same page. If the master supplies more than 8
bytes of data, then the previously loaded data is over
written by the new data, one byte at a time. The master
terminates the data byte loading by issuing a stop con-
dition, which causes the device to begin the non vola-
tile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle. Refer to Figure 12 for the address, acknowledge,
and data transfer sequence.
Acknowledge Polling
The disabling of the inputs during non volatile write
cycles can be used to take advantage of the typical
5ms write cycle time. Once the stop condition is issued
to indicate the end of the master’s byte load operation,
the device initiates the internal non volatile write cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the slave address byte for a write or read operation. If
the device is still busy with the non volatile write cycle
then no ACK will be returned. If the device has com-
pleted the write operation, an ACK will be returned and
the host can then proceed with the read or write opera-
tion. Refer to the flow chart in Figure 13.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and its associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the device will reset itself without
performing the write. The contents of the array will not
be affected.
Characteristics subject to change without notice. 11 of 23
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X1202
Figure 13. Acknowledge Polling Sequence
READ OPERATIONS
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incrimi-
nated by one. Therefore, if the last read was to address
n, the next read operation would access data from
address n + 1.
Issue START
Issue Slave
Issue STOP
Address Byte
(Read or Write)
Upon receipt of the slave address byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the data byte. The master
terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 14 for
the address, acknowledge, and data transfer sequence.
NO
NO
ACK
Returned?
YES
Nonvolatile Write
Cycle Complete.
Continue Command
Sequence?
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Issue STOP
YES
Continue Normal
Read or Write
Command
Sequence
PROCEED
Figure 14. Current Address Read Sequence
S
S
t
o
p
t
a
r
Signals from
the Master
Slave
Address
t
SDA Bus
1 1 0 1 1 1 1 1
A
C
K
Signals from
the Slave
Data
Characteristics subject to change without notice. 12 of 23
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X1202
Random Read
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 15 for the address,
acknowledge, and data transfer sequence.
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
slave address byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the CCR address bytes. After acknowledging receipt of
the CCR address bytes, the master immediately issues
another start condition and the slave address byte with
the R/W bit set to one. This is followed by an acknowl-
edge from the device and then by the eight bit word.
The master terminates the read operation by not
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 16. The X1202 then
goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next current address read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Figure 15. Random Address Read Sequence
S
t
S
S
t
a
r
CCR
Address 0
Slave
Address
CCR
Address 1
Signals from
the Master
Slave
Address
t
a
r
o
p
t
t
SDA Bus
1 1 0 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 0 1 1 1 1 1
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
Figure 16. Sequential Read Sequence
S
t
o
p
Signals from
the Master
Slave
Address
A
C
K
A
C
K
A
C
K
SDA Bus
1
A
C
K
Signals from
the Slave
Data (2)
Data (n-1)
Data (1)
Data (n)
(n is any integer greater than 1)
Sequential Read
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments auto-
matically, allowing the entire register contents to be
serially read during one operation. At the end of the
register space the counter “rolls over” to the first location
in the register and the device continues to output data
for each acknowledge received. Refer to Figure 18 for
the acknowledge and data transfer sequence.
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
Characteristics subject to change without notice. 13 of 23
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X1202
DEVICE ADDRESSING
After loading the entire slave address byte from the
SDA bus, the device compares the device identifier and
device select bits with 1101111. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Following a start condition, the master must output a
slave address byte. The first four bits of the Slave
Address Byte specify access to the CCR. Slave bits
1101 access the CCR.
Following the slave byte is a two byte CCR address.
The CCR address is either supplied by the master
device or obtained from an internal counter.
Bit 3 through Bit 1 of the slave byte specify the device
select bits.These are set to 111.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. That is, for a random read of the clock/
control registers, the slave byte must be 1101111x in
both places.
The last bit of the slave address byte defines the oper-
ation to be performed. When this R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 18.
Figure 17. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Device Identifier
Slave Address Byte
Byte 0
1
1
0
1
1
1
1
R/W
0
High Order Word Address
Byte 1—X1202
0
0
0
0
0
0
0
Low Order Word Address
Byte 2—X1202
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
Data Byte
Byte 3
Characteristics subject to change without notice. 14 of 23
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X1202
ABSOLUTE MAXIMUM RATINGS
COMMENTS
Temperature under bias ........................ -65 to +135°C
Storage temperature ............................. -65 to +150°C
Voltage on any pin (respect to ground)....-1.0V to 7.0V
DC output current................................................ 5 mA
Lead temperature (soldering, 10 sec) ............... 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those indicated in the operational sections of this spec-
ification) is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.
DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.)
Symbol
Parameter
Conditions
Min.
2.7
Typ.
Max.
5.5
Unit
V
Notes
V
Main Power Supply
Backup Power Supply
Switch to Backup Supply
Switch to Main Supply
Active Supply Current
CC
V
1.8
5.5
V
BACK
V
V
V
- 0.2
V
- 0.1
V
17
17
CB
BC
BACK
BACK
V
V
+ 0.1
V
BACK
BACK
I
I
I
V
V
V
V
V
V
= 2.7V
= 5.5V
= 2.7V
= 5.5V
= 2.7V
= 5.5V
1.2
1.7
1.5
3.0
2.0
2.5
1.0
1.5
2
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
5, 8, 15
CC1
CC
CC
CC
CC
CC
CC
Program Supply Current
(nonvolatile)
5, 8, 16, 17
5, 7, 16, 17
7, 10, 16, 17
7, 10, 16, 17
CC2
CC3
Main Timekeeping
Current
I
I
Backup Timekeeping
Current
V
= 1.8V
= 5.5V
= 1.8V
= 5.5V
BACK1
BACK2
BACK
BACK
BACK
BACK
V
V
V
Backup Supply Current
(External crystal net-
work)
1.6
7.5
10
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
µA
µA
V
11
11
LI
I
10
LO
V
-0.5
V
V
x 0.2 or
CC
5, 14
IL
x 0.2
BACK
V
Input HIGH Voltage
V
V
x 0.7 or
V
+ 0.5
+ 0.5
5, 14
14
IH
CC
CC
V
x 0.7
V
BACK
BACK
V
Schmitt Trigger Input
Hysteresis
V
related level .05 x V or
HYS
CC CC
V
V
.05 x V
BACK
V
Output LOW Voltage
V
V
V
V
= 2.7V
= 5.5V
= 2.7V
= 5.5V
0.4
0.4
12
OL
CC
CC
CC
CC
V
Output HIGH Voltage
1.6
2.4
13
OH
V
Characteristics subject to change without notice. 15 of 23
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X1202
Notes: (1) The device enters the active state after any start, and remains active: for 9 clock cycles if the device select bits in the slave address
byte are incorrect or until 200ns after a stop ending a read or write operation.
(2) The device enters the program state 200ns after a stop ending a write operation and continues for t
.
WC
(3) The device goes into the timekeeping state 200ns after any stop, except those that initiate a nonvolatile write cycle; t
after a stop
WC
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave
address byte.
(4) For reference only and not tested.
(5) V = V x 0.1, V = V x 0.9, f
= 400kHz, SDA = open
IL
CC
IH
CC
SCL
SCL
(6) V = V x 0.1, V = V x 0.9, f
= 400kHz, f
= 400kHz, V = 1.22 x V Min
IL
CC
IH
CC
SDA CC CC
(7) V = 0V
CC
(8) V
(9) V
(10)V
(11)V
= 0V
BACK
= V
= V , Others = GND or V
CC CC
SDA
SDA
SDA
SCL
= V
= V
, Others = GND or V
SCL
BACK BACK
= GND to V
V
= GND or V
CC, CLK CC
(12)I = 3.0mA at 5V, 1.5mA at 2.7V
OL
(13)I
= -1.0mA at 5V, -0.4mA at 2.7V
OH
(14)Threshold voltages based on the higher of V or V
.
BACK
CC
(15)Driven by external 32.768kHz square wave oscillator on X1, X2 open.
(16)Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(17)Periodically sampled and not 100% tested
CAPACITANCE T = 25°C, F = 1.0 MHZ, V
= 5V
A
CC
Symbol
Parameter
Max.
Unit
pF
Test Condition
= 0V
(1)
C
Output capacitance (SDA, RESET)
Input capacitance (SCL)
8
6
V
OUT
OUT
(1)
C
pF
V
= 0V
IN
IN
Note: (1) This parameter is periodically sampled and not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR
= 5V (standard output load for testing the device
V
CC
with V
= 5.0V)
CC
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
5.0V
Input rise and fall times
Input and output timing levels
Output load
10ns
V
x 0.5
CC
For V = 0.4V
OL
1533Ω
Standard output load
and I = 3 mA
OL
SDA
100pF
Characteristics subject to change without notice. 16 of 23
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X1202
AC SPECIFICATIONS (T = -40°C to +85°C, V
= +2.7V to +5.5V, unless otherwise specified.)
A
CC
Symbol
Parameter
Min.
Max. Unit
f
SCL clock frequency
0
400
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
pF
SCL
t
Pulse width suppression time at inputs
SCL LOW to SDA data out valid
Time the bus must be free before a new transmission can start
Clock LOW time
50
IN
t
0.1
0.9
AA
t
1.3
BUF
t
1.3
LOW
t
Clock HIGH time
0.6
HIGH
t
Start condition setup time
Start condition hold time
0.6
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
t
t
0.6
Data in setup time
100
t
t
Data in hold time
0
Stop condition setup time
Data output hold time
0.6
t
50
DH
t
SDA and SCL rise time
20 +.1Cb(3)
20 +.1Cb(3)
300
300
400
R
t
SDA and SCL fall time
F
Cb
Capacitive load for each bus line
Notes: (1) Typical values are for T = 25°C and V = 5.0V
A
CC
(2) This parameter is periodically sampled and not 100% tested.
(3) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
t
t
t
t
R
F
HIGH
LOW
SCL
t
t
SU:DAT
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA IN
t
t
t
BUF
AA
DH
SDA OUT
Characteristics subject to change without notice. 17 of 23
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X1202
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
t
WC
Stop
Start
Condition
Condition
Power Up Timing
Symbol
Parameter
Min.
Typ.(2)
Max.
Unit
ms
(1)
t
Time from power up to read
Time from power up to write
1
5
PUR
(1)
t
ms
PUW
Notes: (1) Delays are measured from the time V
is stable until the specified operation can be initiated. These parameters are periodically
CC
sampled and not 100% tested.
(2) Typical values are for T = 25°C and V = 5.0V
A
CC
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min.
Typ.(1)
Max.
Unit
(1)
t
Write cycle time
5
10
ms
WC
Note: (1) t
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
WC
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
Pre-programmed reset trip voltage
PTRIP
X1202-4.5A
X1202
X1202-2.7A
X1202-2.7
4.49
4.25
2.76
2.57
4.63
4.38
2.85
2.65
4.77
4.51
2.94
2.73
V
t
V
detect to RESET LOW
500
400
ns
ms
µs
µs
RPD
CC
t
Power up reset time out delay
100
10
200
PURST1
t
V
V
fall time
rise time
F
CC
t
10
R
CC
t
Watchdog timer period:
WD1 = 0, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 1, WD0 = 0
WDO
1.7
725
225
1.75
750
250
1.8
775
275
s
ms
ms
t
t
Watchdog reset time out delay
2-wire interface
225
1
250
275
ms
µs
V
RST1
RSP
V
Reset valid V
1.0
RVALID
CC
Characteristics subject to change without notice. 18 of 23
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X1202
V
Programming Timing Diagram
TRIP
V
CC
(V
)
TRIP
V
TRIP
t
t
t
TSU
THD
V
= 15V
P
RESET
V
CC
V
CC
t
VPH
VPO
t
VPS
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
t
RP
AEh
00h
03h/01h
00h
V
Programming Parameters
TRIP
Parameter
Description
Min. Max. Unit
t
V
V
V
V
V
V
V
program enable voltage setup time
program enable voltage hold time
setup time
1
1
µs
µs
µs
ms
ms
µs
ms
V
VPS
VPH
TRIP
TRIP
TRIP
TRIP
TRIP
TRIP
TRIP
t
t
1
TSU
THD
t
hold (stable) time
10
t
write cycle time
10
WC
t
program enable voltage off time (between successive adjustments)
program recovery period (between successive adjustments)
0
VPO
t
10
RP
V
Programming voltage
programmed voltage range
14
15
5.0
P
V
V
1.7
-0.1
-25
V
TRAN
TRIP
V
V
Initial V
program voltage accuracy (V applied–V ) (programmed at 25°C)
TRIP
+0.4
+25
V
ta1
ta2
TRIP
CC
Subsequent V
Programmed at 25°C.)
program voltage accuracy [(V applied–V )—V .
TRIP
mV
TRIP
CC
ta1
V
V
program voltage repeatability (Successive program operations. Programmed
-25
-25
+25
+25
mV
mV
tr
TRIP
at 25°C.)
V
V
TRIP
program variation after programming (0–75°C). (programmed at 25°C)
tv
V
programming parameters are periodically sampled and are not 100% tested.
TRIP
Characteristics subject to change without notice. 19 of 23
REV 1.1.8 5/17/01
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X1202
PACKAGING INFORMATION
8-Lead Plastic, SOIC, Package Code S8
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050"Typical
X 45°
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 20 of 23
REV 1.1.8 5/17/01
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X1202
PACKAGING INFORMATION
8-Lead Plastic, TSSOP, Package Code V8
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.114 (2.9)
.122 (3.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
(7.72)
(4.16)
Detail A (20X)
(1.78)
(0.42)
.031 (.80)
.041 (1.05)
(0.65)
All Measurements Are Typical
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 21 of 23
REV 1.1.8 5/17/01
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X1202
Ordering Information
V
Range
V
Package
Operating Temperature Range
0–70°C
Part Number
X1202S8-4.5A
X1202S8I-4.5A
X1202V8-4.5A
X1202V8I-4.5A
X1202S8
CC
TRIP
4.5–5.5V
4.5–5.5V
4.5–5.5V
4.5–5.5V
2.7–3.6V
2.7–3.6V
2.7–3.6V
2.7–3.6V
4.63V 3%
4.63V 3%
4.38V 3%
4.38V 3%
2.85V 3%
2.85V 3%
2.65V 3%
2.65V 3%
8L SOIC
-40–85°C
0–70°C
8L TSSOP
8L SOIC
-40–85°C
0–70°C
-40–85°C
0–70°C
X1202S8I
8L TSSOP
8L SOIC
X1202V8
-40–85°C
0–70°C
X1202V8I
X1202S8-2.7A
X1202S8I-2.7A
X1202V8-2.7A
X1202V8I-2.7A
X1202S8-2.7
X1202S8I-2.7
X1202V8-2.7
X1202V8I-2.7
-40–85°C
0–70°C
8L TSSOP
8L SOIC
-40–85°C
0–70°C
-40–85°C
0–70°C
8L TSSOP
-40–85°C
Characteristics subject to change without notice. 22 of 23
REV 1.1.8 5/17/01
www.xicor.com
X1202
Part Mark Information
8-Lead TSSOP
EYWW
XXXXX
1202AL = 4.5 to 5.5V, 0 to +70°C, V
= 4.63V 3%
TRIP
1202AM = 4.5 to 5.5V, -40 to +85°C, V
= 4.63V 3%
TRIP
1202 = 4.5 to 5.5V, 0 to +70°C, V
= 4.38V 3%
TRIP
1202I = 4.5 to 5.5V, -40 to +85°C, V
1202AN = 2.7 to 3.6V, 0 to +70°C, V
= 4.38V 3%
= 2.85V 3%
TRIP
TRIP
1202AP = 2.7 to 3.6V, -40 to +85°C, V
= 2.85V 3%
TRIP
1202F = 2.7 to 3.6V, 0 to +70°C, V
= 2.65V 3%
TRIP
1202G = 2.7 to 3.6V, -40 to +85°C, V
= 2.65V 3%
TRIP
8-Lead SOIC
Blank = 8-Lead SOIC
X1202 X
XX
AL = 4.5 to 5.5V, 0 to +70°C, V
= 4.63V 3%
TRIP
AM = 4.5 to 5.5V, -40 to +85°C, V
Blank = 4.5 to 5.5V, 0 to +70°C, V
= 4.63V 3%
= 4.38V 3%
TRIP
TRIP
I = 4.5 to 5.5V, -40 to +85°C, V
AN = 2.7 to 3.6V, 0 to +70°C, V
= 4.38V 3%
= 2.85V 3%
TRIP
TRIP
AP = 2.7 to 3.6V, -40 to +85°C, V
= 2.85V 3%
TRIP
F = 2.7 to 3.6V, 0 to +70°C, V
= 2.65V 3%
TRIP
G = 2.7 to 3.6V, -40 to +85°C, V
= 2.65V 3%
TRIP
LIMITED WARRANTY
©Xicor, Inc. 2001 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS ANDTRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 23 of 23
REV 1.1.8 5/17/01
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