X1226 [XICOR]
Real Time Clock/Calendar with EEPROM; 实时时钟/日历与EEPROM
| 型号： | X1226 |
| 厂家： | 
XICOR INC. |
| 描述： | Real Time Clock/Calendar with EEPROM |
| 文件： | 总24页 (文件大小：420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
New Features
Repetitive Alarms &
Temperature Compensation
4K (512 x 8)
2-Wire™ RTC
X1226
Real Time Clock/Calendar with EEPROM
FEATURES
APPLICATIONS
• Real Time Clock/Calendar
• Utility Meters
—Tracks time in Hours, Minutes, and Seconds
—Day of the Week, Day, Month, andYear
• 2 Polled Alarms (Non-volatile)
—Settable on the Second, Minute, Hour, Day of
the Week, Day, or Month
—Repeat Mode (periodic interrupts)
• Oscillator Compensation on chip
—Internal feedback resistor and compensation
capacitors
• HVAC Equipment
• Audio / Video Components
• Set Top Box / Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers / PDA
• POS Equipment
—64 position Digitally Controlled Trim Capacitor
—6 digital frequency adjustment settings to
±±3ppm
• Test Meters / Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Battery Switch or Super Cap Input
• 512 x 8 Bits of EEPROM
• Computer Products
• Other Industrial / Medical / Automotive
—64-Byte Page Write Mode
—8 modes of Block Lock™ Protection
—Single Byte Write Capability
• High Reliability
DESCRIPTION
The X1226 device is a Real Time Clock with clock/
calendar, two polled alarms with integrated 512x8
EEPROM, oscillator compensation, and battery
backup switch.
—Data Retention: 133 years
—Endurance: 133,333 cycles per byte
• 2-Wire™ Interface interoperable with I2C*
—433kHz data transfer rate
• Frequency Output (SW Selectable: Off, 1Hz,
4396Hz or ±2.768kHz)
• Low Power CMOS
—1.25µA Operating Current (Typical)
• Small Package Options
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
—8-Lead SOIC and 8-Lead TSSOP
BLOCK DIAGRAM
OSC
Compensation
X1
Timer
Calendar
Logic
Battery
Switch
Circuitry
Time
Keeping
Registers
V
V
CC
Frequency
Divider
1Hz
Oscillator
32.768kHz
BACK
X2
Select
(SRAM)
PHZ/IRQ
Status
Control/
Control
Decode
Logic
Compare
Serial
Interface
Decoder
Registers
SCL
SDA
Registers
Alarm
(EEPROM)
(SRAM)
Alarm Regs
(EEPROM)
8
4K
EEPROM
ARRAY
*I2C is a Trademark of Philips.
REV 1.1.24 1/13/03
Characteristics subject to change without notice. 1 of 24
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X1226
DESCRIPTION (continued)
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire inter-
face speed.
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, Seconds. The Calendar
has separate registers for Date, Month, Year and Day-
of-week. The calendar is correct through 2099, with
automatic leap year correction.
V
BACK
This input provides a backup supply voltage to the
The powerful Dual Alarms can be set to any Clock/
Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide
a hardware interrupt (IRQ Pin). There is a repeat
mode for the alarms allowing a periodic interrupt.
device. V
event the V
supplies power to the device in the
supply fails. This pin can be connected
BACK
CC
to a battery, a Supercap or tied to ground if not used.
Programmable Frequency/Interrupt Output – PHZ/IRQ
This is either an output from the internal oscillator or an
interrupt signal output. It is an open drain output.
The PHZ/IRQ pin may be software selected to provide
a frequency output of 1 Hz, 4096 Hz, or 32,768 Hz.
When used as frequency output, this signal has a
frequency of 32.768kHz, 4096Hz, 1Hz or inactive.
The device offers a backup power input pin. This
V
pin allows the device to be backed up by battery
BACK
When used as interrupt output, this signal notifies a
host processor that an alarm has occurred and an
action is required. It is an active LOW output.
or SuperCap. The entire X1226 device is fully
operational from 2.7 to 5.5 volts and the clock/calendar
portion of the X1226 device remains fully operational
down to 1.8 volts (Standby Mode).
The control bits for this function are FO1 and FO0 and
are found in address 0011h of the Clock Control Mem-
ory map. Refer to “Programmable Frequency Output
Bits” on page 6.
The X1226 device provides 4K bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock allows a
safe, secure memory for critical user and configuration
data, while allowing a large user storage area.
X1, X2
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external
32.768kHz quartz crystal is used with the X1226 to
supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit.
Plenty of ground plane around the device and short
traces to X1 and X2 are highly recommended. See
Application section for more recommendations.
PIN DESCRIPTIONS
X1226
8-Pin SOIC
8-Pin TSSOP
V
SCL
SDA
1
2
V
V
BACK
X1
X2
8
7
6
5
1
2
CC
8
7
6
5
V
CC
BACK
V
SS
X1
X2
3
4
PHZ/IRQ
3
4
SCL
SDA
PHZ/IRQ
V
SS
NC = No internal connection
Figure 1. Recommended Crystal connection
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
X1
X2
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs.The input buffer is always active (not gated).
POWER CONTROL OPERATION
The power control circuit accepts a V
and a V
BACK
CC
input. The power control circuit powers the clock from
when V < V – 0.2V. It will switch back to
V
BACK
CC
BACK
power the device from V when V exceeds V .
CC
CC
BACK
Characteristics subject to change without notice. 2 of 24
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X1226
Figure 2. Power Control
the time while an RTC register write is in progress and
the RTC continues to run during any nonvolatile write
sequences. A single byte may be written to the RTC
without affecting the other bytes.
V
CC
Voltage
On
V
BACK
In
Off
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC perfor-
mance will also be dependent upon temperature. The
frequency deviation of the crystal is a fuction of the
turnover temperature of the crystal from the crystal’s
nominal frequency. For example, a >20ppm frequency
deviation translates into an accuracy of >1 minute per
month. These parameters are available from the
crystal manufacturer. Xicor’s RTC family provides on-
chip crystal compensation networks to adjust load-
capacitance to tune oscillator frequency from +116
ppm to –37 ppm when using a 12.5 pF load crystal.
For more detail information see the Application
section.
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external
32.768kHz quartz crystal to maintain an accurate
internal representation of the second, minute, hour,
day, date, month, and year. The RTC has leap-year
correction. The clock also corrects for months having
fewer than 31 days and has a bit that controls 24 hour
or AM/PM format. When the X1226 powers up after
the loss of both V
and V
, the clock will not
CC
BACK
operate until at least one byte is written to the clock
register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change during
the course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a separate
latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a
read are unaffected by the read operation.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
CCR Access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the next “one second” clock cycle after
the stop bit is written. The RTC continues to update
The CCR is divided into 5 sections.These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Characteristics subject to change without notice. 3 of 24
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X1226
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Addi-
tional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
change the time being read. A sequential read of the
CCR will not result in the output of data from the mem-
ory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 (status register) supports
a single byte read or write only. Continued reads or
writes from this section terminates the operation.
Table 1. Clock/Control Memory Map
Bit
Reg
Name
Addr.
Type
Range
7
6
5
4
3
2
1
0 (optional)
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
000F
000E
000D
000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
Status
SR
Y2K
BAT
AL1
0
AL0
Y2K21
0
0
Y2K20
0
0
Y2K13
0
RWEL
0
WEL
0
RTCF
Y2K10
DY0
Y10
01h
20h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
20h
00h
RTC
(SRAM)
0
0
19/20
0-6
DW
0
DY2
Y12
G12
D12
H12
M12
S12
DTR2
ATR2
X
DY1
Y11
G11
D11
H11
M11
S11
DTR1
ATR1
X
YR
Y23
0
Y22
0
Y21
0
Y20
G20
D20
H20
M20
S20
0
Y13
G13
D13
H13
M13
S13
0
0-99
1-12
1-31
0-23
0-59
0-59
MO
G10
DT
0
0
D21
H21
M21
S21
0
D10
HR
MIL
0
0
H10
MN
M22
S22
0
M10
S10
SC
0
Control
(EEPROM)
DTR
0
DTR0
ATR0
X
ATR
0
0
ATR5
AL0E
BP0
ATR4
FO1
0
ATR3
FO0
0
INT
IM
BP2
0
AL1E
BP1
0
BL
0
0
0
Alarm1
(EEPROM)
Y2K1
DWA1
YRA1
MOA1
DTA1
HRA1
MNA1
SCA1
Y2K0
DWA0
YRA0
MOA0
DTA0
HRA0
MNA0
SCA0
A1Y2K21 A1Y2K20 A1Y2K13
0
0
A1Y2K10
DY0
19/20
0-6
EDW1
0
0
0
0
DY2
DY1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
EMO1
EDT1
EHR1
EMN1
ESC1
0
0
0
A1G20
A1D20
A1H20
A1M20
A1S20
A1G13
A1D13
A1H13
A1M13
A1S13
A1G12
A1D12
A1H12
A1M12
A1S12
0
A1G11
A1D11
A1H11
A1M11
A1S11
0
A1G10
A1D10
A1H10
A1M10
A1S10
A0Y2K10
DY0
1-12
1-31
0-23
0-59
0-59
19/20
0-6
00h
00h
00h
00h
00h
20h
00h
0
A1D21
A1H21
A1M21
A1S21
0
A1M22
A1S22
0
Alarm0
(EEPROM)
A0Y2K21 A0Y2K20 A0Y2K13
EDW0
0
0
0
0
DY2
DY1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
EMO0
EDT0
EHR0
EMN0
ESC0
0
0
0
A0G20
A0D20
A0H20
A0M20
A0S20
A0G13
A0D13
A0H13
A0M13
A0S13
A0G12
A0D12
A0H12
A0M12
A0S12
A0G11
A0D11
A0H11
A0M11
A0S11
A0G10
A0D10
A0H10
A0M10
A0S10
1-12
1-31
0-23
0-59
0-59
00h
00h
00h
00h
00h
A0D21
A0H21
A0M21
A0S21
0
A0M22
A0S22
Characteristics subject to change without notice. 4 of 24
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X1226
ALARM REGISTERS
indicator with a ‘1’ representing PM. The clock defaults
to standard time with H21=0.
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4.Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1226 does not correct for
the leap year in the year 2100.
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
STATUS REGISTER (SR)
*n = 0 for Alarm 0: N = 1 for Alarm 1
The Status Register is located in the CCR memory
map at address 003Fh. This is a volatile register only
and is used to control the WEL and RWEL write
enable latches, read power status and two alarm bits.
This register is separate from both the array and the
Clock/Control Registers (CCR).
When there is a match, an alarm flag is set.The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
Table 2. Status Register (SR)
Addr
003Fh BAT AL1 AL0
Default
7
6
5
4
3
2
1
0
– The user can set the X1226 to alarm every Wednes-
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00 AM
Wednesday.
0
0
0
0
RWEL WEL RTCF
0
0
0
0
0
1
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from V , not V . It is a read-only bit and is set/
– A daily alarm for 9:30PM results when the EHRn*
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30 PM.
BACK
CC
reset by hardware (X1226 internally). Once the device
*n = 0 for Alarm 0: N = 1 for Alarm 1
begins operating from V , the device sets this bit to
CC
“0”.
REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SC, MN, HR, DT, MO, YR)
AL1, AL3: Alarm bits—Volatile
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is
1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.
These bits announce if either alarm 0 or alarm 1 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read opera-
tion is complete.
Date of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
default value is defined as ‘0’.
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both
the RWEL and WEL bits to be set in a specific
sequence.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12-
hour format and H21 bit functions as an AM/PM
Characteristics subject to change without notice. 5 of 24
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X1226
WEL: Write Enable Latch—Volatile
Table ±. Block Protect Bits
The WEL bit controls the access to the CCR and
memory array during a write operation. This bit is a
volatile latch that powers up in the LOW (disabled)
state. While the WEL bit is LOW, writes to the CCR or
any array address will be ignored (no acknowledge will
be issued after the Data Byte). The WEL bit is set by
writing a “1” to the WEL bit and zeroes to the other bits
of the Status Register. Once set, WEL remains set
until either reset to 0 (by writing a “0” to the WEL bit
and zeroes to the other bits of the Status Register) or
until the part powers up again. Writes to WEL bit do
not cause a nonvolatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
Protected
Addresses
X1226
Array Lock
None
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
6000h – 7FFFh
4000h – 7FFFh
0000h – 7FFFh
0000h – 007Fh
0000h – 00FFh
0000h – 01FFh
0000h – 03FFh
Upper 1/4
Upper 1/2
Full Array
First Page
First 2 pgs
First 4 pgs
First 8 Pgs
RTCF: Real Time Clock Fail Bit—Volatile
Two volatile bits (AL1 and AL0), associated with the two
alarms respectively, indicate if an alarm has happened.
These bits are set on an alarm condition regardless of
whether the IRQ interrupt is enabled. The AL1 and AL0
bits in the status register are reset by the falling edge of
the eighth clock of a read of the register containing the
bits.
This bit is set to a ‘1’ after a total power failure. This is
a read only bit that is set by hardware (X1226 inter-
nally) when the device powers up after having lost all
power to the device. The bit is set regardless of
whether V
or V
is applied first. The loss of only
CC
BACK
one of the supplies does not result in setting the RTCF
bit. The first valid write to the RTC after a complete
power failure (writing one byte is sufficient) resets the
RTCF bit to ‘0’.
Pulse Interrupt Mode
The pulsed interrrupt mode allows for repetitive or
recurring alarm functionality. Hence an repetitive or
recurring alarm can be set for every nth second, or nth
minute, or nth hour, or nth date, or for the same day of
the week. The pulsed interrupt mode can be consid-
ered a repetitive interrupt mode, with the repetition
rate set by the time setting fo the alarm.
Unused Bits:
This device does not use bits 3 or 4 in the SR, but
must have a zero in these bit positions. The Data Byte
output during a SR read will contain zeros in these bit
locations.
The Pulse Interrupt Mode is enabled when the IM bit is
set.
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
IM Bit
Interrupt / Alarm Frequency
0
Single Time Event Set By Alarm
Block Protect Bits—BP2, BP1, BP3
Repetitive / Recurring Time Event Set By
Alarm
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array.The partitions are described in Table 3.
1
The Alarm IRQ output will output a single pulse of
short duration (approximately 10-40ms) once the
alarm condition is met. If the interrupt mode bit (IM bit)
is set, then this pulse will be periodic.
INTERRUPT CONTROL AND FREQUENCY
OUTPUT REGISTER (INT)
Programmable Frequency Output Bits—FO1, FO3
Interrupt Control and Status Bits (IM, AL1E, AL3E)
These are two output control bits. They select one of
three divisions of the internal oscillator, that is applied
to the PHZ output pin. Table 4 shows the selection bits
for this output. When using the PHZ output function,
the Alarm IRQ output function is disabled.
There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output (IRQ). The interrupts are enabled when either the
AL1E and AL0E bits are set to ‘1’, respectively.
Characteristics subject to change without notice. 6 of 24
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X1226
Table 4. Programmable Frequency Output Bits
Output Frequency
The on-chip capacitance can be calculated as follows:
= [(ATR value, decimal) x 0.25pF] + 11.0pF
C
ATR
FO1 FO3
(average of 133 samples)
Alarm IRQ output
32.768kHz
Note that the ATR values are in two’s complement,
with ATR(000000) = 11.0pF, so the entire range runs
from 3.25pF to 18.75pF in 0.25pF steps.
0
0
1
1
0
1
0
1
4096Hz
The values calculated above are typical, and total load
capacitance seen by the crystal will include approxi-
mately 2pF of package and board capacitance in addi-
tion to the ATR value.
1Hz
ON-CHIP OSCILLATOR COMPENSATION
See Application Section and Xicor’s Application Note
AN154 for more information.
Digital Trimming Register (DTR) — DTR2, DTR1
and DTR3 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/
control register requires the following steps:
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
– Write a 02h to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
– Write a 06h to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit.This is also a volatile cycle.The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
A range from -30ppm to +30ppm can be represented
by using three bits above.
Table 5. Digital Trimming Registers
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete.Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write cycle,
so the sequence must be repeated to again initiate
another change to the CCR contents. If the
DTR Register
Estimated frequency
DTR2
DTR1
DTR3
PPM
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
+10
+20
+30
0
-10
-20
-30
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
Analog Trimming Register (ATR) (Non-volatile)
– Writing all zeros to the status register resets both the
WEL and RWEL bits.
Six analog trimming Bits from ATR5 to ATR3 are pro-
vided to adjust the on-chip loading capacitance range.
The on-chip load capacitance ranges from 3.25pF to
18.75pF. Each bit has a different weight for capaci-
tance adjustment. Using a Citizen CFS-206 crystal
with different ATR bit combinations provides an esti-
mated ppm range from +116ppm to -37ppm to the
nominal frequency compensation. The combination of
digital and analog trimming can give up to +146ppm
adjustment.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
Characteristics subject to change without notice. 7 of 24
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X1226
SERIAL COMMUNICATION
Interface Conventions
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 5.
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave.The master always initiates data trans-
fers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family
operate as slaves in all applications.
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 3.
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
– All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 4.
– The 2nd Data Byte of a Status Register Write Opera-
tion (only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the Standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus. See
Figure 4.
Figure ±. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Characteristics subject to change without notice. 8 of 24
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X1226
Figure 4. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Figure 5. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
DEVICE ADDRESSING
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to either the EEPROM
array or to the CCR. Slave bits ‘1010’ access the
EEPROM array. Slave bits ‘1101’ access the CCR.
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power
up the internal address counter is set to address 0h, so
a current address read of the EEPROM array starts at
address 0. When required, as part of a random read,
the master must supply the 2 Word Address Bytes as
shown in Figure 6.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the cus-
tomer to a known state.
Bit 3 through Bit 1 of the slave byte specify the device
select bits.These are set to ‘111’.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. That is if the random read is from the
array the slave byte must be 1010111x in both
instances. Similarly, for a random read of the Clock/
Control Registers, the slave byte must be 1101111x in
both places.
The last bit of the Slave Address Byte defines the oper-
ation to be performed. When this R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 6.
After loading the entire Slave Address Byte from the
SDA bus, the X1226 compares the device identifier
Characteristics subject to change without notice. 9 of 24
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X1226
Figure 6. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Device Identifier
Slave Address Byte
Byte 0
Array
CCR
1
1
0
1
1
0
0
1
1
0
1
1
R/W
A8
Word Address 1
Byte 1
0
0
0
0
0
0
Word Address 0
Byte 2
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
Data Byte
Byte 3
Write Operations
Byte Write
receipt of each address byte, the X1226 responds with
an acknowledge. After receiving both address bytes
the X1226 awaits the eight bits of data. After receiving
the 8 data bits, the X1226 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1226 then begins
an internal write cycle of the data to the nonvolatile
memory. During the internal write cycle, the device
inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance. See Figure 7.
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
Figure 7. Byte Write Sequence
S
t
a
r
Signals from
the Master
S
t
o
p
Slave
Address
Word
Address 1
Word
Address 0
t
Data
SDA Bus
1
1 1 1 0 0 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Figure 8. Writing 30 bytes to a 64-byte memory page starting at address 40.
7 Bytes
23 Bytes
Address Pointer
Ends Here
Addr = 7
Address
Address
= 6
Address
40
63
Characteristics subject to change without notice. 10 of 24
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X1226
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the write
command, the X1226 will not initiate an internal write
cycle, and will continue to ACK commands.
tion 60 of the memory and loads 30 bytes, then the first
23 bytes are written to addresses 40 through 63, and
the last 7 bytes are written to columns 0 through 6.
Afterwards, the address counter would point to location
7 on the page that was just written. If the master sup-
plies more than the maximum bytes in a page, then the
previously loaded data is over written by the new data,
one byte at a time. Refer to Figure 8.
Page Write
The X1226 has a page write operation. It is initiated in
the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit up to 63
more bytes to the memory array and up to 7 more
bytes to the clock/control registers. (Note: Prior to writ-
ing to the CCR, the master must write a 02h, then 06h
to the status register in two preceding operations to
enable the write operation. See “Writing to the Clock/
Control Registers.”
The master terminates the Data Byte loading by issu-
ing a stop condition, which causes the X1226 to begin
the nonvolatile write cycle. As with the byte write oper-
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 9 for the address,
acknowledge, and data transfer sequence.
Stops and Write Modes
After the receipt of each byte, the X1226 responds with
an acknowledge, and the address is internally incre-
mented by one. When the counter reaches the end of
the page, it “rolls over” and goes back to the first
address on the same page. This means that the mas-
ter can write 64 bytes to a memory array page or 8
bytes to a CCR section starting at any location on that
page. For example, if the master begins writing at loca-
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X1226 resets itself without per-
forming the write. The contents of the array are not
affected.
Figure 9. Page Write Sequence
1 ≤ n ≤ 64 for EEPROM array
1 ≤ n ≤ 8 for CCR
S
t
a
r
Signals from
the Master
S
t
o
p
Word
Address 1
Slave
Address
Word
Address 0
Data
(1)
Data
(n)
t
SDA Bus
1
1 1 1 0
0 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Characteristics subject to change without notice. 11 of 24
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X1226
Acknowledge Polling
Figure 11. Acknowledge Polling Sequence
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
X1226 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do this,
the master issues a start condition followed by the
Memory Array Slave Address Byte for a write or read
operation (AEh or AFh). If the X1226 is still busy with
the nonvolatile write cycle then no ACK will be
returned. When the X1226 has completed the write
operation, an ACK is returned and the host can pro-
ceed with the read or write operation. Refer to the flow
chart in Figure 11. Note: Do not use the CCR Salve
byte (DEh or DFh) for Acknowledge Polling.
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Memory Array Slave
Address Byte
AFh (Read) or AEh (Write)
Issue STOP
NO
ACK
returned?
YES
Read Operations
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
NO
nonvolatile write
Cycle complete. Continue
command sequence?
Issue STOP
Current Address Read
YES
Internally the X1226 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the sixteen bit
address is initialized to 0h. In this way, a current
address read immediately after the power on reset can
download the entire contents of memory starting at the
first location.Upon receipt of the Slave Address Byte
with the R/W bit set to one, the X1226 issues an
acknowledge, then transmits eight data bits. The mas-
ter terminates the read operation by not responding
with an acknowledge during the ninth clock and issuing
a stop condition. Refer to Figure 10 for the address,
acknowledge, and data transfer sequence.
Continue normal
Read or Write
command
sequence
PROCEED
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Figure 13. Current Address Read Sequence
S
t
S
t
Signals from
a
Slave
Address
o
the Master
r
t
p
SDA Bus
1
1 1 1 1
A
C
K
Signals from
the Slave
Data
Characteristics subject to change without notice. 12 of 24
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X1226
Random Read
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Random read operations allow the master to access
any location in the X1226. Prior to issuing the Slave
Address Byte with the R/W bit set to zero, the master
must first perform a “dummy” write operation.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indi-
cating it requires additional data. The device continues
to output data for each acknowledge received.The mas-
ter terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipt of
each word address byte, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
data word. The master terminates the read operation
by not responding with an acknowledge and then issu-
ing a stop condition. Refer to Figure 12 for the address,
acknowledge, and data transfer sequence.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to the start of the address space and the
X1226 continues to output data for each acknowledge
received. Refer to Figure 13 for the acknowledge and
data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 12. The X1226 then
goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
Figure 12. Random Address Read Sequence
S
t
S
S
t
o
p
t
a
r
Signals from
the Master
Slave
Address
Word
Address 0
a
r
Slave
Address
Word
Address 1
t
t
SDA Bus
1
1 1 1 1
1
1 1 1 0
0 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
Figure 1±. Sequential Read Sequence
S
t
o
p
Slave
Address
A
C
K
A
C
K
A
C
K
Signals from
the Master
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
Characteristics subject to change without notice. 13 of 24
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X1226
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................... -65°C to +135°C
Storage Temperature......................... -65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect
device reliability.
Voltage on V , V
and PHZ/IRQ
CC BACK
pin (respect to ground)............................-0.5V to 7.0V
Voltage on SCL, SDA, X1 and X2
pin (respect to ground)............... -0.5V to 7.0V or 0.5V
above V or V
(whichever is higher)
CC
BACK
DC Output Current .............................................. 5 mA
Lead Temperature (Soldering, 10 sec) ...............300°C
DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.)
Symbol
Parameter
Conditions
Min
2.7
Typ
Max
5.5
Unit
V
Notes
V
Main Power Supply
Backup Power Supply
Switch to Backup Supply
Switch to Main Supply
CC
V
1.8
5.5
V
BACK
V
V
V
-0.2
V
-0.1
V
CB
BC
BACK
BACK
V
V
+0.2
V
BACK
BACK
OPERATING CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
µA
Notes
V
V
V
V
V
V
= 2.7V
= 5.0V
= 2.7V
= 5.0V
= 2.7V
= 5.0V
400
800
2.5
3.0
10
Read Active Supply
Current
CC
CC
CC
CC
CC
CC
I
I
I
1, 5, 7, 14
CC1
CC2
CC3
µA
mA
mA
µA
ProgramSupplyCurrent
(nonvolatile)
2, 5, 7, 14
Main Timekeeping
Current
3, 7, 8, 14, 15
20
µA
V
= 1.8V
= 3.3V
1.25
1.5
µA
3, 6, 9, 14, 15
“See Perfor-
mance Data”
BACK
BACK
I
Timekeeping Current
BACK
V
µA
I
Input Leakage Current
Output Leakage Current
10
µA
µA
10
10
LI
I
10
LO
V
V
x 0.2 or
CC
V
Input LOW Voltage
Input HIGH Voltage
-0.5
V
V
V
13
13
13
IL
x 0.2
BACK
V
V
x 0.7 or
V
V
+ 0.5 or
CC
CC
V
IH
x 0.7
+ 0.5
BACK
BACK
Schmitt Trigger Input
Hysteresis
.05 x V or
CC
V
V
related level
HYS
CC
.05 x V
BACK
V
V
V
V
V
V
= 2.7V
= 5.5V
= 2.7V
= 5.5V
= 2.7V
= 5.5V
0.4
0.4
Output LOW Voltage for
SDA
CC
CC
CC
CC
CC
CC
V
V
V
V
11
11
12
OL1
OL2
OH2
V
x 0.3
Output LOW Voltage for
PHZ/IRQ
CC
CC
V
V
x 0.3
V
V
x 0.7
x 0.7
Output HIGH Voltage
for PHZ/IRQ
CC
CC
V
Characteristics subject to change without notice. 14 of 24
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X1226
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave
Address Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for t
.
WC
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; t
after a
WC
stop that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in
the Slave Address Byte.
(4) For reference only and not tested.
(5)
(6)
(7)
(8)
(9)
V
V
V
V
V
= V x 0.1, V = V x 0.9, f
= 400KHz
SCL
IL
CC
IH
CC
= 0V
CC
= 0V
BACK
= V
=V , Others = GND or V
CC
SDA
SDA
SDA
SCL CC
=V
=V
, Others = GND or V
SCL BACK BACK
(10) V
= GND or V , V
= GND or V
CC SCL CC
(11) I = 3.0mA at 5.5V, 1.5mA at 2.7V
OL
(12) I
= -1.0mA at 5.5V, -0.4mA at 2.7V
OH
(13) Threshold voltages based on the higher of Vcc or Vback.
(14) Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15) Typical values are for T = 25°C
A
Capacitance T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol
Parameter
Output Capacitance (SDA, PHZ/IRQ)
Input Capacitance (SCL)
Max.
10
Units
pF
Test Conditions
= 0V
(1)
C
V
OUT
OUT
(1)
C
10
pF
V
= 0V
IN
IN
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
V
x 0.1 to V x 0.9
CC
CC
Input Rise and Fall Times
10ns
Input and Output Timing
Levels
V
x 0.5
CC
Output Load
Standard Output Load
Figure 14. Standard Output Load for testing the device with V = 5.3V
CC
Equivalent AC Output Load Circuit for V
= 5V
CC
5.0V
5.0V
For V = 0.4V
OL
1316Ω
806Ω
1533Ω
and I = 3 mA
OL
PHZ/IRQ
SDA
100pF
100pF
Characteristics subject to change without notice. 15 of 24
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X1226
AC Specifications (T = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)
A
Symbol
Parameter
Min.
Max. Units
f
SCL Clock Frequency
400
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
pF
SCL
t
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
50(1)
IN
t
0.1
0.9
AA
t
1.3
BUF
t
1.3
LOW
t
Clock HIGH Time
0.6
HIGH
t
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
t
t
0.6
100
t
t
Data In Hold Time
0
Stop Condition Setup Time
Data Output Hold Time
0.6
t
50
DH
t
SDA and SCL Rise Time
20 +.1Cb(2)
20 +.1Cb(2)
300
300
400
R
t
SDA and SCL Fall Time
F
Cb
Capacitive load for each bus line
Notes: (1) This parameter is not 100% tested.
(2) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA IN
t
t
t
BUF
AA
DH
SDA OUT
Characteristics subject to change without notice. 16 of 24
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X1226
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
t
WC
Stop
Start
Condition
Condition
Power Up Timing
Symbol
Parameter
Min.
Typ.(2)
Max.
Units
ms
(1)
t
Time from Power Up to Read
Time from Power Up to Write
1
5
PUR
(1)
t
ms
PUW
Notes: (1) Delays are measured from the time V
is stable until the specified operation can be initiated. These parameters are not 100%
CC
tested.V slew rate should be between 0.2mV/µsec and 50mV/µsec.
CC
(2) Typical values are for T = 25°C and V = 5.0V
A
CC
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
(1)
t
Write Cycle Time
5
10
ms
WC
Note: (1) t
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
WC
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Characteristics subject to change without notice. 17 of 24
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X1226
APPLICATION SECTION
cally 25 deg C, and a peak drift of >110ppm occurs at
the temperature extremes of –40 and +85 deg C. It is
possible to address this variable drift by adjusting the
load capacitance of the crystal, which will result in pre-
dictable change to the crystal frequency. The Xicor
RTC family allows this adjustment over temperature
since the devices include on-chip load capacitor trim-
ming. This control is handled by the Analog Trimming
Register, or ATR, which has 6 bits of control. The load
capacitance range covered by the ATR circuit is
approximately 3.25pF to 18.75pF, in 0.25pf incre-
ments. Note that actual capacitance would also
include about 2pF of package related capacitance. In-
circuit tests with commercially available crystals dem-
onstrate that this range of capacitance allows fre-
quency control from +116ppm to –37ppm, using a
12.5pF load crystal.
CRYSTAL OSCILLATOR AND TEMPERATURE
COMPENSATION
Xicor has now integrated the oscillator compensation
circuity on-chip, to eliminate the need for external com-
ponents and adjust for crystal drift over temperature
and enable very high accuracy time keeping (<5ppm
drift).
The Xicor RTC family uses an oscillator circuit with on-
chip crystal compensation network, including adjust-
able load-capacitance. The only external component
required is the crystal. The compensation network is
optimized for operation with certain crystal parameters
which are common in many of the surface mount or
tuning-fork crystals available today. Table 6 summa-
rizes these parameters.
In addition to the analog compensation afforded by the
adjustable load capacitance, a digital compensation
feature is available for the Xicor RTC family. There are
three bits known as the Digital Trimming Register or
DTR, and they operate by adding or skipping pulses in
the clock signal. The range provided is 30ppm in
increments of 10ppm. The default setting is 0ppm. The
DTR control can be used for coarse adjustments of
frequency drift over temperature or for crystal initial
accuracy correction.
Table 7 contains some crystal manufacturers and part
numbers that meet the requirements for the Xicor RTC
products.
The turnover temperature in Table 6 describes the
temperature where the apex of the of the drift vs. tem-
perature curve occurs. This curve is parabolic with the
drift increasing as (T-T0)2. For an Epson MC-405
device, for example, the turnover temperature is typi-
Table 6. Crystal Parameters Required for Xicor RTC’s
Parameter
Min
Typ
Max
Units
kHz
Notes
Frequency
32.768
Freq. Tolerance
100
30
ppm
Down to 20ppm if desired
Typically the value used for most
crystals
Turnover Temperature
20
25
°C
Operating Temperature Range
Parallel Load Capacitance
Equivalent Series Resistance
-40
85
°C
pF
kΩ
12.5
50
For best oscillator performance
Table 7. Crystal Manufacturers
Manufacturer
Citizen
Part Number
CM201, CM202, CM200S
MC-405, MC-406
RSM-200S-A or B
32S12A or B
Temp Range
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-10 to +60°C
-10 to +60°C
-40 to +85°C
+25°C Freq Toler.
20ppm
Epson
20ppm
Raltron
SaRonix
Ecliptek
ECS
20ppm
20ppm
ECPSM29T-32.768K
ECX-306/ECX-306I
FSM-327
20ppm
20ppm
Fox
20ppm
Characteristics subject to change without notice. 18 of 24
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X1226
A final application for the ATR control is in-circuit cali-
bration for high accuracy applications, along with a
temperature sensor chip. Once the RTC circuit is pow-
ered up with battery backup, the PHZ output is set at
32.768kHz and frequency drift is measured. The ATR
control is then adjusted to a setting which minimizes
drift. Once adjusted at a particular temperature, it is
possible to adjust at other discrete temperatures for
minimal overall drift, and store the resulting settings in
the EEPROM. Extremely low overall temperature drift
is possible with this method. The Xicor evaluation
board contains the circuitry necessary to implement
this control.
ground near the X1 and X2 pins should be avoided as
it will add to the load capacitance at those pins. Keep in
mind these guidelines for other PCB layers in the vicin-
ity of the RTC device. A small decoupling capacitor at
the Vcc pin of the chip is mandatory, with a solid con-
nection to ground.
The X1226 product has a special consideration. The
PHZ/IRQ- pin on the 8-lead SOIC package is located
next to the X2 pin. When this pin is used as a fre-
quency output (PHZ) and is set to 32.768kHz output
frequency, noise can couple to the X1 or X2 pins and
cause double-clocking. The layout in figure 15 can help
minimize this by running the PHZ output away from the
X1 and X2 pins. Also, minimizing the switching current
at this pin by careful selection of the pullup resistor
value will reduce noise. Xicor suggests a minimum
value of 5.1kΩ for 32.768kHz, and higher values (up to
20kΩ) for lower frequency PHZ outputs.
For more detailed operation see Xicor’s application
note AN154 on Xicor’s website at www.xicor.com.
Layout Considerations
The crystal input at X1 has a very high impedance and
will pick up high frequency signals from other circuits
on the board. Since the X2 pin is tied to the other side
of the crystal, it is also a sensitive node. These signals
can couple into the oscillator circuit and produce dou-
ble clocking or mis-clocking, seriously affecting the
accuracy of the RTC. Care needs to be taken in layout
of the RTC circuit to avoid noise pickup. Below in Fig-
ure 15 is a suggested layout for the X1226 or X1227
devices.
For other RTC products, the same rules stated above
should be observed, but adjusted slightly since the
packages and pinouts are slightly different.
Assembly
Most electronic circuits do not have to deal with
assembly issues, but with the RTC devices assembly
includes insertion or soldering of a live battery into an
unpowered circuit. If a socket is soldered to the board,
and a battery is inserted in final assembly, then there
are no issues with operation of the RTC. If the battery
is soldered to the board directly, then the RTC device
Vback pin will see some transient upset from either sol-
dering tools or intermittent battery connections which
can stop the circuit from oscillating. Once the battery is
soldered to the board, the only way to assure the circuit
will start up is to momentarily (very short period of
time!) short the Vback pin to ground and the circuit will
begin to oscillate.
Figure 15. Suggested Layout for Xicor RTC in SO-8
Oscillator Measurements
When a proper crystal is selected and the layout guide-
lines above are observed, the oscillator should start up
in most circuits in less than one second. Some circuits
may take slightly longer, but startup should definitely
occur in less than 5 seconds. When testing RTC cir-
cuits, the most common impulse is to apply a scope
probe to the circuit at the X2 pin (oscillator output) and
observe the waveform. DO NOT DO THIS! Although in
some cases you may see a useable waveform, due to
the parasitics (usually 10pF to ground) applied with the
The X1 and X2 connections to the crystal are to be
kept as short as possible. A thick ground trace around
the crystal is advised to minimize noise intrusion, but
Characteristics subject to change without notice. 19 of 24
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X1226
scope probe, there will be no useful information in that
waveform other than the fact that the circuit is oscillat-
ing. The X2 output is sensitive to capacitive impedance
so the voltage levels and the frequency will be affected
by the parasitic elements in the scope probe. Applying
a scope probe can possibly cause a faulty oscillator to
start up, hiding other issues (although in the Xicor
RTC’s, the internal circuitry assures startup when
using the proper crystal and layout).
backup time can last from a few days to two weeks
(with >1F). A simple silicon or Schottky barrier diode
can be used in series with Vcc to charge the superca-
pacitor, which is connected to the Vback pin. Do not
use the diode to charge a battery (especially lithium
batteries!).
Figure 16. Supercapactor charging circuit
The best way to analyze the RTC circuit is to power it
up and read the real time clock as time advances, or if
the chip has the PHZ output, look at the output of that
pin on an oscilloscope (after enabling it with the control
register, and using a pullup resistor for an open-drain
output). Alternaltively, the X1226 device has an IRQ-
output which can be checked by setting an alarm for
each minute. Using the pulse interrupt mode setting,
the once-per-minute interrupt functions as an indica-
tion of proper oscillation.
2.7-5.5V
VCC
Vback
Supercapacitor
VSS
Since the battery switchover occurs at Vcc=Vback-
0.1V (see Figure 16), the battery voltage must always
be lower than the Vcc voltage during normal operation
or the battery will be drained.
Backup Battery Operation
Many types of batteries can be used with the Xicor
RTC products. 3.0V or 3.6V Lithium batteries are
appropriate, and sizes are available that can power a
Xicor RTC device for up to 10 years. Another option is
to use a supercapacitor for applications where Vcc may
disappear intermittently for short periods of time.
Depending on the value of supercapacitor used,
The summary of conditions for backup battery opera-
tion is given in Table 8:
Referring to Figure 16, Vtrip applies to the “Internal
Vcc” node which powers the entire device. This means
that if Vcc is powered down and the battery voltage at
Vback is higher than the Vtrip voltage, then the entire
Table 8. Battery Backup Operation
1. Example Application, Vcc=5V, Vback=±.3V
Condition
a. Normal Operation
Vcc
5.00
Vback
3.00
Vtrip
4.38
4.38
4.38
Iback
<<1µA
0
Notes
b. Vcc on with no battery
c. Backup Mode
5.00
0
0–1.8
1.8-3.0
<2µA
Timekeeping only
2. Example Application, Vcc=±.±V,Vback=±.3V
Condition
a. Normal Operation
Vcc
3.30
Vback
3.00
Vtrip
2.65
2.65
2.65
Iback
<<1µA
0
b. Vcc on with no battery
c. Backup Mode
3.30
0
0–1.8
1.8–3.0*
<2µA*
Timekeeping only
d. UNWANTED - Vcc ON, Vback
powering
Internal
Vcc=Vback
2.65 - 3.30
> Vcc
2.65
up to 3mA
*since Vback>2.65V is higher than Vtrip, the battery is powering the entire device
Characteristics subject to change without notice. 20 of 24
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X1226
chip will be running from the battery. If Vback falls to
lower than Vtrip, then the chip shuts down and all out-
puts are disabled except for the oscillator and time-
keeping circuitry. The fact that the chip can be powered
from Vback is not necessarily an issue since standby
current for the RTC devices is <2µA for this mode
(called “main timekeeping current” in the data sheet).
Only when the serial interface is active is there an
increase in supply current, and with Vcc powered
down, the serial interface will most likely be inactive.
PERFORMANCE DATA
Performance
I
BACK
I
vs. Temperature
BACK
Multi-Lot Process Variation Data
1.4
3.3V
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8V
One way to prevent operation in battery backup mode
above the Vtrip level is to add a diode drop (silicon
diode preferred) to the battery to insure it is below
Vtrip. This will also provide reverse leakage protection
which may be needed to get safety agency approval.
-40
25
60
85
One mode that should always be avoided is the opera-
tion of the RTC device with Vback greater than both
Vcc and Vtrip (Condition 2d in Table 8). This will cause
the battery to drain quickly as serial bus communica-
tion and non-volatile writes will require higher supplier
current.
Temperature °C
Characteristics subject to change without notice. 21 of 24
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X1226
PACKAGING INFORMATION
8-Lead Plastic, SOIC, Package Code S8
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050"Typical
X 45°
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 22 of 24
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X1226
PACKAGING INFORMATION
8-Lead Plastic, TSSOP, Package Code V8
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.114 (2.9)
.122 (3.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
(7.72)
(4.16)
Detail A (20X)
(1.78)
(0.42)
.031 (.80)
.041 (1.05)
(0.65)
All Measurements Are Typical
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 23 of 24
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X1226
ORDERING INFORMATION
V
Range
Package
Operating Temperature Range
Part Number 4Kb EEPROM PHZ/IRQ
CC
2.7-5.5V
8L SOIC
0–70°C
-40–85°C
0–70°C
X1226S8
X1226S8I
X1226V8
X1226V8I
8L TSSOP
-40–85°C
PART MARK INFORMATION
8-Lead TSSOP
8-Lead SOIC
Blank = 8-Lead SOIC
X1226 X
XX
YWW
XXXXX
Blank = 2.7 to 5.5V, 0 to +70°C
I = 2.7 to 5.5V, -40 to 85°C
1226 = 2.7 to 5.5V, 0 to +70°C
1226I = 2.7 to 5.5V, -40 to 85°C
LIMITED WARRANTY
©Xicor, Inc. 2003 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS ANDTRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 24 of 24
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