X2016P-55 [XICOR]
Memory IC,;
| 型号： | X2016P-55 |
| 厂家： | 
XICOR INC. |
| 描述： | Memory IC, |
| 文件： | 总21页 (文件大小：515K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION
NOTE
A
V A I L A B L E
AN56
16K
2K x 8 Bit
X20C16
High Speed AUTOSTORE™ NOVRAM
FEATURES
DESCRIPTION
• Fast access time: 35ns, 45ns, 55ns
• High reliability
—Endurance: 1,000,000 nonvolatile store
operations
—Retention: 100 years minimum
• AUTOSTORE NOVRAM
—Automatically stores RAM data into the
The Xicor X20C16 is a 2K x 8 NOVRAM featuring a
high-speed static RAM overlaid bit-for-bit with a non-
volatile electrically erasable PROM (EEPROM) and
the AUTOSTORE feature which automatically saves
the RAM contents to EEPROM at power-down. The
X20C16 is fabricated with advanced CMOS floating
gate technology to achieve high speed with low power
and wide power-supply margin. The X20C16 features
a compatible JEDEC approved pinout for byte-wide
memories, for industry standard RAMs, ROMs,
EPROMs, and EEPROMs.
EEPROM array when V
is detected
low threshold
CC
—User enabled option
—Open drain autostore status output pin
• Power-on recall
—EEPROM data automatically recalled into RAM
upon power-up
• Software data protection
—Locks out inadvertent store operations
• Low power CMOS
The NOVRAM design allows data to be easily trans-
ferred from RAM to EEPROM (store) and EEPROM to
RAM (recall). The store operation is completed in 5ms
or less and the recall operation is completed in 10µs or
less. An automatic array recall operation reloads the
contents of the EEPROM into RAM upon power-up.
—Standby: 250µA
• Infinite EEPROM array recall, and RAM read and
write cycles
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
EEPROM, and a minimum 1,000,000 store operations
to the EEPROM. Data retention is specified to be
greater than 100 years.
BLOCK DIAGRAM
V
Sense
AS
CC
EEPROM Array
High Speed
Row
Select
2K x 8
SRAM
Array
A –A
3
8
CE
OE
WE
NE
Control
Logic
Column Select
&
A –A
0
2
I/OS
A –A
9
10
I/O –I/O
0
7
Characteristics subject to change without notice. 1 of 21
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X20C16
PIN CONFIGURATION
Plastic CERDIP
TSOP
V
1
28
NE
NC
CC
WE
AS
2
27
3
26
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
A
8
4
25
A
9
5
24
NC
OE
6
23
7
X20C16 22
A
8
21
20
19
18
17
16
15
10
X20C16
9
CE
I/O
10
11
12
13
14
7
I/O
I/O
I/O
I/O
I/O
6
5
4
3
0
I/O
I/O
V
1
2
SS
LCC
SOIC
PLCC
28
27
26
25
24
23
22
A
NC
OE
10
1
2
CE
I/O
A
9
7
3
4
3
2
1
32 31 30
I/O
I/O
I/O
I/O
V
A
8
6
5
4
3
4
A
A
A
A
5
6
7
8
9
29
28
27
26
25
24
23
22
21
8
9
AS
6
5
5
WE
6
A
A
NC
NC
OE
V
4
3
CC
7
X20C16
21
NE
NC
SS
8
X20C16
(TOP VIEW)
A
A
A
I/O
20
19
18
17
16
15
2
1
0
2
1
0
9
A
I/O
I/O
10
11
12
13
A
7
10
10
11
12
13
14
CE
I/O
A
6
A
0
A
5
7
NC
I/O
A
1
A
4
I/O
6
0
14 15 16 17 18 19 20
A
2
A
3
Characteristics subject to change without notice. 2 of 21
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X20C16
PIN NAMES
Symbol
AUTOSTORE Output (AS)
AS is an open drain output which, when asserted indi-
Description
Address inputs
cates V
has fallen below the AUTOSTORE threshold
CC
A –A
0
10
(V
). AS may be wire-ORed with multiple open drain
ASTH
outputs and used as an interrupt input to a microcontroller.
I/O –I/O
0
Data input/output
Write enable
Chip enable
Output enable
Nonvolatile enable
AUTOSTORE output
+5V
7
WE
CE
OE
NE
AS
DEVICE OPERATION
The CE, OE, WE and NE inputs control the X20C16
operation.The X20C16 byte-wide NOVRAM uses a 2-line
control architecture to eliminate bus contention in a sys-
tem environment.The I/O bus will be in a high impedance
state when either OE or CE is HIGH, or when NE is LOW.
V
CC
V
Ground
SS
RAM Operations
NC
No connect
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE and OE to be LOW with WE and NE HIGH. A write
operation requires CE and WE to be LOW with NE HIGH.
There is no limit to the number of read or write operations
performed to the RAM portion of the X20C16.
PIN DESCRIPTIONS
Addresses (A –A )
0
10
The Address inputs select an 8-bit memory location
during a read or write operation.
Memory Transfer Operations
Chip Enable (CE)
There are two memory transfer operations: a recall
operation whereby the data stored in the EEPROM
array is transfered to the RAM array; and a store oper-
ation which causes the entire contents of the RAM
array to be stored in the EEPROM array.
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consump-
tion is reduced.
Output Enable (OE)
Recall operations are performed automaticaly upon
power-up and under host system control when NE, OE
and CE are LOW and WE is HIGH. The recall opera-
tion takes a maximum of 5µs.
The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Out-
put Enable LOW disables a store operation regardless
of the state of CE, WE, or NE.
SDP (Software Data Protection)
Data In/Data Out (I/O –I/O )
0
7
There are two methods on initiating a store operation.
The first is the software store command. This com-
mand takes the place of the hardware store employed
on the X20C04. This command is issued by entering
into the special command mode: NE, CE, and WE
strobe LOW while at the same time a specific address
and data combination is sent to the device. This is a
three step operation: the first address/data combina-
tion is 555[H]/AA[H]; the second combination is
2AA[H]/55[H]; and the final command conbination is
555[H]/33[H]. This sequence of pseudo write opera-
tions will immediately initiate a store operation. Refer
to the software command timing diagrams for details
on set and hold times for the various signals.
Data is written to or read from the X20C16 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CE or OE is HIGH or when NE is LOW.
Write Enable (WE)
The Write Enable input controls the writing of data to
the static RAM.
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls the recall func-
tion to the EEPROM array.
Characteristics subject to change without notice. 3 of 21
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X20C16
The second method of storing data is with the
AUTOSTORE command. When enable, data is auto-
matically stored for the RAM into the EEPROM array
The following symbol table provides a key to under-
standing the conventions used in the device timing dia-
grams. The diagrams should be used in conjunction
with the device timing specifications to determine
actual device operation and perfomance, as well as
device suitability for user’s application.
whenever V
falls below the preset Autostore thresh-
CC
old. This feature is enabled by performing the first two
steps for the software store with the command combi-
nation being 555[H]/CC[H].
SYMBOL TABLE
The AUTOSTORE feature is disable by issuing the
three step command sequence with the command
combination being 555[H]/CD[H]. The AUTOSTORE
WAVEFORM
INPUTS
OUTPUTS
feature will also be reset if V
up reset threshold (approximately 3.5V) and is then
raised back into the operation range.
falls below the power-
CC
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
Write Protection
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
The X20C16 supports two methods of protecting the
nonvolatile data.
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
– If after power-up the AUTOSTORE feature is not
enabled, no AUTOSTORE can occur.
N/A
Center Line
is High
Impedance
– V
3.0V typical.
Sense—All functions are inhibited when V
is
CC
CC
Characteristics subject to change without notice. 4 of 21
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X20C16
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... –65°C to +135°C
Storage temperature ....................... –65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any conditions other than those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
respect to V .........................................–1V to +7V
SS
D.C. output current ............................................. 10mA
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
+125°C
Supply Voltage
Limits
X20C16
5V 10ꢀ
–40°C
–55°C
Military
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
current (active)
Min.
Max.
Unit
Test Conditions
NE = WE = V , CE = OE = V
IL
l
V
100
mA
CC1
CC
IH
Address inputs = 0.4V/2.4V levels
@ f = 20MHz All I/Os = open
I
V
V
V
current during store
5
mA
mA
mA
All inputs = V
IH
All I/Os = open
CC2
CC
CC
CC
(2)
I
current during AUTOSTORE
standby current (TTL input)
2.5
10
CC3
I
CE = V , All other inputs = V
IH
All I/Os = open
SB1
IH
I
V
standby current (CMOS input)
250
µA
All inputs = V – 0.3V
CC
All I/Os = open
SB2
CC
I
Input leakage current
Output leakage current
Input LOW voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
I
= V to V , CE = V
SS CC IH
LO
OUT
(1)
V
–1
2
0.8
IL
(1)
V
Input HIGH voltage
Output LOW voltage
AUTOSTORE output
Output HIGH voltage
V
+ 0.5
CC
V
IH
V
0.4
0.4
V
I
I
I
= 4mA
OL
OL
V
V
= 1mA
= –4mA
OLAS
OLAS
V
2.4
V
OH
OH
POWER-UP TIMING
Symbol
Parameter
Max.
Unit
µs
(2)
t
Power-up to RAM operation
Power-up to nonvolatile operation
100
5
PUR
(2)
t
ms
PUW
Characteristics subject to change without notice. 5 of 21
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X20C16
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Test
Max.
10
Unit
pF
Conditions
(2)
C
Input/output capacitance
Input capacitance
V
= 0V
= 0V
I/O
I/O
(2)
C
6
pF
V
IN
IN
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
(2) This parameter is periodically sampled and not 100ꢀ tested.
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Endurance
Store cycles
Data retention
100,000
1,000,000
100
Data changes per bit
Store cycles
Years
MODE SELECTION
CE
H
L
WE
X
NE
X
H
H
H
L
OE
X
Mode
Not selected
Read RAM
I/O
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Output high Z
Output data
H
L
L
L
H
H
L
Write “1” RAM
Write “0” RAM
Array recall
Input data high
Input data low
Output high Z
Input data
L
L
L
H
L
L
L
H
H
L
Software command
Output Disabled
Not allowed
L
H
L
H
L
Output high Z
Output high Z
Output high Z
L
L
H
L
H
No operation
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input pulse levels
0V to 3V
5V
Input rise and fall times
Input and output timing levels
5ns
1.5V
735KΩ
Output
318Ω
30pF
Characteristics subject to change without notice. 6 of 21
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X20C16
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)
Read Cycle Limits
X20C16-35
–40 to +85°C
X20C16-45
Min. Max.
X20C16-55
Min. Max.
Symbol
Parameter
Read cycle time
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
35
45
55
RC
t
Chip enable access time
35
35
20
45
45
25
55
55
30
CE
t
Address access time
AA
OE
t
Output enable access time
Chip enable to output in low Z
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output in high Z
Output hold from address change
(3)
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LZ
(3)
t
OLZ
(3)
t
15
15
20
20
25
25
HZ
(3)
t
OHZ
t
OH
Note: (3) t min., t , t
min., and t
are periodically sampled and not 100ꢀ tested. t max. and t
max. are measured, with C = 5pF,
LZ
HZ OLZ
OHZ
HZ
OHZ L
from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven.
Read Cycle
t
RC
Address
CE
t
CE
t
OE
OE
WE
t
t
OLZ
OHZ
t
t
HZ
LZ
t
OH
Data Valid
Data Valid
Data I/O
t
AA
Characteristics subject to change without notice. 7 of 21
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X20C16
Write Cycle Limits
X20C16-35
X20C16-45
Min. Max.
X20C16-55
Min. Max.
Symbol
Parameter
Min.
35
30
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
Write cycle time
45
35
0
55
40
0
WC
Chip enable to end of write input
Address setup time
CW
t
AS
WP
WR
DW
t
Write pulse width
30
0
35
0
40
0
t
t
Write recovery time
Data setup to end of write
Data hold time
15
3
20
3
25
3
t
DH
(4)
t
Write Enable to output in high Z
Output active from end of write
Output enable to output in high Z
15
15
20
20
25
25
WZ
(4)
t
5
5
5
OW
(4)
t
OZ
Note: (4) t , t , t are periodically sampled and not 100ꢀ tested.
WZ OW OZ
WE Controlled Write Cycle
t
WC
Address
OE
t
CW
CE
t
t
WP
t
AS
WR
WE
t
t
OW
OZ
Data Out
Data In
t
t
DH
DW
Data Valid
Characteristics subject to change without notice. 8 of 21
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X20C16
CE Controlled Write Cycle
t
WC
Address
V
IH
OE
CE
WE
t
CW
t
t
WP
t
AS
WR
t
t
WZ
OW
Data Out
t
DW
t
DH
Data Valid
Data In
Characteristics subject to change without notice. 9 of 21
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X20C16
ARRAY RECALL CYCLE LIMITS
X20C16-35
X20C16-45
X20C16-55
Symbol
Parameter
Min.
Max.
Min.
Max.
10
Min.
Max.
10
Unit
µs
t
Array recall cycle time
10
RCC
(5)
t
Recall pulse width to initiate recall
WE setup time to NE
0.6
0
1000
40
0
1000
50
0
1000
ns
RCP
t
ns
RWE
Note: (5) The Recall Pulse Width (t
) is a minimum time that NE, OE and CE must be LOW simultaneously to insure data integrity, NE and CE.
RCP
Array Recall Cycle
t
RCC
Address
NE
t
RCP
OE
t
RWE
WE
CE
Data I/O
Characteristics subject to change without notice. 10 of 21
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X20C16
Software Command Timing Limits
X20C16-35
X20C16-45
X20C16-55
Symbol
Parameter
Min.
Max. Min.
Max.
Min.
Max.
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Store cycle time
5
5
5
STO
(6)
t
Store pulse width
30
35
35
0
40
45
45
0
50
55
55
0
SP
t
Store pulse hold time
Write cycle time
SPH
t
WC
t
Address setup time
Address hold time
AS
AH
DS
DH
t
t
0
0
0
Data setup time
15
3
20
3
25
3
t
Data hold time
(7)
t
OE disable to store function
Output enable from end of store
Nonvolatile enable to output in high Z
NE setup time
20
10
20
10
20
5
20
10
SOE
(7)
t
OEST
(7)
t
15
25
NHZ
t
5
5
5
5
NES
t
NE hold time
5
NEH
Notes: (6) The Store Pulse Width (t ) is a minimum time that NE, WE and CE must be LOW simultaneously.
SP
(7) t
, t
and t
are periodically sampled and not 100ꢀ tested.
SOE OEST
NHZ
CE Controlled Software Command Sequence
t
t
STO
WC
Address
OE
555
2AA
555
t
t
t
OEST
t
AS
SPH
SP
CE
t
AH
WE
t
t
NEH
NES
NE
t
t
SOE
NHZ
Data Out
Data In
t
t
DH
DS
AA
55
CMD
Characteristics subject to change without notice. 11 of 21
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X20C16
WE Controlled Software Command Sequence
t
t
STO
WC
Address
OE
555
2AA
555
t
OEST
CE
t
AS
t
t
SPH
SP
WE
t
AH
t
NES
t
NEH
NE
t
t
NHZ
SOE
Data Out
Data In
t
t
DS
DH
AA
55
CMD
AUTOSTORE Feature
The AUTOSTORE instruction (EAS) to the SDP regis-
ter sets the AUTOSTORE enable latch, allowing the
X20C16 to automatically perform a store operation
The AUTOSTORE feature automatically saves the con-
tents of the X20C16’s static RAM to the on-board bit-
for-bit shadow EEPROM at power-down. This circuitry
insures that no data is lost during accidental power-
downs or general system crashes, and is ideal for
microprocessor caching systems, embedded software
systems, and general system back-up memory.
whenever V
falls below the AUTOSTORE threshold
must remain above the AUTOSTORE
CC
(V
). V
ASTH
CC
Cycle End Voltage (V
) for the duration of the
ASEND
store cycle (t
). The detailed timing for this feature
ASTO
is illustrated in the AUTOSTORE timing diagram,
below. Once the AUTOSTORE cycle is initiated, all
other device func-tions are inhibited.
Characteristics subject to change without notice. 12 of 21
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X20C16
AUTOSTORE CYCLE Timing Diagrams
V
CC
5
4
3
2
1
V
V
ASTH
AUTOSTORE Cycle in Progress
ASEND
t
ASTO
Store Time
Time (ms)
V
CC
V
ASTH
0V
t
PUR
t
PUR
t
ASTO
AS
AUTOSTORE CYCLE LIMITS
Symbol
X20C16
Parameter
Min.
Max.
2.5
Unit
ms
V
t
AUTOSTORE cycle time
ASTO
V
AUTOSTORE threshold voltage
AUTOSTORE cycle end voltage
4.0
3.5
4.3
ASTH
V
V
ASEND
Characteristics subject to change without notice. 13 of 21
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X20C16
SDP (Software Data Protection)
SOFTWARE DATA PROTECTION COMMANDS
Command
Data
EAS
RAS
SS
Enable AUTOSTORE
Reset AUTOSTORE
Software Store
CC[H]
CD[H]
33[H]
Power Up
Store State Diagram
S0
No Store
ADDR 555,
Data AA
ADDR 555,
Data AA
Power Up
S1
Power
Down
Power On
Recall
No Store
ADDR 2AA,
DATA 55
ADDR 555,
Data AA
Software
Store
SS
Enabled
S2
No Store
Write: ADDR 555,
Data = Command
RAS
EAS
Store on SS
Software
Store &
or
AUTOSTORE
Enable/Reset
AUTOSTORE
Power Down
(AUTOSTORE)
Enable
EAS
SS
Characteristics subject to change without notice. 14 of 21
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X20C16
PACKAGING INFORMATION
28-Lead Hermetic, CerDIP, Package Code D28
1.490 (37.85) Max.
0.610 (15.49)
0.500 (12.70)
Pin 1
0.005 (0.127) Min.
0.100 (2.54) Max.
Seating
Plane
0.232 (5.90) Max.
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
0.125 (3.18)
0.150 (3.81) Min.
0.023 (0.58)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.038 (0.97)
0.014 (0.36)
Typ. 0.100 (2.54)
Typ. 0.055 (1.40)
Typ. 0.018 (0.46)
0.620 (15.75)
0.590 (14.99)
Typ. 0.614 (15.60)
0°
15°
0.015 (0.38)
0.008 (0.20)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 15 of 21
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X20C16
PACKAGING INFORMATION
28-Lead Plastic, PDIP, Package Code P28
1.470 (37.34)
1.400 (35.56)
0.557 (14.15)
0.510 (12.95)
Pin 1 Index
Pin 1
0.085 (2.16)
0.040 (1.02)
1.300 (33.02)
Ref.
0.160 (4.06)
0.125 (3.17)
Seating
Plane
0.030 (0.76)
0.015 (0.38)
0.160 (4.06)
0.120 (3.05)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.022 (0.56)
0.014 (0.36)
0.625 (15.88)
0.590 (14.99)
0°
15°
Typ. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 16 of 21
REV 1.0 6/21/00
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X20C16
PACKAGING INFROMATION
32-Pad Hermetic, LCC, Package Code E32
0.300 (7.62)
BSC
0.150 (3.81) BSC
0.020 (0.51) x 45° Ref.
0.015 (0.38)
0.003 (0.08)
0.095 (2.41)
0.075 (1.91)
Pin 1
0.022 (0.56)
DIA.
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
0.200 (5.08)
BSC
0.015 (0.38)
Min.
TYP. (4) PLCS.
0.028 (0.71)
0.040 (1.02) x 45° Ref.
Typ. (3) Plcs.
0.022 (0.56)
(32) Plcs.
0.050 (1.27) BSC
0.088 (2.24)
0.050 (1.27)
0.458 (11.63)
0.442 (11.22)
0.458 (11.63)
––
0.120 (3.05)
0.060 (1.52)
0.558 (14.17)
––
0.560 (14.22)
0.540 (13.71)
0.400 (10.16)
BSC
Pin 1 Index Corner
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: 1ꢀ NLT 0.005 (0.127)
Characteristics subject to change without notice. 17 of 21
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X20C16
PACKAGING INFORMATION
32-Lead Plastic, PLCC, Package Code J32
0.030" Typical
32 Places
0.050"
Typical
0.420 (10.67)
0.050"
Typical
0.510"
Typical
0.400"
0.050 (1.27) Typ.
0.300"
Ref.
0.410"
FOOTPRINT
0.021 (0.53)
0.013 (0.33)
Typ. 0.017 (0.43)
Seating Plane
0.045 (1.14) x 45°
0.004 Lead
CO – Planarity
—
0.015 (0.38)
0.495 (12.57)
0.485 (12.32)
Typ. 0.490 (12.45)
0.095 (2.41)
0.060 (1.52)
0.140 (3.56)
0.100 (2.45)
Typ. 0.136 (3.45)
0.453 (11.51)
0.447 (11.35)
Typ. 0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
Ref.
Pin 1
0.595 (15.11)
0.585 (14.86)
Typ. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
Typ. 0.550 (13.97)
0.400
Ref.
(10.16)
3° Typ.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
Characteristics subject to change without notice. 18 of 21
REV 1.0 6/21/00
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X20C16
PACKAGING INFORMATION
28-Lead Plastic, SOIC, Package Code S28
0.299 (7.59)
0.290 (7.37)
0.419 (10.64)
0.394 (10.01)
0.020 (0.508)
0.014 (0.356)
0.713 (18.11)
0.697 (17.70)
0.105 (2.67)
0.092 (2.34)
Base Plane
Seating Plane
0.012 (0.30)
0.003 (0.08)
0.050 (1.270)
BSC
0.050"Typical
0.0200 (0.5080)
0.0100 (0.2540)
X 45°
0.050"
Typical
0.013 (0.32)
0.008 (0.20)
0° – 8°
0.42" Max.
0.0350 (0.8890)
0.0160 (0.4064)
0.030"Typical
28 Places
FOOTPRINT
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
Characteristics subject to change without notice. 19 of 21
REV 1.0 6/21/00
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X20C16
PACKAGING INFORMATION
32-Lead, TSOP, Package Code T32
See Note 2
12.50 (0.492)
12.30 (0.484)
Pin #1 Ident.
O 0.76 (0.03)
0.50 (0.0197) BSC
See Note 2
8.02 (0.315)
7.98 (0.314)
0.26 (0.010)
0.14 (0.006)
1.18 (0.046)
1.02 (0.040)
0.17 (0.007)
0.03 (0.001)
Seating
Plane
0.58 (0.023)
0.42 (0.017)
14.15 (0.557)
13.83 (0.544)
14.80 0.05
(0.583 0.002)
0.30 0.05
(0.012 0.002)
Solder Pads
Typical
32 Places
15 Eq. Spc. 0.50 0.04
0.0197 0.016 = 7.50 0.06
(0.295 0.0024) Overall
Tol. Non-Cumulative
0.17 (0.007)
0.03 (0.001)
0.50 0.04
1.30 0.05
(0.0197 0.0016)
(0.051 0.002)
FOOTPRINT
NOTE:
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
Characteristics subject to change without notice. 20 of 21
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X20C16
Ordering Information
X20C16
X
X
-X
Access Time
-35 = 35ns
-45 = 45ns
-55 = 55ns
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = Mil. STD-883
Package
D = 28-Lead Cerdip
P = 28-Lead Plastic DIP
E = 32-Pad Ceramic LCC
J = 32-Lead PLCC
S = 28-Lead SOIC
T = 32-Lead TSOP
LIMITED WARRANTY
©Xicor, Inc. 2001 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS ANDTRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 21 of 21
REV 1.0 6/21/00
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