X20C04JI-15T4
更新时间：2024-09-18 15:13:35
品牌：XICOR
描述：Non-Volatile SRAM, 512X8, 150ns, CMOS, PQCC32, PLASTIC, LCC-32
概述
规格参数
数据手册X20C04JI-15T4 概述
Non-Volatile SRAM, 512X8, 150ns, CMOS, PQCC32, PLASTIC, LCC-32 SRAM
X20C04JI-15T4 规格参数
| 生命周期： | Obsolete | 包装说明： | PLASTIC, LCC-32 |
| Reach Compliance Code： | unknown | 风险等级： | 5.83 |
| 最长访问时间： | 150 ns | 其他特性： | MINIMUM 100 YEARS OF DATA RETENTION |
| JESD-30 代码： | R-PQCC-J32 | 长度： | 13.97 mm |
| 内存密度： | 4096 bit | 内存集成电路类型： | NON-VOLATILE SRAM |
| 内存宽度： | 8 | 功能数量： | 1 |
| 端口数量： | 1 | 端子数量： | 32 |
| 字数： | 512 words | 字数代码： | 512 |
| 工作模式： | ASYNCHRONOUS | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 组织： | 512X8 |
| 输出特性： | 3-STATE | 可输出： | YES |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | QCCJ |
| 封装形状： | RECTANGULAR | 封装形式： | CHIP CARRIER |
| 并行/串行： | PARALLEL | 认证状态： | Not Qualified |
| 座面最大高度： | 3.55 mm | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 4.5 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | INDUSTRIAL | 端子形式： | J BEND |
| 端子节距： | 1.27 mm | 端子位置： | QUAD |
| 宽度： | 11.43 mm | Base Number Matches： | 1 |
X20C04JI-15T4 数据手册
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PDF下载X20C04
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X20C04
512 x 8 Bit
Nonvolatile Static RAM
FEATURES
DESCRIPTION
• High Reliability
The Xicor X20C04 is a 512 x 8 NOVRAM featuring a
static RAM overlaid bit-for-bit with a nonvolatile electri-
cally erasable PROM (E2PROM). The X20C04 is fabri-
cated with advanced CMOS floating gate technology to
achieve low power and wide power-supply margin. The
X20C04 features the JEDEC approved pinout for byte-
widememories,compatiblewithindustrystandardRAMs,
ROMs, EPROMs, and E2PROMs.
—Endurance: 1,000,000 Nonvolatile Store
Operations
—Retention: 100 Years Minimum
• Power-on Recall
—E2PROM Data Automatically Recalled Into
SRAM Upon Power-up
• Lock Out Inadvertent Store Operations
• Low Power CMOS
The NOVRAM design allows data to be easily trans-
ferred from RAM to E2PROM (store) and E2PROM to
RAM (recall). The store operation is completed in 5ms or
less and the recall operation is completed in 5µs or less.
—Standby: 250µA
• Infinite E2PROM Array Recall, and RAM Read
and Write Cycles
• Compatible with X2004
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E2PROM, andaminimum1,000,000storeoperationsto
the E2PROM. Data retention is specified to be greater
than 100 years.
PIN CONFIGURATION
LCC
PLCC
PLASTIC
CERDIP
NE
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
2
WE
4
3
2
1
32 31 30
29
3
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
A
A
A
A
A
A
A
5
6
7
8
9
A
4
A
8
6
5
4
3
2
1
0
8
28
27
26
25
24
23
22
21
NC
NC
NC
OE
NC
CE
I/O
5
NC
NC
OE
NC
CE
I/O
6
7
X20C04
(TOP VIEW)
X20C04
8
10
11
12
13
9
10
11
12
13
14
7
NC
I/O
I/O
I/O
I/O
I/O
7
0
1
2
6
5
4
3
I/O
I/O
I/O
I/O
V
0
6
14 15 16 17 18 19 20
SS
3825 FHD F03
3825 FHD F02
©Xicor, Inc. 1992, 1995, 1996 Patents Pending
3825-2.8 2/24/99 T4/C0/D0 SH
Characteristics subject to change without notice
1
X20C04
PIN DESCRIPTIONS
Addresses (A0–A8)
Write Enable (WE)
The Write Enable input controls the writing of data to
both the static RAM and stores to the E2PROM.
The Address inputs select an 8-bit memory location
during a read or write operation.
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls all accesses to
the E2PROM array (store and recall functions).
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
writeoperations.WhenCEisHIGH,powerconsumption
is reduced.
PIN NAMES
Symbol
A –A
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
Nonvolatile Enable
+5V
0
8
Output Enable (OE)
I/O –I/O
0
7
TheOutputEnableinputcontrolsthedataoutputbuffers
and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of
the state of CE, WE, or NE.
WE
CE
OE
NE
Data In/Data Out (I/O0–I/O7)
V
V
CC
SS
Data is written to or read from the X20C04 through the
I/O pins. The I/O pins are placed in the high impedance
statewheneither CEor OE isHIGHorwhenNE isLOW.
Ground
NC
No Connect
3825 PGM T01
FUNCTIONAL DIAGRAM
V
SENSE
CC
EEPROM ARRAY
ROW
SELECT
RECALL
512 x 8
SRAM
A –A
3
6
ARRAY
ORE
ST
CE
OE
WE
NE
CONTROL
LOGIC
COLUMN
SELECT
&
A –A
0
2
A –A
7
8
I/OS
3825 FHD F01
I/O –I/O
0
7
2
X20C04
DEVICE OPERATION
Power-Up Recall
Upon power-up (VCC), the X20C04 performs an auto-
matic array recall. When VCC minimum is reached, the
recall is initiated, regardless of the state of CE, OE, WE
and NE.
The CE, OE, WE and NE inputs control the X20C04
operation. The X20C04 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either OE or CE is HIGH, or
when NE is LOW.
Write Protection
The X20C04 has five write protect features that are
employed to protect the contents of both the nonvolatile
memory and the RAM.
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE and OE to be LOW with WE and NE HIGH. A write
operation requires CE and WE to be LOW with NE
HIGH. There is no limit to the number of read or write
operationsperformedtotheRAMportionoftheX20C04.
• VCC Sense—All functions are inhibited when VCC is
3.5V.
• A RAM write is required before a Store Cycle is
initiated.
• Write Inhibit—Holding either OE LOW, WE HIGH,
CE HIGH, or NE HIGH during power-up and power-
down will prevent an inadvertent store operation.
• Noise Protection—A combined WE, NE, OE and
CE pulse of less than 20ns will not initiate a Store
Cycle.
• Noise Protection—A combined WE, NE, OE and
CE pulse of less than 20ns will not initiate a recall
cycle.
Nonvolatile Operations
WithNE LOW, recall operation is performed in the same
manner as RAM read operation. A recall operation
causes the entire contents of the E2PROM to be written
into the RAM array. The time required for the operation
to complete is 5µs or less. A store operation causes the
entire contents of the RAM array to be stored in the
nonvolatile E2PROM. The time for the operation to
complete is 5ms or less.
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
3
X20C04
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecificationis
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Respect to V
....................................... –1V to +7V
SS
D.C. Output Current ........................................... 10mA
Lead Temperature (Soldering, 10 seconds)..... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
Industrial
Military
0°C
+70°C
+85°C
+125°C
Supply Voltage
Limits
–40°C
–55°C
X20C04
5V ±10%
3825 PGM T02.1
3825 PGM T03
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
NE = WE = V , CE = OE = V
IL
l
V
Current (Active)
100
mA
CC1
CC
IH
Address Inputs = 0.4V/2.4V levels
@ f = 5MHz. All I/Os = Open
I
V
V
Current During Store
Standby Current
10
mA
All Inputs = V
IH
CC2
CC
CC
All I/Os = Open
I
I
10
mA
µA
CE = V
SB1
SB2
IH
(TTL Input)
All Other Inputs = V , All I/Os = Open
IH
V
Standby Current
250
All Inputs = V – 0.3V
CC
CC
(CMOS Input)
All I/Os = Open
I
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V , CE = V
IH
LO
OUT
SS
CC
(1)
V
V
V
V
–1
2
0.8
IL
(1)
V
+ 0.5
CC
V
IH
0.4
V
I
I
= 2.1mA
OL
OH
OL
2.4
V
= –400µA
OH
3825 PGM T04.3
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(2)
t
t
Power-Up to RAM Operation
100
5
µs
PUR
(2)
Power-Up to Nonvolatile Operation
ms
PUW
3825 PGM T05
CAPACITANCE TA = +25°C, F = 1MHz, VCC = 5V.
Symbol
Test
Max.
Units
Conditions
(2)
C
C
Input/Output Capacitance
Input Capacitance
10
6
pF
pF
V
V
= 0V
I/O
I/O
IN
(2)
= 0V
IN
3825 PGM T06.1
Notes: (1) V min. and V max. are for reference only and are not tested.
IL IH
(2) This parameter is periodically sampled and not 100% tested.
4
X20C04
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
100,000
1,000,000
100
Data Changes Per Bit
Store Cycles
Years
Store Cycles
Data Retention
3825 PGM T07.1
MODE SELECTION
CE
WE
NE
OE
Mode
I/O
Power
H
L
L
L
L
L
L
L
L
X
H
L
X
H
H
H
L
X
L
Not Selected
Read RAM
Output High Z
Output Data
Standby
Active
Active
Active
Active
Active
Active
Active
Active
H
H
L
Write “1” RAM
Write “0” RAM
Array Recall
Input Data High
Input Data Low
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
L
H
L
L
H
H
L
Nonvolatile Storing
Output Disabled
Not Allowed
H
L
H
L
H
L
H
No Operation
3825 PGM T09.1
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input Pulse Levels
0V to 3V
5V
Input Rise and
Fall Times
10ns
1.5V
1.92KΩ
Input and Output
Timing Levels
OUTPUT
3825 PGM T08.2
1.37KΩ
100pF
3825 FHD F04.1
5
X20C04
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)
Read Cycle Limits
X20C04-15 X20C04-20 X20C04-25
X20C04
Symbol
Parameter
Read Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Units
t
t
t
t
t
t
t
t
t
150
200
250
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
CE
AA
OE
Chip Enable Access Time
150
150
50
200
200
70
250
250
100
300
300
150
Address Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold From Address Change
(3)
0
0
0
0
0
0
0
0
LZ
(3)
OLZ
(3)
80
80
100
100
100
100
100
100
HZ
(3)
OHZ
OH
0
0
0
0
3825 PGM T10
Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
WE
t
t
OLZ
OHZ
t
t
t
LZ
HZ
OH
DATA I/O
DATA VALID
DATA VALID
t
AA
3825 FHD F05
Note: (3) t min., t , t
LZ HZ OLZ
min., and t
are periodically sampled and not 100% tested. t max. and t
HZ
max. are measured, with
OHZ
OHZ
C
= 5pF from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven.
L
6
X20C04
Write Cycle Limits
X20C04-15 X20C04-20 X20C04-25
X20C04
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Units
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
150
150
0
200
200
0
250
250
0
300
300
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CW
AS
Chip Enable to End of Write Input
Address Setup Time
Write Pulse Width
100
0
120
0
150
0
200
0
WP
WR
DW
DH
Write Recovery Time
Data Setup to End of Write
Data Hold Time
100
0
120
0
150
0
200
0
(4)
Write Enable to Output in High Z
Output Active from End of Write
Output Enable to Output in High Z
80
80
100
100
100
100
100
100
WZ
(4)
5
5
5
5
OW
(4)
OZ
3825 PGM T11
WE Controlled Write Cycle
t
WC
ADDRESS
OE
t
CW
CE
WE
t
t
t
AS
WP
WR
t
t
OZ
OW
DATA OUT
DATA IN
t
t
DW
DH
DATA VALID
3825 FHD F06
Note: (4) t , t
, and t
are periodically sampled and not 100% tested.
OZ
WZ OW
7
X20C04
CE Controlled Write Cycle
t
WC
ADDRESS
V
OE
CE
IH
t
CW
t
t
t
t
AS
WP
WR
WE
t
WZ
OW
DATA OUT
DATA IN
t
t
DW
DH
DATA VALID
3825 FHD F07.1
8
X20C04
STORE CYCLE LIMITS
X20C04-15
X20C04-20
X20C04-25
X20C04
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Units
t
t
t
Store Cycle Time
Store Pulse Width
5
5
5
5
ms
ns
ns
STC
SP
100
120
150
200
Nonvolatile Enable to
Output in High Z
80
100
100
100
NHZ
t
t
t
Output Enable From
End of Store
10
20
0
10
20
0
10
20
0
10
20
0
ns
ns
OEST
SOE
NS
OE Disable to Store
Function
NE Setup Time from WE
ns
3825 PGM T09
Store Timing
t
STC
t
SP
NE
OE
t
t
OEST
SOE
WE
t
NS
CE
t
NHZ
DATA I/O
V
MIN (5)
V
CC
CC
3825 FHD F15.1
Note: (5) X20C04 V
CC
min. = 4.5V
TheStorePulseWidth(tSP)isaminimumtimethatNE, WE andCEmustbeLOWsimultaneously.
9
X20C04
ARRAY RECALL CYCLE LIMITS
X20C04-15
X20C04-20
X20C04-25
X20C04
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Units
t
t
Array Recall Cycle Time
5
1
5
1
5
1
5
1
µs
µs
RCC
(6)
Recall Pulse Width to
InitiateRecall
0.1
0
0.12
0
0.15
0
0.2
0
RCP
t
WE Setup Time to NE
ns
RWE
3825 PGM T13.1
Array Recall Cycle
t
RCC
ADDRESS
NE
t
RCP
OE
t
RWE
WE
CE
DATA I/O
3825 FHD F10
Note: (6) The Recall Pulse Width (t
NE and CE.
) is a minimum time that NE, OE and CE must be LOW simultaneously to insure data integrity,
RCP
10
X20C04
PACKAGING INFORMATION
28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
1.490 (37.85) MAX.
0.610 (15.49)
0.500 (12.70)
PIN 1
0.005 (0.127) MIN.
0.100 (2.54) MAX.
SEATING
PLANE
0.232 (5.90) MAX.
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
0.125 (3.18)
0.150 (3.81) MIN.
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.038 (0.97)
0.023 (0.58)
0.014 (0.36)
TYP. 0.100 (2.54)
TYP. 0.055 (1.40)
TYP. 0.018 (0.46)
0.620 (15.75)
0.590 (14.99)
TYP. 0.614 (15.60)
0°
0.015 (0.38)
0.008 (0.20)
15°
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F08
11
X20C04
PACKAGING INFORMATION
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.470 (37.34)
1.400 (35.56)
0.557 (14.15)
0.510 (12.95)
PIN 1 INDEX
PIN 1
0.085 (2.16)
0.040 (1.02)
1.300 (33.02)
REF.
0.160 (4.06)
0.125 (3.17)
SEATING
PLANE
0.030 (0.76)
0.015 (0.38)
0.160 (4.06)
0.120 (3.05)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.022 (0.56)
0.014 (0.36)
0.625 (15.88)
0.590 (14.99)
0°
TYP. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F04
12
X20C04
PACKAGING INFORMATION
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
0.300 (7.62)
BSC
0.150 (3.81) BSC
0.020 (0.51) x 45° REF.
0.015 (0.38)
0.003 (0.08)
0.095 (2.41)
0.075 (1.91)
PIN 1
0.022 (0.56)
DIA.
0.006 (0.15)
0.055 (1.39)
0.200 (5.08)
BSC
0.045 (1.14)
TYP. (4) PLCS.
0.015 (0.38)
MIN.
0.028 (0.71)
0.040 (1.02) x 45° REF.
0.022 (0.56)
(32) PLCS.
TYP. (3) PLCS.
0.050 (1.27) BSC
0.458 (11.63)
0.088 (2.24)
0.050 (1.27)
0.442 (11.22)
0.120 (3.05)
0.458 (11.63)
––
0.060 (1.52)
0.558 (14.17)
––
0.560 (14.22)
0.540 (13.71)
0.400 (10.16)
BSC
PIN 1 INDEX CORNER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
3926 FHD F14
13
X20C04
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.030" TYPICAL
32 PLACES
0.050"
0.420 (10.67)
TYPICAL
0.050"
TYPICAL
0.510"
TYPICAL
0.400"
0.050 (1.27) TYP.
0.300"
REF
0.410"
FOOTPRINT
0.021 (0.53)
0.013 (0.33)
TYP. 0.017 (0.43)
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.045 (1.14) x 45°
0.015 (0.38)
0.095 (2.41)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
0.060 (1.52)
0.140 (3.56)
0.453 (11.51)
0.100 (2.45)
TYP. 0.136 (3.45)
0.447 (11.35)
TYP. 0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
REF.
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
14
X20C04
ORDERING INFORMATION
X20C04
X
X
-X
Access Time
–15 = 150ns
–20 = 200ns
–25 = 250ns
Blank = 300ns
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-833
Package
D = 28-Lead Cerdip
P = 28 Lead Plastic DIP
E = 32-Pad Ceramic LCC
J = 32-Lead PLCC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475;4,450,402;4,486,769;4,488,060;4,520,461;4,533,846;4,599,706;4,617,652;4,668,932;4,752,912;4,829,482;4,874,967;4,883,976.
Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. Acriticalcomponentisanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocausethefailure
of the life support device or system, or to affect its satety or effectiveness.
15
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