概述
规格参数
数据手册X20C16P-45 概述
High Speed AUTOSTORE⑩ NOVRAM 高速自动存储™ NOVRAM SRAM
X20C16P-45 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 包装说明： | PLASTIC, DIP-28 | Reach Compliance Code： | unknown |
| 风险等级： | 5.72 | 最长访问时间： | 45 ns |
| 其他特性： | MINIMUM 100 YEARS OF DATA RETENTION | JESD-30 代码： | R-PDIP-T28 |
| JESD-609代码： | e0 | 长度： | 36.32 mm |
| 内存密度： | 16384 bit | 内存集成电路类型： | NON-VOLATILE SRAM |
| 内存宽度： | 8 | 功能数量： | 1 |
| 端口数量： | 1 | 端子数量： | 28 |
| 字数： | 2048 words | 字数代码： | 2000 |
| 工作模式： | ASYNCHRONOUS | 最高工作温度： | 70 °C |
| 最低工作温度： | 组织： | 2KX8 | |
| 输出特性： | 3-STATE | 可输出： | YES |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | DIP |
| 封装等效代码： | DIP28,.6 | 封装形状： | RECTANGULAR |
| 封装形式： | IN-LINE | 并行/串行： | PARALLEL |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 认证状态： | Not Qualified |
| 座面最大高度： | 4.82 mm | 最大待机电流： | 0.00025 A |
| 子类别： | SRAMs | 最大压摆率： | 0.1 mA |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 4.5 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | NO |
| 技术： | CMOS | 温度等级： | COMMERCIAL |
| 端子面层： | Tin/Lead (Sn/Pb) | 端子形式： | THROUGH-HOLE |
| 端子节距： | 2.54 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 15.24 mm |
| Base Number Matches： | 1 |
X20C16P-45 数据手册
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PDF下载APPLICATION NOTE
A V A I L A B L E
AN56
16K
X20C16
2K x 8 Bit
High Speed AUTOSTORE™ NOVRAM
FEATURES
DESCRIPTION
• Fast Access Time: 35ns, 45ns, 55ns
• High Reliability
TheXicorX20C16isa2Kx8NOVRAMfeaturingahigh-
speed static RAM overlaid bit-for-bit with a nonvolatile
electrically erasable PROM (E2PROM) and the
AUTOSTORE feature which automatically saves the
RAMcontentstoE2PROMatpower-down. TheX20C16
isfabricatedwithadvancedCMOSfloatinggatetechnol-
ogy to achieve high speed with low power and wide
power-supply margin. The X20C16 features a compat-
ible JEDEC approved pinout for byte-wide memories,
for industry standard RAMs, ROMs, EPROMs, and
E2PROMs.
—Endurance: 1,000,000 Nonvolatile Store
Operations
—Retention: 100 Years Minimum
• AUTOSTORE™ NOVRAM
—Automatically Stores RAM Data Into the
E2PROM Array When VCC Low Threshold is
Detected
—User Enabled Option
—Open Drain AUTOSTORE Status Output Pin
• Power-on Recall
The NOVRAM design allows data to be easily trans-
ferred from RAM to E2PROM (store) and E2PROM to
RAM(recall). Thestoreoperationiscompletedin5msor
less and the recall operation is completed in 10µs or
less. An automatic array recall operation reloads the
contents of the E2PROM into RAM upon power-up.
—E2PROM Data Automatically Recalled Into
RAM Upon Power-up
• Software Data Protection
—Locks Out Inadvertent Store Operations
• Low Power CMOS
—Standby: 250µA
• Infinite E2PROM Array Recall, and RAM Read
and Write Cycles
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E2PROM, andaminimum1,000,000storeoperationsto
the E2PROM. Data retention is specified to be greater
than 100 years.
PIN CONFIGURATION
PLASTIC
CERDIP
TSOP
NE
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
2
WE
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
3
AS
4
A
8
A
9
LCC
PLCC
5
SOIC
6
NC
7
OE
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
OE
A
10
CE
X20C16
8
A
X20C16
10
2
4
3
2
1
32 31 30
29
9
CE
3
A
9
I/O
7
A
A
A
A
A
A
A
5
6
7
8
9
A
A
10
11
12
13
14
I/O
7
I/O
6
I/O
5
I/O
4
6
5
4
3
2
1
0
8
9
4
A
I/O
I/O
I/O
I/O
V
8
6
5
4
3
28
27
26
25
24
23
22
21
I/O
0
1
2
5
AS
NC
NC
OE
A
I/O
I/O
V
6
WE
7
X20C16
(TOP VIEW)
V
CC
NE
X20C16
I/O
3
SS
8
SS
10
11
12
13
10
3826 FHD F02
9
NC
I/O
2
1
0
CE
10
11
12
13
14
A
7
I/O
I/O
NC
I/O
7
A
3826 ILL F17.2
6
I/O
I/O
0
6
A
5
A
0
14 15 16 17 18 19 20
A
A
4
1
3826 FHD F15.1
A
3
A
2
3826 FHD F03
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
©Xicor, Inc. 1991, 1995, 1996 Patents Pending
3826-2.9 7/31/97 T4/C0/D0 SH
Characteristics subject to change without notice
1
X20C16
PIN DESCRIPTIONS
Addresses (A0–A10)
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls the recall function
2
to the E PROM array.
The Address inputs select an 8-bit memory location
during a read or write operation.
AUTOSTORE Output (AS)
AS is an open drain output which, when asserted indi-
Chip Enable (CE)
cates V has fallen below the AUTOSTORE threshold
CC
(V
). AS may be wire-ORed with multiple open drain
The Chip Enable input must be LOW to enable all read/
writeoperations.WhenCEisHIGH,powerconsumption
is reduced.
ASTH
outputsandusedasaninterruptinputtoamicrocontroller.
PIN NAMES
Output Enable (OE)
TheOutputEnableinputcontrolsthedataoutputbuffers
and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of
the state of CE, WE, or NE.
Symbol
A –A
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
0
10
I/O –I/O
0
7
WE
CE
OE
NE
AS
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X20C16 through the
I/O pins. The I/O pins are placed in the high impedance
statewheneither CE or OE isHIGHorwhen NE isLOW.
Output Enable
Nonvolatile Enable
AUTOSTORE Output
+5V
V
CC
SS
Write Enable (WE)
V
Ground
The Write Enable input controls the writing of data to the
static RAM.
NC
No Connect
3826 PGM T01
FUNCTIONAL DIAGRAM
V
SENSE
AS
CC
EEPROM ARRAY
ROW
SELECT
HIGH SPEED
RECALL
A –A
3
8
2K x 8
SRAM
ARRAY
ORE
ST
CE
OE
WE
NE
CONTROL
LOGIC
COLUMN
SELECT
&
A –A
0
A –A
2
I/OS
9
10
I/O –I/O
0
7
3826 FHD F01
2
X20C16
2
DEVICE OPERATION
matically stored from the RAM into the E PROM array
whenever V falls below the preset Autostore thresh-
CC
The CE, OE, WE, and NE inputs control the X20C16
operation. The X20C16 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either OE or CE is HIGH, or
when NE is LOW.
old. This feature is enabled by performing the first two
stepsforthesoftwarestorewiththecommandcombina-
tion being 555[H]/CC[H].
The AUTOSTORE feature is disabled by issuing the
three step command sequence with the command com-
binationbeing555[H]/CD[H].TheAUTOSTOREfeature
RAM Operations
will also be reset if V falls below the power-up reset
CC
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE and OE to be LOW with WE and NE HIGH. A write
operation requires CE and WE to be LOW with NE
HIGH. There is no limit to the number of read or write
operationsperformedtotheRAMportionoftheX20C16.
threshold (approximately 3.5V) and is then raised back
into the operation range.
Write Protection
The X20C16 supports two methods of protecting the
nonvolatile data.
Memory Transfer Operations
—If after power-up the AUTOSTORE feature is not
enabled, no AUTOSTORE can occur.
There are two memory transfer operations: a recall
operationwherebythedatastoredintheE PROMarray
2
—V Sense – All functions are inhibited when V is
CC
CC
is transferred to the RAM array; and a store operation
which causes the entire contents of the RAM array to be
≤ 3.0V typical.
2
stored in the E PROM array.
SYMBOL TABLE
The following symbol table provides a key to under-
standing the conventions used in the device timing
diagrams. The diagrams should be used in conjunction
with the device timing specifications to determine actual
device operation and performance, as well as device
suitability for user’s application.
Recall operations are performed automatically upon
power-up and under host system control when NE, OE
and CE are LOW and WE is HIGH. The recall operation
takes a maximum of 5µs.
SDP (Software Data Protection)
There are two methods of initiating a store operation.
The first is the software store command. This command
takes the place of the hardware store employed on the
X20C04. This command is issued by entering into the
special command mode: NE, CE, and WE strobe LOW
while at the same time a specific address and data
combination is sent to the device. This is a three step
operation: the first address/data combination is 555[H]/
AA[H];thesecondcombinationis2AA[H]/55[H];andthe
final command combination is 555[H]/33[H]. This se-
quence of pseudo write operations will immediately
initiate a store operation. Refer to the software com-
mand timing diagrams for details on set and hold times
for the various signals.
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
The second method of storing data is with the
AUTOSTORE command. When enabled, data is auto-
3
X20C16
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any conditions other than those
indicatedintheoperationalsectionsofthisspecificationis
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Respect to V
....................................... –1V to +7V
SS
D.C. Output Current ........................................... 10mA
Lead Temperature (Soldering, 10 seconds)...... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
Industrial
Military
0°C
+70°C
+85°C
+125°C
Supply Voltage
Limits
–40°C
–55°C
X20C16
5V ±10%
3826 PGM T02.1
3826 PGM T03.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
NE = WE = V , CE = OE = V
IL
l
V
CC
Current (Active)
100
mA
CC1
IH
Address Inputs = 0.4V/2.4V Levels
@ f = 20MHz All I/Os = Open
I
I
V
V
Current During Store
Current During
5
mA
mA
All Inputs = V
IH
CC2
CC
(2)
2.5
All I/Os = Open
CC3
CC
AUTOSTORE
I
I
V
Standby Current
10
mA
CE = V All Other Inputs = V
IH
All I/Os = Open
SB1
CC
IH,
(TTL Input)
V
CC
Standby Current
250
µA
All Inputs = V – 0.3V
SB2
CC
(CMOS Input)
All I/Os = Open
I
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
AUTOSTORE Output
Output HIGH Voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V , CE = V
IH
LO
OUT
SS
CC
(1)
V
V
V
V
V
–1
2
0.8
IL
(1)
V
+ 0.5
V
IH
CC
0.4
0.4
V
I
I
I
= 4mA
OL
OL
V
= 1mA
= –4mA
OLAS
OH
OLAS
2.4
V
OH
3826 PGM T04.3
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(2)
t
t
Power-Up to RAM Operation
100
5
µs
PUR
(2)
Power-Up to Nonvolatile Operation
ms
PUW
3826 PGM T05
CAPACITANCE T = +25°C, f = 1MHz, V = 5V.
A
CC
Symbol
Test
Max.
Units
Conditions
(2)
C
C
Input/Output Capacitance
Input Capacitance
10
6
pF
pF
V
V
= 0V
I/O
I/O
(2)
= 0V
IN
IN
3826 PGM T06.1
Notes: (1) V min. and V max. are for reference only and are not tested.
IL IH
(2) This parameter is periodically sampled and not 100% tested.
4
X20C16
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
100,000
1,000,000
100
Data Changes Per Bit
Store Cycles
Years
Store Cycles
Data Retention
3826 PGM T07.1
MODE SELECTION
CE
WE
NE
OE
Mode
I/O
Power
H
L
L
L
L
L
L
L
L
X
H
L
X
H
H
H
L
X
L
Not Selected
Read RAM
Output High Z
Output Data
Standby
Active
Active
Active
Active
Active
Active
Active
Active
H
H
L
Write “1” RAM
Write “0” RAM
Array Recall
Input Data High
Input Data Low
Output High Z
Input Data
L
H
L
L
H
H
L
Software Command
Output Disabled
Not Allowed
H
L
H
L
Output High Z
Output High Z
Output High Z
H
L
H
No Operation
3826 PGM T09
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input Pulse Levels
0V to 3V
5V
Input Rise and
Fall Times
5ns
735Ω
Input and Output
Timing Levels
1.5V
OUTPUT
3826 PGM T08.1
318Ω
30pF
3826 FHD F04
5
X20C16
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)
Read Cycle Limits
X20C16-35
–40 to +85°C
X20C16-45
X20C16-55
Symbol
Parameter
Read Cycle Time
Min.
Max.
Min.
Max.
Min.
Max. Units
t
t
t
t
t
t
t
t
t
35
45
55
ns
ns
ns
ns
ns
ns
ns
ns
RC
CE
AA
OE
Chip Enable Access Time
35
35
20
45
45
25
55
55
30
Address Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold From Address Change
(3)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LZ
(3)
OLZ
(3)
15
15
20
20
25
25
HZ
(3)
OHZ
OH
ns
3826 PGM T10
Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
WE
t
t
OLZ
OHZ
t
t
t
LZ
HZ
OH
DATA I/O
DATA VALID
DATA VALID
t
AA
3826 FHD F05
Note: (3) t min., t , t
LZ HZ OLZ
min., and t
OHZ
are periodically sampled and not 100% tested. t max. and t
HZ
max. are measured, with
OHZ
C
L
= 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven.
6
X20C16
Write Cycle Limits
X20C16-35
X20C16-45
X20C16-55
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Units
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
35
30
0
45
35
0
55
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CW
AS
Chip Enable to End of Write Input
Address Setup Time
Write Pulse Width
30
0
35
0
40
0
WP
WR
DW
DH
Write Recovery Time
Data Setup to End of Write
Data Hold Time
15
3
20
3
25
3
(4)
Write Enable to Output in High Z
Output Active from End of Write
Output Enable to Output in High Z
15
15
20
20
25
25
WZ
(4)
5
5
5
OW
(4)
ns
3826 PGM T11
OZ
WE Controlled Write Cycle
t
WC
ADDRESS
OE
t
CW
CE
WE
t
t
t
AS
t
WP
WR
t
OZ
OW
DATA OUT
DATA IN
t
t
DH
DW
DATA VALID
3826 FHD F06
Note: (4) t , t are periodically sampled and not 100% tested.
, t
WZ OW OZ
7
X20C16
CE Controlled Write Cycle
t
WC
ADDRESS
V
OE
CE
IH
t
CW
t
t
t
t
AS
WP
WR
WE
t
WZ
OW
DATA OUT
DATA IN
t
t
DW
DH
DATA VALID
3826 FHD F07.2
8
X20C16
ARRAY RECALL CYCLE LIMITS
X20C16-35
Min. Max.
X20C16-45
Min. Max.
X20C16-55
Symbol
Parameter
Min.
Max.
Units
t
t
Array Recall Cycle Time
10
10
10
µs
RCC
(5)
Recall Pulse Width to
InitiateRecall
0.6
0
1000
40
0
1000
50
0
1000
ns
RCP
t
WE Setup Time to NE
ns
RWE
3826 PGM T13
Array Recall Cycle
t
RCC
ADDRESS
NE
t
RCP
OE
t
RWE
WE
CE
DATA I/O
3826 FHD F10
Note: (5) The Recall Pulse Width (t
NE and CE.
) is a minimum time that NE, OE and CE must be LOW simultaneously to insure data integrity,
RCP
9
X20C16
Software Command Timing Limits
X20C16-35
X20C16-45
X20C16-55
Symbol
Parameter
Store Cycle Time
Min.
Max.
Min.
Max.
Min.
Max. Units
t
t
t
t
t
t
t
t
t
t
t
5
5
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STO
(6)
Store Pulse Width
30
35
35
0
40
45
45
0
50
55
55
0
SP
Store Pulse Hold Time
Write Cycle Time
SPH
WC
AS
Address Setup Time
Address Hold time
0
0
0
AH
Data Setup Time
15
3
20
3
25
3
DS
Data Hold Time
DH
(7)
OE Disable to Store Function
Output Enable from End of Store
20
10
20
10
20
10
SOE
(7)
OEST
(7)
Nonvolatile Enable to Output in
High Z
15
20
25
NHZ
t
t
NE Setup Time
NE Hold Time
5
5
5
5
5
5
ns
NES
ns
NEH
3826 PGM T12.2
CE Controlled Software Command Sequence
t
t
WC
STO
ADDRESS
OE
555
555
2AA
t
t
t
t
AS
SP
SPH
OEST
CE
t
AH
WE
t
t
NEH
NES
NE
t
t
SOE
NHZ
DATA OUT
DATA IN
t
t
DS
DH
AA
55
CMD
3826 FHD F08.2
Note: (6) The Store Pulse Width (t ) is a minimum time that NE, WE and CE must be LOW simultaneously.
SP
(7) t
, t
and t
are periodically sampled and not 100% tested.
SOE OEST
NHZ
10
X20C16
WE Controlled Software Command Sequence
t
t
STO
WC
ADDRESS
OE
555
555
2AA
t
OEST
CE
t
t
t
SPH
AS
SP
WE
t
AH
t
NES
t
NEH
NE
t
t
SOE
NHZ
DATA OUT
DATA IN
t
t
DH
DS
AA
55
CMD
3826 FHD F09.2
11
X20C16
AUTOSTORE Feature
TheAUTOSTOREinstruction(EAS)totheSDPregister
setstheAUTOSTOREenablelatch,allowingtheX20C16
to automatically perform a store operation whenever
The AUTOSTORE feature automatically saves the con-
tents of the X20C16’s static RAM to the on-board bit-for-
V
V
falls below the AUTOSTORE threshold (V
).
CC
ASTH
2
bit shadow E PROM at power-down. This circuitry in-
must remain above the AUTOSTORE Cycle End
) for the duration of the store cycle
CC
suresthatnodataislostduringaccidentalpower-downs
orgeneralsystemcrashes, andisidealformicroproces-
sor caching systems, embedded software systems, and
general system back-up memory.
Voltage (V
ASEND
(t
). The detailed timing for this feature is illustrated
ASTO
in the AUTOSTORE timing diagram, below. Once the
AUTOSTORE cycle is initiated, all other device func-
tions are inhibited.
AUTOSTORE CYCLE Timing Diagrams
V
5
4
3
2
1
CC
V
ASTH
AUTOSTORE CYCLE IN PROGRESS
V
ASEND
t
ASTO
STORE TIME
TIME (ms)
CC
V
t
V
ASTH
0V
t
PUR
t
PUR
ASTO
AS
3826 FHD F14
AUTOSTORE CYCLE LIMITS
Symbol
X20C16
Parameter
Min.
Max.
Units
t
AUTOSTORE Cycle Time
2.5
4.3
ms
V
ASTO
V
V
AUTOSTORE Threshold Voltage
AUTOSTORE Cycle End Voltage
4.0
3.5
ASTH
V
ASEND
3826 PGM T15
12
X20C16
SDP (Software Data Protection)
Store State Diagram
POWER UP
POWER UP
Power
Down
Power On
Recall
S0
NO STORE
Software
Store
Enabled
SS
ADDR 555,
DATA AA
ADDR 555,
DATA AA
RAS
EAS
S1
NO STORE
ADDR 2AA,
DATA 55
Software
Store &
AUTOSTORE
Enabled
ADDR 555,
DATA AA
Power Down
(AUTOSTORE)
S2
NO STORE
WRITE: ADDR 555,
DATA=COMMAND
EAS
SS
3826 FHD F13.1
STORE ON SS
OR
ENABLE/RESET
AUTOSTORE
3826 FHD F12.1
SOFTWARE DATA PROTECTION COMMANDS
Command
Data
EAS
RAS
SS
Enable AUTOSTORE
Reset AUTOSTORE
Software Store
CC[H]
CD[H]
33[H]
3826 PGM T14.1
13
X20C16
NOTES
14
X20C16
PACKAGING INFORMATION
28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
1.490 (37.85)
1.435 (36.45)
0.610 (15.49)
0.500 (12.70)
PIN 1
0.100 (2.54)
0.035 (0.89)
1.30 (33.02)
REF.
0.225 (5.72)
0.140 (3.56)
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.070 (1.78)
0.030 (0.76)
0.026 (0.66)
0.014 (0.36)
TYP. 0.100 (2.54)
TYP. 0.055 (1.40)
TYP. 0.018 (0.46)
0.620 (15.75)
0.590 (14.99)
TYP. 0.614 (15.60)
0°
15°
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F08
15
X20C16
PACKAGING INFORMATION
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.460 (37.08)
1.400 (35.56)
0.550 (13.97)
0.510 (12.95)
PIN 1 INDEX
PIN 1
0.085 (2.16)
0.040 (1.02)
1.300 (33.02)
REF.
0.160 (4.06)
0.125 (3.17)
SEATING
PLANE
0.030 (0.76)
0.015 (0.38)
0.150 (3.81)
0.125 (3.17)
0.110 (2.79)
0.090 (2.29)
0.062 (1.57)
0.050 (1.27)
0.020 (0.51)
0.016 (0.41)
0.610 (15.49)
0.590 (14.99)
0°
15°
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F04
16
X20C16
PACKAGING INFORMATION
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
0.150 (3.81) BSC
0.015 (0.38)
0.003 (0.08)
0.020 (0.51) x 45° REF.
0.095 (2.41)
0.075 (1.91)
PIN 1
0.022 (0.56)
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
0.200 (5.08)
BSC
TYP. (4) PLCS.
0.028 (0.71)
0.022 (0.56)
(32) PLCS.
0.040 (1.02) x 45° REF.
TYP. (3) PLCS.
0.050 (1.27) BSC
0.458 (11.63)
0.442 (11.22)
0.088 (2.24)
0.050 (1.27)
0.458 (11.63)
––
0.300 (7.62)
BSC
0.120 (3.05)
0.060 (1.52)
0.560 (14.22)
0.540 (13.71)
0.558 (14.17)
––
0.400 (10.16)
BSC
32 1
PIN 1 INDEX CORDER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NTL ±0.005 (0.127)
3926 FHD F14
17
X20C16
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.420 (10.67)
0.050 (1.27) TYP.
0.021 (0.53)
0.013 (0.33)
TYP. 0.017 (0.43)
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.045 (1.14) x 45°
0.015 (0.38)
0.095 (2.41)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
0.060 (1.52)
0.140 (3.56)
0.453 (11.51)
0.100 (2.45)
TYP. 0.136 (3.45)
0.447 (11.35)
TYP. 0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
REF.
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
18
X20C16
PACKAGING INFORMATION
28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.2980 (7.5692) 0.4160 (10.5664)
0.2920 (7.4168) 0.3980 (10.1092)
0.0192 (0.4877)
0.0138 (0.3505)
0.7080 (17.9832)
0.7020 (17.8308)
0.1040 (2.6416)
0.0940 (2.3876)
BASE PLANE
SEATING PLANE
0.0110 (0.2794)
0.050 (1.270)
BSC
0.0040 (0.1016)
0.0160 (0.4064)
0.0100 (0.2540)
X 45°
0.0125 (0.3175)
0.0090 (0.2311)
0° – 8°
0.0350 (0.8890)
0.0160 (0.4064)
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3. BACK EJECTOR PIN MARKED “KOREA”
4. CONTROLLING DIMENSION: INCHES (MM)
3926 FHD F17
19
X20C16
PACKAGING INFORMATION
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T
SEE NOTE 2
12.50 (0.492)
12.30 (0.484)
PIN #1 IDENT.
O 0.76 (0.03)
0.50 (0.0197) BSC
SEE NOTE 2
8.02 (0.315)
7.98 (0.314)
0.26 (0.010)
0.14 (0.006)
1.18 (0.046)
1.02 (0.040)
0.17 (0.007)
0.03 (0.001)
SEATING
PLANE
0.58 (0.023)
0.42 (0.017)
14.15 (0.557)
13.83 (0.544)
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
(0.012 ± 0.002)
SOLDER PADS
TYPICAL
32 PLACES
15 EQ. SPC. 0.50 ± 0.04
0.0197 ± 0.016 = 7.50 ± 0.06
(0.295 ± 0.0024) OVERALL
TOL. NON-CUMULATIVE
0.17 (0.007)
0.03 (0.001)
0.50 ± 0.04
(0.0197 ± 0.0016)
1.30 ± 0.05
(0.051 ± 0.002)
FOOTPRINT
NOTE:
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
3926 ILL F38.1
20
X20C16
ORDERING INFORMATION
X20C16
X
X
-X
Access Time
–35 = 35ns
–45 = 45ns
–55 = 55ns
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = Mil. STD 883
Package
D = 28-Lead Cerdip
P = 28 Lead Plastic Dip
E = 32-Pad Ceramic LCC
J = 32-Lead PLCC
S = 28-Lead SOIC
T = 32-Lead TSOP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967;
4,883,976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. Acriticalcomponentisanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocausethefailure
of the life support device or system, or to affect its satety or effectiveness.
21
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