X24164P-2.7 [XICOR]

Serial E2PROM; 串行E2PROM


型号：	X24164P-2.7
厂家：	XICOR INC.
描述：	Serial E2PROM 串行E2PROM 可编程只读存储器
文件：	总14页 (文件大小：62K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X24164

Preliminary Information

16K

X24164

2048 x 8 Bit

Serial E²PROM

FEATURES

DESCRIPTION

• 2.7V to 5.5V Power Supply

The X24164 is a CMOS 16,384 bit serial E²PROM,

internally organized 2048 x 8. The X24164 features a

serialinterfaceandsoftwareprotocolallowingoperation

on a simple two wire bus.

• Low Power CMOS

—Active Read Current Less Than 1 mA

—Active Write Current Less Than 3 mA

—Standby Current Less Than 50 µA

• Internally Organized 2048 x 8

• 2 Wire Serial Interface

Three device select inputs (S₀–S₂) allow up to eight

devices to share a common two wire bus.

Xicor E²PROMs are designed and tested for applica-

tions requiring extended endurance. Inherent data re-

tention is greater than 100 years.

—Bidirectional Data Transfer Protocol

• Sixteen Byte Page Write Mode

—Minimizes Total Write Time Per Byte

• Self Timed Write Cycle

—Typical Write Cycle Time of 5 ms

• High Reliability

—Endurance: 100,000 Cycles

—Data Retention: 100 Years

• Pin and Function Compatible with X24C16

• 8-Pin Plastic DIP and 8-Lead SOIC Packages

FUNCTIONAL DIAGRAM

(8) V

(4) V

H.V. GENERATION

START CYCLE

TIMING

& CONTROL

START

STOP

(5) SDA

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

+COMPARATOR

E PROM

XDEC

128 X 128

LOAD

INC

(6) SCL

(3) S

WORD

ADDRESS

COUNTER

(2) S

(1) S

R/W

YDEC

OUT

DATA REGISTER

OUT

ACK

3846 FHD F01

3846-1.2 7/30/96 T0/C1/D1 SH

Characteristics subject to change without notice

X24164

PIN DESCRIPTIONS

Serial Clock (SCL)

PIN CONFIGURATION

The SCL input is used to clock all data into and out of the

device.

DIP/SOIC

Serial Data (SDA)

TEST

SCL

SDA is a bidirectional pin used to transfer data into and

out of the device. It is an open drain output and may be

wire-ORed with any number of open drain or open

collector outputs.

X24164

SDA

3846 FHD F02

An open drain output requires the use of a pull-up

resistor. For selecting typical values, refer to the Pull-Up

Resistor selection graph at the end of this data sheet.

Device Select (S₀, S₁, S₂)

The device select inputs (S₀, S₁, S₂) are used to set the

second, third and fourth bits of the 8 bit slave address.

This allows up to eight X24164’s to share a common

bus. Theseinputscanbestaticoractivelydriven. Ifused

statically they must be tied to V_SSor V_CCas appropriate.

If actively driven, they must be driven to V_SSor V_CC. To

be compatible with the X24C16 these pins must all be

tied to V_SS

Pin Names

Symbol

Description

Device Select Inputs

Serial Data

S₀–S₂

SDA

SCL

TEST

V_SS

Serial Clock

Hold at V_SS

Ground

V_CC

Supply Voltage

3846 PGM T01

X24164

DEVICE OPERATION

Clock and Data Conventions

DatastatesontheSDAlinecanchangeonlyduringSCL

LOW. SDA state changes during SCL HIGH are re-

served for indicating start and stop conditions. Refer to

Figures 1 and 2.

The X24164 supports a bidirectional bus oriented proto-

col. The protocol defines any device that sends data onto

the bus as a transmitter, and the receiving device as the

receiver. The device controlling the transfer is a master

and the device being controlled is the slave. The master

willalwaysinitiatedatatransfers, andprovidetheclockfor

both transmit and receive operations. Therefore, the

X24164 will be considered a slave in all applications.

Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL is

HIGH. The X24164 continuously monitors the SDA and

SCL lines for the start condition and will not respond to

any command until this condition has been met.

Figure 1. Data Validity

SCL

SDA

DATA STABLE

DATA

CHANGE

3846 FHD F07

Notes: (5) Typical values are for T = 25°C and nominal supply voltage (5V)

(6) t

is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the

device requires to perform the internal write operation.

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT

STOP BIT

3846 FHD F08

X24164

Stop Condition

The X24164 will respond with an acknowledge after

recognition of a start condition and its slave address. If

both the device and a write operation have been se-

lected, the X24164 will respond with an acknowledge

after the receipt of each subsequent eight bit word.

All communications must be terminated by a stop con-

dition, which is a LOW to HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the device into the standby power mode after a read

sequence. A stop condition can only be issued after the

transmitting device has released the bus.

In the read mode the X24164 will transmit eight bits of

data, release the SDA line and monitor the line for an

acknowledge. If an acknowledge is detected and no

stop condition is generated by the master, the X24164

will continue to transmit data. If an acknowledge is not

detected, the X24164 will terminate further data trans-

missions. The master must then issue a stop condition

to return the X24164 to the standby power mode and

place the device into a known state.

Acknowledge

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device, either

master or slave, will release the bus after transmitting

eight bits. During the ninth clock cycle the receiver will

pull the SDA line LOW to acknowledge that it received

the eight bits of data. Refer to Figure 3.

Figure 3. Acknowledge Response From Receiver

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

3846 FHD F09

X24164

DEVICE ADDRESSING

The last bit of the slave address defines the operation to

be performed. When set to one a read operation is

selected, when set to zero a write operation is selected.

Following a start condition the master must output the

address of the slave it is accessing. The most significant

bitoftheslaveisaone(seeFigure4). Thenextthreebits

are the device select bits. A system could have up to

eight X24164’s on the bus. The eight addresses are

definedbythestateoftheS₀, S₁, andS₂inputs. S₁ofthe

slave address must be the inverse of the S₁input pin.

Following the start condition, the X24164 monitors the

SDA bus comparing the slave address being transmit-

ted with its slave address device type identifier. Upon a

correct compare the X24164 outputs an acknowledge

on the SDA line. Depending on the state of the R/W bit,

the X24164 will execute a read or write operation.

Figure 4. Slave Address

WRITE OPERATIONS

Byte Write

HIGH

ORDER

DEVICE

SELECT

WORD

ADDRESS

For a write operation, the X24164 requires a second

address field. This address field is the word address,

comprised of eight bits, providing access to any one of

2048 words in the array. Upon receipt of the word

address the X24164 responds with an acknowledge,

and awaits the next eight bits of data, again responding

with an acknowledge. The master then terminates the

transferbygeneratingastopcondition,atwhichtimethe

X24164 begins the internal write cycle to the nonvolatile

memory. While the internal write cycle is in progress the

X24164 inputs are disabled, and the device will not

respond to any requests from the master. Refer to

Figure5fortheaddress, acknowledgeanddatatransfer

sequence.

A0 R/W

3846 FHD F10

Thenextthreebitsoftheslaveaddressareanextension

of the array’s address and are concatenated with the

eight bits of address in the word address field, providing

direct access to the whole 2048 x 8 array.

Figure 5. Byte Write

SLAVE

ADDRESS

WORD

ADDRESS

BUS ACTIVITY:

MASTER

DATA

SDA LINE

BUS ACTIVITY:

X24164

3846 FHD F11

X24164

Page Write

Flow 1. ACK Polling Sequence

The X24164 is capable of a sixteen byte page write

operation. It is initiated in the same manner as the byte

write operation, but instead of terminating the write cycle

after the first data word is transferred, the master can

transmituptofifteenmorewords. Afterthereceiptofeach

word, the X24164 will respond with an acknowledge.

WRITE OPERATION

COMPLETED

ENTER ACK POLLING

ISSUE

START

Afterthereceiptofeachword,thefourloworderaddress

bits are internally incremented by one. The high order

seven bits of the word address remain constant. If the

master should transmit more than sixteen words prior to

generating the stop condition, the address counter will

“roll over” and the previously written data will be over-

written. As with the byte write operation, all inputs are

disabled until completion of the internal write cycle.

RefertoFigure6fortheaddress, acknowledgeanddata

transfer sequence.

ISSUE SLAVE

ADDRESS AND R/W = 0

ISSUE STOP

ACK

RETURNED?

Acknowledge Polling

YES

The disabling of the inputs can be used to take advan-

tage of the typical 5 ms write cycle time. Once the stop

condition is issued to indicate the end of the host’s write

operation the X24164 initiates the internal write cycle.

ACK polling can be initiated immediately. This involves

issuing the start condition followed by the slave address

for a write operation. If the X24164 is still busy with the

write operation no ACK will be returned. If the X24164

has completed the write operation an ACK will be

returned and the host can then proceed with the next

read or write operation. Refer to Flow 1.

OPERATION

A WRITE?

YES

ISSUE BYTE

ADDRESS

ISSUE STOP

PROCEED

3846 FHD F12

Figure 6. Page Write

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

WORD ADDRESS (n)

DATA n

DATA n+1

DATA n+15

SDA LINE

BUS ACTIVITY:

X24164

NOTE: In this example n = xxxx 0000 (B); x = 1 or 0

3846 FHD F13

X24164

READ OPERATIONS

The read operation is terminated by the master; by not

responding with an acknowledge and by issuing a stop

condition. RefertoFigure7forthesequenceofaddress,

acknowledge and data transfer.

Readoperationsareinitiatedinthesamemanneraswrite

operations with the exception that the R/W bit of the slave

address is set to a one. There are three basic read

operations: current address read, random read and se-

quential read.

Random Read

Randomreadoperationsallowthemastertoaccessany

memory location in a random manner. Prior to issuing

the slave address with the R/W bit set to one, the master

must first perform a “dummy” write operation. The mas-

ter issues the start condition, and the slave address

followed by the word address it is to read. After the word

addressacknowledge,themasterimmediatelyreissues

thestartconditionandtheslaveaddresswiththeR/W bit

set to one. This will be followed by an acknowledge from

the X24164 and then by the eight bit word. The read

operationisterminatedbythemaster;bynotresponding

with an acknowledge and by issuing a stop condition.

RefertoFigure8fortheaddress, acknowledgeanddata

transfer sequence.

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read

operation, the master must either issue a stop condition

duringtheninthcycleorholdSDAHIGHduringtheninth

clock cycle and then issue a stop condition.

Current Address Read

Internally the X24164 contains an address counter that

maintains the address of the last word accessed,

incremented by one. Therefore, if the last access (either

areadorwrite)wastoaddressn,thenextreadoperation

would access data from address n + 1. Upon receipt of

the slave address with the R/W set to one, the X24164

issues an acknowledge and transmits the eight bit word.

Figure 7. Current Address Read

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24164

DATA

3846 FHD F14

Figure 8. Random Read

SLAVE

ADDRESS

WORD

ADDRESS n

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24164

DATA n

3846 FHD F15

X24164

Sequential Read

Thedataoutputissequential,withthedatafromaddress

n followed by the data from n + 1. The address counter

for read operations increments all address bits, allowing

the entire memory contents to be serially read during

oneoperation. Attheendoftheaddressspace(address

2047), the counter “rolls over” to 0 and the X24164

continues to output data for each acknowledge re-

ceived. Refer to Figure 9 for the address, acknowledge

and data transfer sequence.

Sequential reads can be initiated as either a current

address read or random access read. The first word is

transmitted as with the other modes, however, the

master now responds with an acknowledge, indicating it

requires additional data. The X24164 continues to out-

put data for each acknowledge received. The read

operationisterminatedbythemaster;bynotresponding

with an acknowledge and by issuing a stop condition.

Figure 9. Sequential Read

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24164

DATA n

DATA n+1

DATA n+2

DATA n+x

3846 FHD F16

Figure 10. Typical System Configuration

PULL-UP

RESISTORS

SDA

SCL

MASTER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

TRANSMITTER/

RECEIVER

3846 FHD F17

X24164

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias

X24164 ...................................... –65°C to +135°C

Storage Temperature ....................... –65°C to +150°C

Voltage on any Pin with

*COMMENT

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and the functional operation of

the device at these or any other conditions above those

indicatedintheoperationalsectionsofthisspecificationis

not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

Respect to V

................................ –1.0V to +7.0V

D.C. Output Current ............................................ 5 mA

Lead Temperature (Soldering, 10 Seconds) ..... 300°C

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Supply Voltage

Limits

Commercial

Industrial

Military

0°C

70°C

+85°C

+125°C

X24164

4.5V to 5.5V

3V to 5.5V

–40°C

–55°C

X24164-3

X24164-2.7

2.7V to 5.5V

3846 PGM T02

3846 PGM T03

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)

Limits

Symbol

Parameter

Min.

Max.

Units

Test Conditions

I_CC1

V_CCSupply Current (Read)

mA SCL = V_CCX 0.1/V_CCX 0.9 Levels

@ 100 KHz, SDA = Open, All

Other

I_CC2

V_CCSupply Current (Write)

V_CCStandby Current

mA Inputs = GND or V_CC– 0.3V

(1)

I_SB1

150

µA

SCL = SDA = V_CC, All Other

Inputs = GND or V_CC– 0.3V,

V_CC= 5V ± 10%

(1)

I_SB2

V_CCStandby Current

µA

SCL = SDA = V_CC, All Other

Inputs = GND or V_CC– 0.3V,

V_CC= 3V

I_LI

Input Leakage Current

Output Leakage Current

Input Low Voltage

µA

V_IN= GND to V_CC

I_LO

V_OUT= GND to V_CC

(2)

V_lL

–1.0

V_CCx 0.3

(2)

V_IH

Input High Voltage

V_CCx 0.7 V_CC+ 0.5

0.4

V_OL

Output Low Voltage

I_OL= 3 mA

3846 PGM T04

CAPACITANCE T_A= 25°C, f = 1.0 MHz, V_CC= 5V

Symbol

Parameter

Max.

Units

Test Conditions

(3)

C_I/O

Input/Output Capacitance (SDA)

V_I/O= 0V

V_IN= 0V

(3)

C_IN

Input Capacitance (S₀, S₁, S₂, SCL)

3846 PGM T05

Notes: (1) Must perform a stop command prior to measurement.

(2) V min. and V max. are for reference only and are not 100% tested.

IL IH

(3) This parameter is periodically sampled and not 100% tested.

X24164

A.C. CONDITIONS OF TEST

EQUIVALENT A.C. LOAD CIRCUIT

Input Pulse Levels

V_CCx 0.1 to V_CCx 0.9

Input Rise and

Fall Times

1533Ω

10 ns

Input and Output

Timing Levels

OUTPUT

V_CCX 0.5

100pF

3846 PGM T06

3846 FHD F04

A.C. CHARACTERISTICS (Over recommended operating range unless otherwise specified)

Read & Write Cycle Limits

Symbol

Parameter

Min.

Max.

Units

f_SCL

T_I

SCL Clock Frequency

100

KHz

Noise Suppression Time

Constant at SCL, SDA Inputs

t_AA

SCL Low to SDA Data Out Valid

0.3

4.7

3.5

µs

t_BUF

Time the Bus Must Be Free Before a

New Transmission Can Start

t_HD:STA

t_LOW

Start Condition Hold Time

Clock Low Period

4.0

4.7

4.0

4.7

µs

t_HIGH

Clock High Period

t_SU:STA

Start Condition Setup Time

(for a Repeated Start Condition)

t_HD:DAT

t_SU:DAT

t_R

Data In Hold Time

µs

Data In Setup Time

250

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

t_F

300

t_SU:STO

t_DH

4.7

300

3846 PGM T07

POWER-UP TIMING⁽⁴⁾

Symbol

Parameter

Max.

Units

t_PUR

t_PUW

Power-up to Read Operation

Power-up to Write Operation

3846 PGM T08

Notes: (4) t

PUR

and t

are the delays required from the time V

is stable until the specified operation can be initiated. These param-

PUW

eters are periodically sampled and not 100% tested.

X24164

Bus Timing

HIGH

LOW

SCL

SU:STO

SU:STA

HD:STA

HD:DAT

SU:DAT

SDA IN

BUF

SDA OUT

3846 FHD F05

Write Cycle Limits

Symbol

(5)

Parameter

Write Cycle Time

Min.

Typ.

Max.

Units

(6)

T_WR

3846 PGM T09

The write cycle time is the time from a valid stop

condition of a write sequence to the end of the internal

erase/programcycle.Duringthewritecycle,theX24164

bus interface circuits are disabled, SDA is allowed to

remainhigh,andthedevicedoesnotrespondtoitsslave

address.

Write Cycle Timing

SCL

ACK

SDA

8th BIT

WORD n

STOP

CONDITION

START

CONDITION

3846 FHD F06

Notes: (5) Typical values are for T = 25°C and nominal supply voltage (5V).

(6) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum

time the device requires to automatically complete the internal write operation.

Guidelines for Calculating Typical Values of

Bus Pull-Up Resistors

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

120

CC MAX

=1.8KΩ

Must be

steady

Will be

steady

MIN

100

OL MIN

May change

from Low to

High

Will change

from Low to

High

MAX

BUS

MAX.

RESISTANCE

May change

from High to

Low

Will change

from High to

Low

MIN.

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

RESISTANCE

20 40 60 80

120

100

Center Line

is High

Impedance

N/A

BUS CAPACITANCE (pF)

3846 FHD F18

X24164

PACKAGING INFORMATION

8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

0.430 (10.92)

0.360 (9.14)

0.092 (2.34)

DIA. NOM.

0.255 (6.47)

0.245 (6.22)

PIN 1 INDEX

PIN 1

0.060 (1.52)

0.020 (0.51)

0.300

(7.62) REF.

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL

0.140 (3.56)

0.130 (3.30)

SEATING

PLANE

0.020 (0.51)

0.015 (0.38)

0.150 (3.81)

0.125 (3.18)

0.062 (1.57)

0.058 (1.47)

0.110 (2.79)

0.090 (2.29)

0.020 (0.51)

0.016 (0.41)

0.325 (8.25)

0.300 (7.62)

0.015 (0.38)

MAX.

0°

15°

TYP. 0.010 (0.25)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

3926 FHD F01

X24164

PACKAGING INFORMATION

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

0.150 (3.80)

0.158 (4.00)

0.228 (5.80)

0.244 (6.20)

PIN 1 INDEX

PIN 1

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

(4X) 7°

0.053 (1.35)

0.069 (1.75)

0.004 (0.19)

0.010 (0.25)

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

X 45°

0° – 8°

0.0075 (0.19)

0.010 (0.25)

0.027 (0.683)

0.037 (0.937)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS)

3926 FHD F22

X24164

ORDERING INFORMATION

X24164

-X

Range

Device

Blank = 4.5V to 5.5V

3 = 3.0V to 5.5V

2.7 = 2.7V to 5.5V

Temperature Range

Blank = 0°C to +70°C

I = –40°C to +85°C

M = –55°C to +125°C

Package

P = 8-Lead Plastic DIP

S8 = 8-Lead SOIC

Part Mark Convention

X24164

P = 8-Lead Plastic DIP

S8 = 8-Lead SOIC

Blank = 4.5V to 5.5V, 0°C to +70°C

I = 4.5V to 5.5V, –40°C to +85°C

D = 3.0V to 5.5V, 0°C to +70°C

E = 3.0V to 5.5V, –40°C to +85°C

F = 2.7V to 5.5V, 0°C to +70°C

G = 2.7V to 5.5V, –40°C to +85°C

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,

express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.

Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and

prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are

implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;

4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and

additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error

detection and correction, redundancy and back-up features to prevent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose

failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

X24164P-2.7 [XICOR]

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