X24256BI-2.5T1 [XICOR]
EEPROM, 32KX8, Serial, CMOS, PBGA8, XBGA-8;
| 型号： | X24256BI-2.5T1 |
| 厂家： | 
XICOR INC. |
| 描述： | EEPROM, 32KX8, Serial, CMOS, PBGA8, XBGA-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 内存集成电路 |
| 文件： | 总17页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256K
32K x 8 Bit
X24256
400kHz 2-Wire Serial EEPROM
DESCRIPTION
FEATURES
• 400kHz 2-wire serial interface
—Schmitt trigger input noise suppression
—Output slope control for ground bounce noise
elimination
The X24256 is a CMOS Serial EEPROM, internally
organized 32K x 8. The device features a serial inter-
face and software protocol allowing operation on a
simple two wire bus.
• Longer battery life with lower power
—Active read current less than 1mA
—Active write current less than 3mA
—Standby current less than 1µA
• 2.5V to 5.5V power supply
• 64-byte page write mode
—Minimizes total write time per word
• Internally organized 32K x 8
• Bidirectional data transfer protocol
• Self-timed write cycle
—Typical write cycle time of 5ms
• High reliability
—Endurance: 100,000 cycles
—Data retention: 100 years
• 8-lead XBGA
Two device select inputs (S –S ) allow up to 4 devices
to share a common two wire bus.
0
1
These pins have internal pull downs, so they are read
as LOW if not connected.
A WP pin, when pulled HIGH prevents any nonvolatile
writes to the array. When not connected WP is pulled
LOW, so the device is not normally protected.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
• 8-lead SOIC
• 14-lead TSSOP
BLOCK DIAGRAM
Data Register
Serial EEPROM Data
and Address (SDA)
Y Decode Logic
Command
Decode
and
Control
Logic
Page
Decode
Logic
SCL
Write Protect
Control Logic
Serial EEPROM
Array
S
S
1
0
Device
Select
Logic
32K x 8
Write Voltage
Control
WP
Characteristics subject to change without notice. 1 of 17
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X24256
PIN DESCRIPTIONS
Serial Clock (SCL)
PIN NAMES
Symbol
S , S
Description
Device Select Inputs
Serial Data
0
1
The SCL input is used to clock all data into and out of
the device.
SDA
SCL
WP
Serial Clock
Serial Data (SDA)
Write Protect
Ground
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs.
V
SS
V
Supply Voltage
No Connect
CC
NC
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
up resistor selection graph at the end of this data
sheet.
PIN CONFIGURATION
8-Lead XBGA: Top View
1
S
8
7
6
5
1
WP
Device Select (S , S )
0
1
V
2
3
4
S
V
CC
SDA
SCL
0
The device select inputs (S , S ) are used to set bits in
0
1
SS
the slave address. This allows up to four devices to
share a common bus. These inputs can be static or
actively driven. If used statically they must be tied to
NC
V
or V as appropriate. If actively driven, they must
SS
CC
14-Lead TSSOP
be driven with CMOS levels (driven to V or V ) and
CC
SS
S
S
1
2
14
13
V
CC
0
they must be constant between each start and stop
issued on the SDA bus. These pins have an active pull
down internally and will be sensed as low if the pin is
left unconnected.
WP
NC
NC
NC
1
NC
NC
NC
12
11
10
9
3
4
X24256
5
6
7
S
SCL
SDA
2
Write Protect (WP)
V
8
SS
WP must be constant between each start and stop
issued on the SDA bus and is always active (not
gated). The WP pin has an active pull down to disable
the write protection when the input is left floating. The
Write Protect input controls the Hardware Write Protect
feature. When held LOW, Protection is disabled and
the device operates normally. When this input is held
HIGH, the device is protected, preventing changes to
any and all locations in the EEPROM array.
8-Lead SOIC
S
S
S
0
1
2
1
2
8
V
CC
WP
7
6
5
X24256
SCL
SDA
3
4
V
SS
Characteristics subject to change without notice. 2 of 17
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X24256
DEVICE OPERATION
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the device will be considered a slave in all
applications.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 2. Definition of Start and Stop
SCL
SDA
Start Bit
Stop Bit
Stop Condition
The device will respond with an acknowledge after rec-
ognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent 8-bit word.
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.
Characteristics subject to change without notice. 3 of 17
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X24256
Figure 3. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
DEVICE ADDRESSING
Figure 4. Device Addressing
Following a start condition, the master must output the
address of the slave it is accessing.The first four bits of
the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next bit is a “0”. The
Device Type
Identifier
Device
Select
1
0
1
0
0
S
S
R/W
1
0
following 2 bits are the device select bits ‘0’, S and S .
1
0
This allows up to 4 devices to share a single bus.
Slave Address Byte
These bits are compared to the S and S device
0
1
select input pins. The last bit of the Slave Address Byte
defines the operation to be performed. When the R/W
bit is a one, then a read operation is selected. When it is
zero then a write operation is selected. Refer to Figure 4.
After loading the Slave Address Byte from the SDA bus,
the device compares the device type bits with the value
“1010” and the device select bits with the status of the
device select input pins. If the compare is not success-
ful, no acknowledge is output during the ninth clock
cycle and the device returns to the standby mode.
High Order Word Address
0
A14 A13 A12 A11 A10 A9 A8
X24256 Word Address Byte 1
Low Order Word Address
On power up the internal address is undefined, so the
first read or write operation must supply an address.
A7
A6
A4 A3
A2 A1
A0
A5
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in Figure 4.
Word Address Byte 0
The internal organization of the E2 array is 512 pages
by 64-bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in
bits 7 through 6 of the Word Address Byte 0. The byte
address is contained in bits 5 through 0 of the Word
Address Byte 0. See Figure 4.
D7 D6 D5
D4 D3
D2 D1 D0
Data Byte
Characteristics subject to change without notice. 4 of 17
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X24256
WRITE OPERATIONS
Byte Write
transmit up to sixty-three more words. The device will
respond with an acknowledge after the receipt of each
word, and then the byte address is internally incre-
mented by one. The page address remains constant.
When the counter reaches the end of the page, it “rolls
over” and goes back to the first byte of the current
page. This means that the master can write 64-bytes to
the page beginning at any byte. If the master begins
writing at byte 32, and loads 64-bytes, then the first
32-bytes are written to bytes 32 through 63, and the
last 16 words are written to bytes 0 through 31. After-
wards, the address counter would point to byte 32. If the
master writes more than 64-bytes, then the previously
loaded data is overwritten by the new data, one byte at
a time.
For a write operation, the device follows “3 byte” proto-
col, consisting of one Slave Address Byte, one Word
Address Byte 1, and the Word Address Byte 0, which
gives the master access to any one of the words in the
array. Upon receipt of the Word Address Byte 0, the
device responds with an acknowledge, and waits for
the first eight bits of data. After receiving the 8 bits of
the data byte, the device again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress
the device inputs are disabled and the device will not
respond to any requests from the master. The SDA pin
is at high impedance. See Figure 5.
The master terminates the data byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. Refer to Figure 6 for the address, acknowl-
edge, and data transfer sequence.
Page Write
The device is capable of a 64 byte page write operation.
It is initiated in the same manner as the byte write
operation; but instead of terminating the write operation
after the first data word is transferred, the master can
Figure 5. Byte Write Sequence
S
S
T
A
R
T
Word Address
Byte 1
Word Address
Byte 0
Signals from
the Master
Slave
Address
T
O
P
Data
SDA Bus
S 1 0 1 0 0
0
P
S1 S0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 6. Page Write Sequence
(0 ≤ n ≤ 64)
S
T
S
T
O
P
Data
(0)
Data
(n)
Signals from
Word Address
Byte 1
Word Address
Byte 0
Slave
A
the Master
Address
R
T
SDA Bus
1 0 1 0 0
0
S
S1 S0
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Characteristics subject to change without notice. 5 of 17
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X24256
Stop and Write Modes
Figure 7. Acknowledge Polling Sequence
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the device will reset itself without
performing the write. The contents of the array will not
be affected.
Byte Load Completed
By Issuing Stop
Enter ACK Polling
Issue
Start
Acknowledge Polling
The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condi-
tion followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the inter-
nal write cycle, then no ACK will be returned. If the
device has completed the internal write operation, an
ACK will be returned and the host can then proceed
with the read or write operation. Refer to Figure 7.
Issue Slave
Address Byte
(Read or Write)
Issue Stop
ACK
Returned?
No
Yes
High
Voltage
Cycle Complete.
Continue
No
Sequence?
Yes
Continue Normal
Read or Write
Issue Stop
Command Sequence
Proceed
Characteristics subject to change without notice. 6 of 17
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X24256
READ OPERATIONS
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “Dummy” write operation.
The master issues the start condition and the Slave
Address Byte with the R/W bit low, receives an
acknowledge, then issues the Word Address Byte 1,
receives another acknowledge, then issues the Word
Address Byte 0. After the device acknowledges receipt
of the Word Address Byte 0, the master issues another
start condition and the Slave Address Byte with the R/W
bit set to one. This is followed by an acknowledge and
then eight bits of data from the device. The master ter-
minates the read operation by not responding with an
acknowledge and then issuing a stop condition. Refer
to Figure 9 for the address, acknowledge, and data
transfer sequence.
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally, the device contains an address counter that
maintains the address of the last word read or written
incremented by one. After a read operation from the
last address in the array, the counter will “roll over” to
the first address in the array. After a write operation to
the last address in a given page, the counter will “roll
over” to the first address on the same page.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master ter-
minates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 8 for the
address, acknowledge, and data transfer sequence.
The device will perform a similar operation called “Set
Current Address” if a stop is issued instead of the
second start shown in Figure 9. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this oper-
ation is that the new address is loaded into the address
counter, but no data is output by the device.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
The next Current Address Read operation will read
from the newly loaded address.
Sequential Read
Figure 8. Current Address Read Sequence
Sequential reads can be initiated as either a current
address read or random read. The first Data Byte is
transmitted as with the other modes; however, the
master now responds with an acknowledge, indicating
it requires additional data. The device continues to out-
put data for each acknowledge received.The master ter-
minates the read operation by not responding with an
acknowledge and then issuing a stop condition.
S
T
A
R
T
S
T
Signals from
the Master
Slave
Address
O
P
SDA Bus
S 1 0 1 0 0 S1S0 1
P
A
C
K
Data
Signals from
the Slave
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through all byte addresses, allowing the entire memory
contents to be read during one operation. At the end of
the address space the counter “rolls over” to address
0000h and the device continues to output data for each
acknowledge received. Refer to Figure 10 for the
acknowledge and data transfer sequence.
Characteristics subject to change without notice. 7 of 17
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X24256
Figure 9. Random Read Sequence
S
T
S
T
Word Address
Byte 0
Slave
Address
S
T
O
P
Word Address
Byte 1
Slave
Address
Signals from
the Master
A
R
A
R
T
T
SDA Bus
1
S 1 0 1 0 0 S1 S0 0
S
P
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
Figure 10. Sequential Read Sequence
Signals from
Slave
S
T
O
P
A
C
K
A
C
K
A
C
K
the Master
Address
SDA Bus
1
P
0 S1 S0
A
C
K
Signals from
the Slave
Data
(1)
Data
(2)
Data
(n–1)
Data
(n)
(n is any integer greater than 1)
Characteristics subject to change without notice. 8 of 17
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X24256
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias X24256...... –65°C to +135°C
Storage Temperature........................ –65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
respect to V .........................................–1V to +7V
SS
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
Limits
X24256–2.5
2.5V to 5.5V
–40°C
D.C. OPERATING CHARACTERISTICS V equals the range indicated for each device type, unless otherwise stated.
CC
V
= 2.5 to 5.5V
CC
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
I
Active Supply Current
(Read)
1
mA
V = V X 0.1, V = V X 0.9,
CC1
IL
CC
IH
CC
f
= 400kHz, SDA = Open
SCL
I
Active Supply Current
(Write)
3
1
mA
mA
CC2
(2)
I
I
Standby Current AC
V = V X 0.1, V = V X 0.9,
SB1
IL
CC
IH
CC
f
= 400kHz, SDA = Open
SCL
V
Standby Voltage (Test)
Standby Current DC
V
– 0.2
V
SB
(2)
CC
1
mA
V
= V
= V , Others =
SB2
SDA
SCL SB
SB
GND or V
I
Input Leakage Current
Output Leakage Current
10
10
mA
mA
V
V
= GND to V
CC
LI
IN
I
= GND to V , Device is in
CC
LO
SDA
Standby(2)
(3)
V
Input LOW Voltage
Input HIGH Voltage
–0.5
x 0.7
CC
V
x 0.3
V
V
V
lL
CC
(3)
IH
V
V
V
V
+ 0.5
CC
Schmitt Trigger Input
Hysteresis Fixed input level
0.2
HYS
V
related level
V
x 0.05
V
V
CC
CC
V
Output LOW Voltage
0.4
I
= 3mA
OL
OL
Characteristics subject to change without notice. 9 of 17
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X24256
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Parameter
Max.
Unit
pF
Test Conditions
(3)
I/O
C
Input/Output Capacitance (SDA)
8
6
V
= 0V
= 0V
I/O
(3)
IN
C
Input Capacitance (S , S , SCL, WP)
pF
V
IN
0
1
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or t after a stop ending a write operation.
WC
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; t
after a stop that initiates a
WC
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) V Min. and V Max. are for reference only and are not tested.
IL
IH
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
5V
Input rise and fall times
Input and output timing levels
Output load
10ns
for V = 0.4V
OL
V
X 0.5
1.53KΩ
I
= 3mA
CC
OL
Standard output load
Output
100pF
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise stated.
Read & Write Cycle Limits
V
= 2.5V
CC
Symbol
Parameter
Min.
Max. Unit
400
f
SCL clock frequency
0
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
ns
ns
pF
SCL
t
Pulse width suppression time at inputs
SCL LOW to SDA data out valid
Time the bus must be free before a new transmission can start
Clock LOW period
50
IN
t
0.1
0.9
AA
t
1.3
BUF
t
1.3
LOW
t
Clock HIGH period
0.6
HIGH
t
Start condition setup time
Start condition hold time
0.6
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
t
t
0.6
Data in setup time
100
t
t
Data in hold time
0
0.6
Stop condition setup time
Data output hold time
t
50
DH
t
SDA and SCL rise time
20 + .1Cb(3)
300
300
R
t
SDA and SCL fall time
F
t
t
S0, S1, and WP Setup Time
S0, S1, and WP Hold Time
Capacitive load for each bus line
0.6
0
SU:S0, S1, WP
HD:S0, S1, WP
Cb
400
Characteristics subject to change without notice. 10 of 17
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X24256
POWER-UP TIMING(4)
Symbol
Parameter
Max.
Unit
ms
t
Power-up to Read Operation
Power-up to Write Operation
1
5
PUR
t
ms
PUW
Notes: (4) t
and t
are the delays required from the time V
is stable until the specified operation can be initiated. These parameters
CC
PUR
PUW
are periodically sampled and not 100% tested.
(5) Typical values are for T = 25°C and nominal supply voltage (5V), Cb = total capacitance of one bus line in pF.
A
Bus Timing
t
t
t
R
t
HIGH
LOW
F
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA IN
t
t
t
BUF
AA
DH
SDA OUT
S , S , and WP Pin Timing
0
1
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
t
t
HD: S0, S1, WP
SU: S0, S1, WP
S , S , and WP
0
1
Write Cycle Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
(6)
WC
T
Write Cycle Time
—
5
10
ms
Note: (6) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WC
time the device requires to automatically complete the internal write operation.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write
cycle. During the write cycle, the X24256 bus interface circuits are disabled, SDA is allowed to remain HIGH, and
the device does not respond to its slave address.
Characteristics subject to change without notice. 11 of 17
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X24256
Write Cycle Timing
SCL
8th Bit
ACK
SDA
Word n
t
WC
Stop
Condition
Start
Condition
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
120
V
I
CC MAX
R
=
Must be
steady
Will be
steady
MIN
100
80
OL MIN
t
R
R
=
MAX
May change
from Low to
High
Will change
from Low to
High
C
BUS
Max.
Resistance
60
40
20
0
May change
from High to
Low
Will change
from High to
Low
Min.
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
Resistance
20 40 60 80
0
100 120
N/A
Center Line
is High
Impedance
Bus Capacitance (pF)
Characteristics subject to change without notice. 12 of 17
REV 1.1.3 10/23/00
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X24256
PACKAGING INFORMATION
8-Lead Plastic, 0.200” Wide Small Outline
Gullwing Package Typ “A” (EIAJ SOIC)
0.020 (.508)
0.012 (.305)
.330 (8.38)
.300 (7.62)
.213 (5.41)
.205 (5.21)
Pin 1 ID
.050 (1.27) BSC
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
.013 (.330)
.004 (.102)
.010 (.254)
.007 (.178)
0°–8° Ref.
.035 (.889)
.020 (.508)
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 13 of 17
REV 1.1.3 10/23/00
www.xicor.com
X24256
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050"Typical
X 45°
0.020 (0.50)
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 14 of 17
REV 1.1.3 10/23/00
www.xicor.com
X24256
PACKAGING INFORMATION
8-Lead XBGA
8-Lead XBGA
Complete Part Number
X24256: Bottom View
Top Mark
A1
X24256B-2.5
X24256BI-2.5
XAAI
XAAU
S1
WP
8-Lead XBGA: Top View
PIN 1
S0
V
CC
.079”
C
S1
S0
WP
8
1
V
V
SDA
SCL
SS
CC
SDA
SCL
7
6
5
E
2
3
4
.137”
V
SS
NC
e
NC
F
DWG Symbol
8L XBGA
A
A1
C
D
E
Contact Factory
Contact Factory
Contact Factory
Contact Factory
Contact Factory
Contact Factory
Contact Factory
D
D
A1
A
e
C
F
ALL DIMENSIONS IN µM (to convert to inches, 1µm = 3.94 x 10-5 inch)
ALL DIMENSIONS ARE TYPICAL VALUES
Characteristics subject to change without notice. 15 of 17
REV 1.1.3 10/23/00
www.xicor.com
X24256
PACKAGINING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 16 of 17
REV 1.1.3 10/23/00
www.xicor.com
X24256
Ordering Information
X24256
X
X
-X
V
Range
Device
CC
2.5 = 2.5V to 5.5V
Temperature Range
Blank = 0°C to +70°C
I = –40°C to +85°C
Package
X24256
V14 = 14-Lead TSSOP
S8 = 8-Lead SOIC, 150 mil wide, JEDEC
A8 = 8-Lead SOIC, 200 mil wide, EIAJ
B = 8-Lead XBGA
Part Mark Conventions
XBGA PACKAGE
TSSOP/SOIC
X24256
Complete Part Number Top Mark
V14 = 14-Lead TSSOP
X
X24256B - 2.5
X24256BI - 2.5
XAAI
XAAU
S8 = 8-Lead SOIC (JEDEC)
A8 = 8-Lead SOIC (EIAJ)
X
AE = 2.5V to 5.5V, 0°C to +70°C
K = 2.5V to 5.5V, –40°C to +85°C
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 17 of 17
REV 1.1.3 10/23/00
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