X24C16P [XICOR]
Serial E2PROM; 串行E2PROM
| 型号： | X24C16P |
| 厂家： | 
XICOR INC. |
| 描述： | Serial E2PROM |
| 文件： | 总15页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
16K
X24C16
2048 x 8 Bit
Serial E2PROM
FEATURES
DESCRIPTION
2
• 2.7V to 5.5V Power Supply
• Low Power CMOS
—Active Read Current Less Than 1 mA
—Active Write Current Less Than 3 mA
—Standby Current Less Than 50 µA
• Internally Organized 2048 x 8
• 2 Wire Serial Interface
The X24C16 is a CMOS 16,384 bit serial E PROM,
internally organized 2048 X 8. The X24C16 features a
serialinterfaceandsoftwareprotocolallowingoperation
on a simple two wire bus.
The X24C16 is fabricated with Xicor’s advanced CMOS
Textured Poly Floating Gate Technology.
—Bidirectional Data Transfer Protocol
• Sixteen Byte Page Write Mode
—Minimizes Total Write Time Per Byte
• Self Timed Write Cycle
TM
The X24C16 utilizes Xicor’s proprietary Direct Write
cell providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
—Typical Write Cycle Time of 5 ms
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
• 8 Pin Mini-DIP, 8 Pin SOIC and 14 Pin SOIC
Packages
FUNCTIONAL DIAGRAM
(8) V
(4) V
CC
SS
(7) TEST
H.V. GENERATION
START CYCLE
TIMING
& CONTROL
START
STOP
(5) SDA
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
+COMPARATOR
2
E PROM
XDEC
128 X 128
LOAD
INC
(6) SCL
(3) A
2
WORD
ADDRESS
COUNTER
(2) A
(1) A
1
0
R/W
YDEC
8
CK
D
OUT
PIN
DATA REGISTER
D
OUT
ACK
3840 FHD F01
© Xicor, 1991 Patents Pending
3840-1.1 7/29/96 T1/C0/D0 SH
Characteristics subject to change without notice
1
X24C16
PIN DESCRIPTIONS
Serial Clock (SCL)
PIN CONFIGURATION
DIP/SOIC
The SCL input is used to clock all data into and out of the
device.
A
A
A
1
2
3
4
8
7
6
5
V
0
1
2
CC
Serial Data (SDA)
TEST
X24C16
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs.
SCL
V
SDA
SS
3840 FHD F02
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-Up
Resistor selection graph at the end of this data sheet.
SOIC
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
Address (A , A , A
2)
0
1
A
0
A
1
V
CC
The A , A and A inputs are unused by the X24C16,
0
1
2
TEST
NC
however, they must be tied to V
device operation.
to insure proper
SS
X24C16
NC
A
2
SCL
SDA
NC
PIN NAMES
V
SS
NC
8
Symbol
Description
Address Inputs
Serial Data
A –A
0
3840 FHD F03
2
SDA
SCL
Serial Clock
TEST
Hold at V
Ground
SS
V
SS
V
CC
Supply Voltage
No Connect
NC
3840 PGM T01
2
X24C16
DEVICE OPERATION
Clock and Data Conventions
DatastatesontheSDAlinecanchangeonlyduringSCL
LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions. Refer to
Figures 1 and 2.
The X24C16 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers, and provide
the clock for both transmit and receive operations.
Therefore, the X24C16 will be considered a slave in all
applications.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C16 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
3840 FHD F06
3
X24C16
Stop Condition
The X24C16 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been se-
lected, the X24C16 will respond with an acknowledge
after the receipt of each subsequent eight bit word.
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used by the
X24C16 to place the device into the standby power
mode after a read sequence. A stop condition can only
be issued after the transmitting device has released the
bus.
In the read mode the X24C16 will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the X24C16
will continue to transmit data. If an acknowledge is not
detected, the X24C16 will terminate further data trans-
missions. The master must then issue a stop condition
to return the X24C16 to the standby power mode and
place the device into a known state.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
3840 FHD F07
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
3840 FHD F08
4
X24C16
DEVICE ADDRESSING
eight bits of address in the word address field, providing
direct access to the whole 2048 x 8 array.
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(see Figure 4). For the X24C16 this is fixed as 1010[B].
Following the start condition, the X24C16 monitors the
SDA bus comparing the slave address being transmit-
ted with its slave address (device type). Upon a correct
compare the X24C16 outputs an acknowledge on the
SDA line. Depending on the state of the R/W bit, the
X24C16 will execute a read or write operation.
Figure 4. Slave Address
HIGH
ORDER
WRITE OPERATIONS
Byte Write
DEVICE TYPE
IDENTIFIER
WORD
ADDRESS
For a write operation, the X24C16 requires a second
address field. This address field is the word address,
comprisedofeightbits, providingaccesstoanyoneofthe
2048wordsinthearray. Uponreceiptofthewordaddress
the X24C16 responds with an acknowledge, and awaits
the next eight bits of data, again responding with an
acknowledge. The master then terminates the transfer by
generating a stop condition, at which time the X24C16
begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress the X24C16
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.
1
0
1
0
A2
A1
A0 R/W
3840 FHD F09
Thenextthreebitsoftheslaveaddressfieldarethebank
select bits. They are used by the host to toggle between
the eight 256 x 8 banks of memory. These are, in effect,
the most significant bits for the word address.
Thenextthreebitsoftheslaveaddressareanextension
of the array’s address and are concatenated with the
Figure 5. Byte Write
S
T
S
SLAVE
ADDRESS
WORD
ADDRESS
A
R
T
T
BUS ACTIVITY:
MASTER
DATA
O
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24C16
3840 FHD F10
5
X24C16
Page Write
Flow 1. ACK Polling Sequence
The X24C16 is capable of a sixteen byte page write
operation. It is initiated in the same manner as the byte
writeoperation,butinsteadofterminatingthewritecycle
after the first data word is transferred, the master can
transmit up to fifteen more words. After the receipt of
each word, the X24C16 will respond with an acknowl-
edge.
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
ISSUE
START
Afterthereceiptofeachword,thefourloworderaddress
bits are internally incremented by one. The high order
seven bits of the address remain constant. If the master
should transmit more than sixteen words prior to gener-
ating the stop condition, the address counter will “roll
over” and the previously written data will be overwritten.
As with the byte write operation, all inputs are disabled
until completion of the internal write cycle. Refer to
Figure6fortheaddress, acknowledgeanddatatransfer
sequence.
ISSUE SLAVE
ADDRESS AND R/W = 0
ISSUE STOP
ACK
NO
RETURNED?
YES
Acknowledge Polling
The disabling of the inputs can be used to take advan-
tage of the typical 5 ms write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation the X24C16 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the X24C16 is still busy with the
write operation no ACK will be returned. If the X24C16
has completed the write operation an ACK will be
returned and the host can then proceed with the next
read or write operation. Refer to Flow 1.
NEXT
NO
OPERATION
A WRITE?
YES
ISSUE BYTE
ADDRESS
ISSUE STOP
PROCEED
PROCEED
3840 FHD F11
Figure 6. Page Write
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS (n)
BUS ACTIVITY:
MASTER
DATA n
DATA n+1
DATA n+15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24C16
NOTE: In this example n = xxxx 000 (B); x = 1 or 0
3840 FHD F12
6
X24C16
READ OPERATIONS
bitword.Thereadoperationisterminatedbythemaster;
by not responding with an acknowledge and by issuing
a stop condition. Refer to Figure 7 for the sequence of
address, acknowledge and data transfer.
Read operations are initiated in the same manner as
writeoperationswiththeexceptionthattheR/Wbitofthe
slave address is set to a one. There are three basic read
operations: current address read, random read and
sequential read.
Random Read
Randomreadoperationsallowthemastertoaccessany
memory location in a random manner. Prior to issuing
the slave address with the R/W bit set to one, the master
must first perform a “dummy” write operation. The mas-
ter issues the start condition, and the slave address
followed by the word address it is to read. After the word
addressacknowledge,themasterimmediatelyreissues
thestartconditionandtheslaveaddresswiththeR/W bit
set to one. This will be followed by an acknowledge from
the X24C16 and then by the eight bit word. The read
operationisterminatedbythemaster;bynotresponding
with an acknowledge and by issuing a stop condition.
RefertoFigure8fortheaddress, acknowledgeanddata
transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
duringtheninthcycleorholdSDAHIGHduringtheninth
clock cycle and then issue a stop condition.
Current Address Read
Internally the X24C16 contains an address counter that
maintains the address of the last word accessed,
incremented by one. Therefore, if the last access (either
areadorwrite)wastoaddressn,thenextreadoperation
would access data from address n + 1. Upon receipt of
the slave address with the R/W bit set to one, the
X24C16 issues an acknowledge and transmits the eight
Figure 7. Current Address Read
S
T
A
R
T
S
SLAVE
ADDRESS
BUS ACTIVITY:
MASTER
T
O
P
DATA
SDA LINE
S
P
A
C
K
BUS ACTIVITY:
X24C16
3840 FHD F13
Figure 8. Random Read
S
T
A
R
T
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS n
SLAVE
ADDRESS
BUS ACTIVITY:
MASTER
DATA n
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24C16
3840 FHD F14
7
X24C16
Sequential Read
Thedataoutputissequential,withthedatafromaddress
n followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing
the entire memory contents to be serially read during
oneoperation. Attheendoftheaddressspace(address
2047), the counter “rolls over” to 0 and the X24C16
continues to output data for each acknowledge re-
ceived. Refer to Figure 9 for the address, acknowledge
and data transfer sequence.
Sequential reads can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other read modes, however, the
master now responds with an acknowledge, indicating it
requires additional data. The X24C16 continues to out-
put data for each acknowledge received. The read
operationisterminatedbythemaster;bynotresponding
with an acknowledge and by issuing a stop condition.
Figure 9. Sequential Read
S
SLAVE
ADDRESS
T
O
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
P
A
C
K
BUS ACTIVITY:
X24C16
DATA n
DATA n+1
DATA n+2
DATA n+x
3840 FHD F15
Figure 10. Typical System Configuration
V
CC
PULL-UP
RESISTORS
SDA
SCL
MASTER
SLAVE
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
TRANSMITTER/
RECEIVER
RECEIVER
3840 FHD F16
8
X24C16
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias.................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecificationis
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Respect to V
................................ –1.0V to +7.0V
SS
D.C. Output Current ............................................ 5 mA
Lead Temperature
(Soldering, 10 Seconds) ............................. 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
Industrial
Military
0°C
70°C
+85°C
+125°C
X24C16
4.5V to 5.5V
3.5V to 5.5V
3V to 5.5V
–40°C
–55°C
X24C16–3.5
X24C16–3
X24C16–2.7
3840 PGM T09
2.7V to 5.5V
3840 PGM T10
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
SCL = V x 0.1/V x 0.9 Levels
l
l
V
V
Supply Current (read)
Supply Current (write)
1
3
CC1
CC2
CC
CC
CC
mA
µA
µA
@ 100 KHz, SDA = Open, All Other
Inputs = GND or V – 0.3V
CC
CC
(1)
I
I
V
V
Standby Current
Standby Current
150
50
SCL = SDA = V – 0.3V, All Other
CC
SB1
SB2
CC
Inputs = GND or V , V = 5.5V
CC
CC
(1)
SCL = SDA = V – 0.3V, All Other
CC
CC
Inputs = GND or V , V = 3.3V +10%
CC
CC
I
I
Input Leakage Current
Output Leakage Current
Input Low Voltage
10
10
µA
µA
V
V
V
= GND to V
CC
LI
IN
= GND to V
CC
LO
OUT
(2)
V
V
V
–1.0
V
x 0.3
lL
CC
(2)
Input High Voltage
V
x 0.7 V + 0.5
V
IH
CC
CC
Output Low Voltage
0.4
V
I
OL
= 3 mA
OL
3840 PGM T03
CAPACITANCE T = 25°C, f = 1.0 MHz, V = 5V
A
CC
Symbol
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (A , A , A , SCL)
Max.
Units
Test Conditions
(3)
C
C
8
6
pF
pF
V
V
= 0V
= 0V
I/O
I/O
(3)
IN
0
1
2
IN
3840 PGM T05
Notes: (1) Must perform a stop command prior to measurement.
(2) V min. and V max. are for reference only and are not tested.
IL
IH
(3) This parameter is periodically sampled and not 100% tested.
9
X24C16
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUIT
5.0V
Input Pulse Levels
V
x 0.1 to V x 0.9
CC
CC
1533Ω
Input Rise and
Fall Times
10 ns
Output
Input and Output
Timing Levels
100pF
V
CC
x 0.5
3840 PGM T02
3840 FHD F18
A.C. CHARACTERISTICS LIMITS (Over the recommended operating conditions unless otherwise specified.)
Read & Write Cycle Limits
Symbol
Parameter
Min.
Max.
Units
f
SCL Clock Frequency
0
100
100
3.5
KHz
ns
SCL
T
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
I
t
t
0.3
4.7
µs
AA
BUF
Time the Bus Must Be Free Before a
New Transmission Can Start
µs
t
t
t
t
t
t
t
t
t
t
Start Condition Hold Time
Clock Low Period
4.0
4.7
4.0
4.7
0
µs
µs
µs
µs
µs
ns
µs
ns
µs
HD:STA
LOW
Clock High Period
HIGH
SU:STA
HD:DAT
SU:DAT
R
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
250
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
300
F
4.7
SU:STO
DH
300
ns
3840 PGM T06
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(4)
t
t
Power-up to Read Operation
Power-up to Write Operation
1
5
ms
ms
PUR
(4)
PUW
3840 PGM T07
Bus Timing
t
t
t
R
t
HIGH
LOW
F
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA IN
t
t
t
BUF
AA
DH
SDA OUT
3840 FHD F04
Notes: (4) t
and t
are the delays required from the time V is stable until the specified operation can be initiated. These parameters
PUW CC
PUR
are periodically sampled and not 100% tested.
10
X24C16
WRITE CYCLE LIMITS
(5)
Symbol
Parameter
Write Cycle Time
Min.
Typ.
Max.
Units
(6)
t
5
10
ms
WR
3840 PGM T08
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/programcycle.Duringthewritecycle,theX24C16
bus interface circuits are disabled, SDA is allowed to
remainhigh,andthedevicedoesnotrespondtoitsslave
address.
Write Cycle Timing
SCL
ACK
SDA
8th BIT
WORD n
t
WR
STOP
CONDITION
START
CONDITION
X24C16
ADDRESS
3840 FHD F05
Notes: (5) Typical values are for T = 25°C and nominal supply voltage (5V)
A
(6) t
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
WR
device requires to perform the internal write operation.
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
120
V
CC MAX
R
=
=1.8KΩ
MIN
I
100
80
OL MIN
May change
from Low to
High
Will change
from Low to
High
t
R
R
=
MAX
C
BUS
May change
from High to
Low
Will change
from High to
Low
MAX.
60
40
20
0
RESISTANCE
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
MIN.
RESISTANCE
Center Line
is High
Impedance
20 40 60 80
120
100
0
N/A
BUS CAPACITANCE (pF)
3840 FHD F17
11
X24C16
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
12
X24C16
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050" TYPICAL
X 45°
0.020 (0.50)
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS)
3926 FHD F22
13
X24C16
14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0° – 8°
0.050" Typical
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.41)
0.037 (0.937)
0.030" Typical
14 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F10
14
X24C16
ORDERING INFORMATION
X24C16
X
X
-X
V
CC
Range
Device
Blank = 4.5V to 5.5V
3.5 = 3.5V to 5.5V
3 = 3V to 5.5V
2.7 = 2.7V to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
P = 8-Lead Plastic DIP
S8 = 8-Lead SOIC
S14 = 14-Lead SOIC
P = 8-Lead Plastic DIP
S8 = 8-Lead SOIC
S14 = 14-Lead SOIC
X24C16
X
X
Part Mark Convention
Blank = 4.5V to 5.5V, 0°C to +70°C
I = 4.5V to 5.5V, –40°C to +85°C
B = 3.5V to 5.5V, 0°C to +70°C
C = 3.5V to 5.5V, –40°C to +85°C
D = 3.0V to 5.5V, 0°C to +70°C
E = 3.0V to 5.5V, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C
M = 4.5V to 5.5V, –55°C to +125°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967;
4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. Acriticalcomponentisanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocausethefailure
of the life support device or system, or to affect its satety or effectiveness.
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