X24C44ST2 [XICOR]
Non-Volatile SRAM, 16X16, 375ns, CMOS, PDSO8, PLASTIC, SOIC-8;
| 型号： | X24C44ST2 |
| 厂家： | 
XICOR INC. |
| 描述： | Non-Volatile SRAM, 16X16, 375ns, CMOS, PDSO8, PLASTIC, SOIC-8 静态存储器 光电二极管 |
| 文件： | 总15页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTES
A V A I L A B L E
AN3 • AN7 • AN8 • AN15 • AN16 • AN25 • AN29
• AN30 • AN35 • AN36 • AN39 • AN56 • AN69
256 Bit
X24C44
16 x 16 Bit
Serial Nonvolatile Static RAM
FEATURES
DESCRIPTION
• Advanced CMOS Version of Xicor’s X2444
• 16 x 16 Organization
The Xicor X24C44 is a serial 256 bit NOVRAM featuring
a static RAM configured 16 x 16, overlaid bit-by-bit with
a nonvolatile E PROM array. The X24C44 is fabricated
2
• Single 5 Volt Supply
• Ideal for use with Single Chip Microcomputers
withXicor’sAdvancedCMOSFloatingGatetechnology.
—Static Timing
TheXicorNOVRAMdesignallowsdatatobetransferred
between the two memory arrays by means of software
commands or external hardware inputs. A store opera-
—Minimum I/O Interface
—Serial Port Compatible (COPS™, 8051)
—Easily Interfaced to Microcontroller Ports
• Software and Hardware Control of Nonvolatile
Functions
• Auto Recall on Power-Up
• TTL and CMOS Compatible
• Low Power Dissipation
2
tion (RAM data to E PROM) is completed in 5ms or less
2
and a recall operation (E PROM data to RAM) is com-
pleted in 2µs or less.
XicorNOVRAMsaredesignedforunlimitedwriteopera-
tions to RAM, either from the host or recalls from
—Active Current: 10mA Maximum
—Standby Current: 50µA Maximum
• 8-Lead PDIP, Cerdip, and 8-Lead SOIC Packages
• High Reliability
2
E PROM and a minimum 1,000,000 store operations.
Inherent data retention is specified to be greater than
100 years.
—Store Cycles: 1,000,000
—Data Retention: 100 Years
FUNCTIONAL DIAGRAM
NONVOLATILE
2
E PROM
ORE
ST
STATIC
RAM
256-BIT
RECALL (6)
STORE (7)
CONTROL
LOGIC
RECALL
ROW
DECODE
CE (1)
INSTRUCTION
DI (3)
COLUMN
DECODE
DO (4)
REGISTER
SK (2)
INSTRUCTION
DECODE
4-BIT
COUNTER
3832 FHD F01
COPS is a trademark of National Semiconductor Corp.
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3832-1.5 2/24/99 T2/C1/D1 NS
Characteristics subject to change without notice
1
X24C44
PIN DESCRIPTIONS
Chip Enable (CE)
PIN CONFIGURATION
The Chip Enable input must be HIGH to enable all read/
write operations. CE must remain HIGH following a
Read or Write command until the data transfer is com-
plete. CE LOW places the X24C44 in the low power
standbymodeandresetstheinstructionregister.There-
fore,CEmustbebroughtLOWafterthecompletionofan
operation in order to reset the instruction register in
preparation for the next command.
PDIP/CERDIP/SOIC
CE
SK
DI
1
2
3
4
8
7
6
5
V
CC
STORE
X24C44
RECALL
DO
V
SS
3832 FHD F02.2
Serial Clock (SK)
The Serial Clock input is used to clock all data into and
out of the device.
Data In (DI)
PIN NAMES
Data In is the serial data input.
Symbol
CE
Description
Data Out (DO)
Chip Enable
Serial Clock
Serial Data In
Serial Data Out
Recall Input
Store Input
+5V
Data Out is the serial data output. It is in the high
impedance state except during data output cycles in
response to a READ instruction.
SK
DI
DO
STORE
RECALL
STORE
STORE LOWwillinitiateaninternaltransferofdatafrom
2
V
RAM to the E PROM array.
CC
V
Ground
SS
RECALL
3832 PGM T01
RECALL LOW will initiate an internal transfer of data
2
from E PROM to the RAM array.
2
X24C44
2
DEVICE OPERATION
operations to the E PROM. The WREN instruction sets
the latch and the WRDS instruction resets the latch,
disabling both RAM writes and E PROM stores, effec-
tively protecting the nonvolatile data from corruption. The
write enable latch is automatically reset on power-up.
The X24C44 contains an 8-bit instruction register. It is
accessed via the DI input, with data being clocked in on
therisingedgeofSK.CEmustbeHIGHduringtheentire
data transfer operation.
2
STO and STORE
Table 1. contains a list of the instructions and their
operation codes. The most significant bit (MSB) of all
instructions is a logic one (HIGH), bits 6 through 3 are
either RAM address bits (A) or don’t cares (X) and bits
2 through 0 are the operation codes. The X24C44
requirestheinstructiontobeshiftedinwiththeMSBfirst.
Either the software STO instruction or a LOW on the
STORE input will initiate a transfer of data from RAM to
2
E PROM. In order to safeguard against unwanted store
operations, the following conditions must be true:
• STO instruction issued or STORE input is LOW.
• The internal “write enable” latch must be set
(WREN instruction issued).
• The “previous recall” latch must be set (either a
software or hardware recall operation).
After CE is HIGH, the X24C44 will not begin to interpret
thedatastreamuntilalogic“1”hasbeenshiftedinonDI.
Therefore, CE may be brought HIGH with SK running
and DI LOW. DI must then go HIGH to indicate the start
condition of an instruction before the X24C44 will begin
any action.
Once the store cycle is initiated, all other device func-
tions are inhibited. Upon completion of the store cycle,
the write enable latch is reset. Refer to Figure 4 for a
state diagram description of enabling/disabling condi-
tions for store operations.
In addition, the SK clock is totally static. The user can
completelystoptheclockanddatashiftingwillbestopped.
Restarting the clock will resume shifting of data.
WRITE
RCL and RECALL
The WRITE instruction contains the 4-bit address of the
word to be written. The write instruction is immediately
followed by the 16-bit word to be written. CE must remain
HIGH during the entire operation. CE must go LOW
before the next rising edge of SK. If CE is brought LOW
prematurely(aftertheinstructionbutbefore16bitsofdata
are transferred), the instruction register will be reset and
the data that was shifted-in will be written to RAM.
Either a software RCL instruction or a LOW on the
RECALL input will initiate a transfer of E PROM data
2
into RAM. This software or hardware recall operation
sets an internal “previous recall” latch. This latch is reset
upon power-up and must be intentionally set by the user
toenableanywriteorstoreoperations. Althougharecall
operation is performed upon power-up, the previous
recall latch is not set by this operation.
If CE is kept HIGH for more than 24 SK clock cycles (8-bit
instructionplus16-bitdata),thedataalreadyshifted-inwill
be overwritten.
WRDS and WREN
InternallytheX24C44containsa“writeenable”latch. This
latch must be set for either writes to the RAM or store
Table 1. Instruction Set
Instruction
Format, I I I
Operation
2 1 0
WRDS (Figure 3)
STO (Figure 3)
Reserved
1XXXX000
1XXXX001
1XXXX010
1AAAA011
1XXXX100
1XXXX101
1AAAA11X
Reset Write Enable Latch (Disables Writes and Stores)
2
Store RAM Data in E PROM
N/A
WRITE (Figure 2)
WREN (Figure 3)
RCL (Figure 3)
READ (Figure 1)
Write Data into RAM Address AAAA
Set Write Enable Latch (Enables Writes and Stores)
2
Recall E PROM Data into RAM
Read Data from RAM Address AAAA
3832 PGM T13
X = Don't Care
A = Address
3
X24C44
READ
SYSTEM CONSIDERATIONS
The READ instruction contains the 4-bit address of the
Power-Up Recall
word to be accessed. Unlike the other six instructions, I
0
The X24C44 performs a power-up recall that transfers
oftheinstructionwordisa“don’tcare”.Thisprovidestwo
advantages. In a design that ties both DI and DO
together, the absence of an eighth bit in the instruction
allows the host time to convert an I/O line from an output
to an input. Secondly, it allows for valid data output
during the ninth SK clock cycle.
2
the E PROM contents to the RAM array. Although the
data may be read from the RAM array, this recall does
not set the “previous recall” latch. During this power-up
recall operation, all commands are ignored. Therefore,
the host should delay any operations with the X24C44 a
minimum of t
after V is stable.
PUR
CC
D0, the first bit output during a read operation, is trun-
cated. That is, it is internally clocked by the falling edge
of the eighth SK clock; whereas, all succeeding bits are
clocked by the rising edge of SK (refer to Read Cycle
Diagram).
Power-Down Data Protection
Because the X24C44 is a 5V only nonvolatile memory
device it may be susceptible to inadvertent stores to the
2
E PROM array during power-down cycles. Power-up
cycles are not a problem because the “previous recall”
latch and “write enable” latch are reset, preventing any
LOW POWER MODE
2
possible corruption of E PROM data.
When CE is LOW, non-critical internal devices are
powered-down, placing the device in the standby power
mode, thereby minimizing power consumption.
Software Power-Down Protection
If the STORE and RECALL pins are tied to V through
CC
SLEEP
a pull-up resistor and only software operations are
performed to initiate stores, there is little likelihood of an
inadvertent store. However, if these two lines are under
microprocessor control, positive action should be em-
ployed to negate the possibility of these control lines
bouncingandgeneratinganunwantedstore. Thesafest
method is to issue the WRDS command after a write
sequence and also following store operations. Note: an
internal store may take up to 5ms; therefore, the host
microprocessor should delay 5ms after initiating the
store prior to issuing the WRDS command.
Because the X24C44 is a low power CMOS device, the
SLEEP instruction implemented on the first generation
NMOS device has been deleted. For systems convert-
ing from the X2444 to the X24C44 the software need not
be changed; the instruction will be ignored.
WRITE PROTECTION
The X24C44 provides two software write protection
mechanisms to prevent inadvertent stores of unknown
data.
Hardware Power-Down Protection
Power-Up Condition
(whenthe“writeenable”latchand“previousrecall”latch
are not in the reset state):
Upon power-up the “write enable” latch is in the reset
state, disabling any store operation.
Holding either RECALL LOW, CE LOW or STORE
HIGH during power-down will prevent an inadvertent
store.
Unknown Data Store
The “previous recall” latch must be set after power-up.
It may be set only by performing a software or hardware
recall operation, which assures that data in all RAM
locations is valid.
4
X24C44
Figure 1. RAM Read
CE
SK
DI
1
1
2
3
4
5
6
7
8
9
10
11
12
22
23
24
A
A
A
A
1
1
X*
HIGH Z
DO
D
D
D
D
D
D
D
D
0
1
2
3
13
14
15
0
*Bit 8 of Read Instructions is Don’t Care
3832 FHD F07.1
Figure 2. RAM Write
CE
SK
DI
1
1
2
3
4
5
6
7
8
1
9
10
D
11
D
21
22
23
24
A
A
A
A
0
1
D
D
D
D
D
0
1
2
12
13
14
15
3832 FHD F08.1
Figure 3. Non-Data Operations
CE
SK
DI
1
2
3
4
5
6
7
8
1
X
X
X
X
I2
I1
I0
3832 FHD F09.1
5
X24C44
Figure 4. X24C44 State Diagram
POWER
ON
POWER-UP
RECALL
RAM READ
RAM
READ
ENABLED
RCL COMMAND
OR RECALL
RAM READ
RAM
READ
ENABLED
WREN
COMMAND
STO OR
WRDS CMD
OR STORE
RAM
READ &
WRITE
RAM READ
OR WRITE
STORE
ENABLED
3832 FHD F10.1
6
X24C44
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecificationis
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Respect to V ............................................ –1V to +7V
SS
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
Industrial
Military
0°C
+70°C
+85°C
+125°C
X24C44
5V ±10%
3832 PGM T03.1
–40°C
–55°C
3832 PGM T02.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
l
V
Supply Current
CC
10
mA
SK = 0.4V/2.4V Levels @ 1MHz,
CC
(TTL Inputs)
DO = Open, All Other Inputs = V
IH
I
I
V
Standby Current
1
mA
µA
DO = Open, CE = V ,
IL
SB1
SB2
CC
(TTL Inputs)
All Other Inputs = V
IH
V
Standby Current
50
DO = Open, CE = V
SS
CC
(CMOS Inputs)
All Other Inputs = V – 0.3V
CC
I
I
Input Load Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V
LO
OUT
SS
CC
(1)
V
V
V
V
–1
2
0.8
lL
(1)
V
+ 1
CC
V
IH
0.4
V
I = 4.2mA
OL
OL
OH
2.4
V
I = –2mA
OH
3832 PGM T04.3
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
100,000
1,000,000
100
Data Changes Per Bit
Store Cycles
Years
Store Cycles
Data Retention
3832 PGM T05
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Parameter
Max.
Units
Test Conditions
(2)
C
Output Capacitance
Input Capacitance
8
6
pF
pF
V
V
= 0V
OUT
OUT
(2)
C
IN
= 0V
IN
3832 PGM T06.1
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
(2) This parameter is periodically sampled and not 100% tested.
7
X24C44
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input Pulse Levels
0V to 3V
5V
Input Rise and
Fall Times
10ns
1.5V
919Ω
Input and Output
Timing Levels
OUTPUT
3832 PGM T07.1
497Ω
100pF
3832 FHD F11
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Read and Write Cycle Limits
Symbol
Parameter
SK Frequency
Min.
Max.
Units
(3)
F
1
MHz
ns
ns
ns
ns
ns
ns
µs
ns
ns
SK
SKH
SKL
DS
t
t
t
t
t
t
t
t
t
t
SK Positive Pulse Width
SK Negative Pulse Width
Data Setup Time
400
400
400
80
Data Hold Time
DH
SK to Data Bit 0 Valid
SK to Data Valid
375
375
1
PD1
PD
Chip Enable to Output High Z
Chip Enable Setup
Chip Enable Hold
Z
800
350
800
CES
CEH
CDS
Chip Deselect
ns
3832 PGM T08.1
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(4)
t
t
Power-up to Read Operation
200
5
µs
PUR
(4)
Power-up to Write or Store Operation
ms
PUW
3832 PGM T09
Notes: (3) SK rise and fall times must be less than 50ns.
(4) t and t are the delays required from the time V is stable until the specified operation can be initiated. These parameters
PUR
PUW
CC
are periodically sampled and not 100% tested.
8
X24C44
Write Cycle
1/F
SK
SK CYCLE #
t
t
SKH
SKL
SK
CE
DI
x
1
2
n
t
t
CDS
t
CEH
CES
t
t
DH
DS
3832 FHD F03
Read Cycle
SK CYCLE #
SK
6
7
8
9
10
n
V
IH
I2
CE
t
PD
I1
DI
DON’T CARE
t
PD1
t
Z
HIGH Z
HIGH Z
DO
D0
D1
Dn
3832 FHD F04
9
X24C44
NONVOLATILE OPERATIONS
Previous
Recall Latch
State
Software
Instruction
Write Enable
Latch State
Operation
STORE
RECALL
(5)
Hardware Recall
Software Recall
Hardware Store
Software Store
1
1
0
1
0
1
1
1
NOP
X
X
X
RCL
X
(5)
NOP
SET
SET
SET
STO
SET
3832 PGM T10
ARRAY RECALL LIMITS
Symbol
Parameter
Recall Cycle Time
Min.
Max.
Units
t
t
t
2
µs
ns
RCC
RCP
RCZ
(6)
Recall Pulse Width
500
Recall to Output in High Z
500
ns
3832 PGM T11
Recall Timing
t
RCC
t
RCP
RECALL
DO
t
RCZ
HIGH Z
3832 FHD F05
Notes: (5) NOP designates when the X24C44 is not currently executing an instruction.
(6) Recall rise time must be <10µs.
10
X24C44
STORE CYCLE LIMITS
Symbol
(7)
Parameter
Store Time
Min.
Typ.
Max.
Units
t
t
t
2
5
ms
ns
µs
V
ST
STP
Z
Store Pulse Width
CE to Output in High Z
Store Inhibit
200
1
V
3
CC
3832 PGM T12
Store Timing
CE
STORE
DO
t
ST
t
STP
t
Z
HIGH Z
3832 FHD F06
Note: (7) Typical values are for T = 25°C and nominal supply voltage.
A
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
11
X24C44
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.092 (2.34)
DIA. NOM.
0.255 (6.47)
0.245 (6.22)
PIN 1 INDEX
PIN 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.140 (3.56)
0.130 (3.30)
SEATING
PLANE
0.020 (0.51)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.062 (1.57)
0.058 (1.47)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
15°
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F01
12
X24C44
PACKAGING INFORMATION
8-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
0.405 (10.29)
––
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN.
0.300 (7.62)
0.055 (1.40) MAX.
REF.
0.200 (5.08)
SEATING
PLANE
0.140 (3.56)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
0.125 (3.18)
0.150 (3.81) MIN.
0.065 (1.65)
0.038 (0.97)
TYP. 0.060 (1.52)
0.110 (2.79)
0.090 (2.29)
0.023 (0.58)
0.014 (0.36)
TYP. 0.100 (2.54)
TYP. 0.017 (0.43)
0.320 (8.13)
0.290 (7.37)
TYP. 0.311 (7.90)
0°
0.015 (0.38)
0.008 (0.20)
15°
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F05
13
X24C44
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050" TYPICAL
X 45°
0.020 (0.50)
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
14
X24C44
ORDERING INFORMATION
X24C44
P
T
-V
V
Limits
Device
CC
Blank = 5V ±10%
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 8-Lead Plastic DIP
D = 8-Lead Ceramic DIP
S = 8-Lead SOIC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967;
4,883,976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. Acriticalcomponentisanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocausethefailure
of the life support device or system, or to affect its satety or effectiveness.
15
相关型号：
©2020 ICPDF网 联系我们和版权申明