X25256V20I-2.5 [XICOR]
EEPROM, 32KX8, Serial, CMOS, PDSO20, PLASTIC, TSSOP-20;
| 型号： | X25256V20I-2.5 |
| 厂家： | 
XICOR INC. |
| 描述： | EEPROM, 32KX8, Serial, CMOS, PDSO20, PLASTIC, TSSOP-20 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总17页 (文件大小：492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
256K
32K x 8 Bit
X25256
5MHz SPI Serial E2PROM with Block Lock™ Protection
FEATURES
• Packages
—8-lead XBGA
—8-lead SOIC (JEDEC, EIAJ)
—20-lead TSSOP
• 5MHz Clock Rate
• Low Power CMOS
—<1µA standby current
—<5mA active current
• 2.5V To 5.5V Power Supply
• SPI Modes (0,0 & 1,1)
DESCRIPTION
The X25256 is a CMOS 256K-bit serial E2PROM, inter-
nally organized as 32K x 8. The X25256 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
• 32K X 8 Bits
—64 byte page mode
• Block Lock™ Protection
—Protect first page, first 2 pages, first 4 pages,
first 8 pages, 1/4, 1/2 or all of E2PROM array
• Programmable Hardware Write Protection
—In-circuit programmable ROM mode
• Built-In Inadvertent Write Protection
—Power-up/down protection circuitry
—Write enable latch
The X25256 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25256 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire
input to the X25256 disabling all write attempts to the
status register, thus providing a mechanism for limiting
end user capability of altering first page, first 2 pages, 4
pages, 8 pages, 0, 1/4, 1/2 or all of the memory.
—Write protect pin
• Self-Timed Write Cycle
—5ms write cycle time (typical)
• High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100Years
—ESD protection: 2000V on all pins
FUNCTIONAL DIAGRAM
Write
Status
Protect
Register
Logic
32K Byte
Array
128
128 X 512
SO
SI
SCK
CS
HOLD
Command
Decode
128
X-Decode
Protect
Logic
And
128 X 512
Control
Logic
248
4
248 X 512
4 X 512
256 X 512
Write
Control
And
Timing
Logic
2
1
1
2 X 512
1 X 512
1 X 512
WP
64
8
Y Decode
DataRegister
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
Characteristics subject to change without notice. 1 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
The X25256 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
PIN CONFIGURATION
8-Lead XBGA
Serial Input (SI)
8
7
6
5
1
2
3
4
S0
HOLD
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
V
CC
CS
V
SI
SS
SCK
WP
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
8-Lead SOIC
1
2
8
CS
SO
V
CC
7
6
5
HOLD
SCK
SI
X25256
WP
3
4
V
SS
Chip Select (CS)
When CS is HIGH, the X25256 is deselected and the
SO output pin is at high impedance and unless an
internal write operation is underway, the X25256 will be
in the standby power mode. CS LOW enables the
X25256, placing it in the active power mode. It should
be noted that after power-up, a HIGH to LOW transition
on CS is required prior to the start of any operation.
20-Lead TSSOP
1
CS
V
20
CC
NC
NC
SO
NC
NC
NC
NC
2
19
18
17
16
15
HOLD
NC
3
4
NC
5
6
7
X25256
NC
SCK
NC
NC
SI
14
Write Protect (WP)
8
13
12
11
WP
NC
When WP is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25256 status register are dis-
abled, but the part otherwise functions normally. When
WP is held HIGH, all functions, including nonvolatile
writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25256 status reg-
ister. If the internal write cycle has already been initi-
ated, WP going LOW will have no affect on a write.
9
10
V
SS
PIN NAMES
Symbol
CS
Description
Chip Select Input
Serial Output
Serial Input
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25256 in a system with WP pin grounded and still
be able to write to the status register. The WP pin func-
tions will be enabled when the WPEN bit is set “1”.
SO
SI
SCK
WP
Serial Clock Input
Write Protect Input
Ground
V
V
SS
CC
Supply Voltage
Hold Input
HOLD
NC
No Connect
Characteristics subject to change without notice. 2 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
Hold (HOLD)
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume com-
munication, HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
HOLD is used in conjunction with the CS pin to pause
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
WRDI
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
RDSR
WRSR
READ
WRITE
Write Status Register
Read Data from Memory Array beginning at selected address
Write Data to Memory Array beginning at Selected Address (1 to 64 Bytes)
Notes: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
PRINCIPLES OF OPERATION
Status Register
The X25256 is a 32K x 8 E2PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
The X25256 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK. CS must be LOW and the HOLD and
WP inputs must be HIGH during the entire operation.
7
6
5
4
3
2
1
0
WPEN
X
X
BL2 BL1 BL0 WEL WIP
WPEN, BL0 and BL1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
other operations.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
The Write-In-Process (WIP) bit indicates whether the
X25256 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. This bit is set and reset by hardware, it
cannot be controlled by the WRSR instruction. When
reading the Status Register while an internal nonvola-
tile write is in progress, all bits output will be ‘1’. This
allows the programmer to use the WIP bit to determine
an early end of write condition. It also allows the pro-
grammer to check for “FF” or “not FF” to determine end
of write. The programmer can also use the first one or
two bits received from the Status Register (if they were
known to be zero) to determine end of write. Each of
these techniques can simplify or speed the end of non-
volatile write detection.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25256 into a “PAUSE” condition. After releasing
HOLD, the X25256 will resume operation from the
point when HOLD was first asserted.
Write Enable Latch
The X25256 contains a “write enable” latch. This latch
must be SET before a write operation will be com-
pleted internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status reg-
ister write cycle.
Characteristics subject to change without notice. 3 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
The Write Enable Latch (WEL) bit indicates the status
of the “write enable” latch. When set to a “1”, the latch
is set, when set to a “0”, the latch is reset. This bit is
controlled by hardware and cannot be written by the
WRSR instruction.
The Block Lock (BL0, BL1, and BL2) bits are nonvola-
tile and allow the user to select one of eight levels of
protection.That is, the user may read the segments but
will be unable to alter (write) data within the selected
segments. The partitioning is controlled as illustrated in
the following table.
Status Register Bits
BL2
0
BL1
0
BL0
0
Array Addresses Protected
Array Lock
None
None
0
0
1
$6000–$7FFF (8K bytes)
$4000–$7FFF (16K bytes)
$0000–$7FFF (32K bytes)
$000–$03F (64 bytes)
$000–$07F (128 bytes)
$000–$0FF (256 bytes)
$000–$1FF (512 bytes)
Upper 1/4 (Q4)
Upper 1/2 (Q3, Q4)
Full Array (All)
First Page (P1)
First 2 Pages (P2)
First 4 Pages (P4)
First 8Pages (P8)
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Figure 1. Block Lock Configurations
bit itself, as well as the block-protected sections in the
memory array. Only the sections of the memory array
that are not block-protected can be written.
BL2-BL0
000
001
010
011
100
101
110
111
In Circuit Programmable ROM Mode
Note that since the WPEN bit is write protected, it can-
not be changed back to a LOW state; so write protec-
tion is enabled as long as the WP pin is held LOW.
Thus an In Circuit Programmable ROM function can be
implemented by hardwiring the WP pin to Vss, writing
to and Block Locking the desired portion of the array to
be ROM, and then programming the WPEN bit HIGH.
The table above defines the program protect status for
each combination of WPEN and WP.
1/2 Array
3/4 Array
All Array
Clock and Data Timing
The Write-Protect-Enable (WPEN) bit is available for
the X25256 as a nonvolatile enable bit for the WP pin.
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Programmable Hardware Write Protection
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register con-
trol the Programmable Hardware Write Protect feature.
Hardware Write Protection is enabled when WP pin is
LOW, and the WPEN bit is “1”. Hardware Write Protec-
tion is disabled when either the WP pin is HIGH or the
WPEN bit is “0”. When the chip is hardware write pro-
tected, nonvolatile writes are disabled to the Status
Register, including the Block Lock bits and the WPEN
Read Sequence
When reading from the E2PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25256, followed by the
16-bit address of which the last 15 are used. After the
READ opcode and address are sent, the data stored in
the memory at the selected address is shifted out on the
SO line. The data stored in memory at the next address
Characteristics subject to change without notice. 4 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
can be read sequentially by continuing to provide clock
pulses. The address is automatically incremented to the
next higher address after each byte of data is shifted out.
When the highest address is reached ($7FFF) the
address counter rolls over to address $0000 allowing the
read cycle to be continued indefinitely.The read operation
is terminated by taking CS HIGH. Refer to the read
E2PROM array operation sequence illustrated in Figure 2.
To read the status register the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the status register are shifted out on the SO line.
Figure 3 illustrates the read status register sequence.
Memory Array Not
Block Protected
Memory Array
Block Lock
WP
HIGH
LOW
LOW
WPEN
Block Protected
Bits
WPEN Bit
Writable
Protection
Software
X
0
1
Writable
Writable
Writable
Blocked
Writable
Blocked
Writable
Writable
Software
Blocked
Writes Blocked
Writes Blocked
Hardware
Write Sequence
While the write is in progress following a status register
or E2PROM write sequence, the status register may be
read to check the WIP bit. During this time the WIP bit
will be HIGH.
Prior to any attempt to write data into the X25256, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 4). CS is first taken
LOW, then the WREN instruction is clocked into the
X25256. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user con-
tinues the write operation without taking CS HIGH after
issuing the WREN instruction, the write operation will
be ignored.
Hold Operation
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW and SCK must
also be LOW when HOLD is released.
To write data to the E2PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written.This is minimally a thirty-
two clock operation. CS must go LOW and remain LOW
for the duration of the operation. The host may continue
to write up to 64 bytes of data to the X25256. The only
restriction is the 64 bytes must reside on the same
page. If the address counter reaches the end of the
page and the clock continues, the counter will “roll over”
to the first address of the page and overwrite any data
that may have been written.
The HOLD input may be tied HIGH either directly to
VCC or tied to VCC through a resistor.
Operational Notes
The X25256 powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
For the write operation (byte or page write) to be com-
pleted, CS can only be brought HIGH after bit 0 of data
byte N is clocked in. If it is brought HIGH at any other
time the write operation will not be completed. Refer to
Figures 5 and 6 below for a detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
– The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The “write enable” latch is reset upon power-up.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 5, and
6 are “don’t care”. Figure 7 illustrates this sequence.
– A WREN instruction must be issued to set the “write
enable” latch.
– CS must come HIGH at the proper clock count in
order to start a write cycle.
Characteristics subject to change without notice. 5 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
Figure 2. Read E2PROM Array Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
Instruction
16 Bit Address
15 14 13 2
3
1
0
Data Out
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
Figure 3. Read Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
SI
Instruction
Data Out
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
Figure 4. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
High Impedance
SO
Characteristics subject to change without notice. 6 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
Figure 5. Byte Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
Instruction
16 Bit Address
15 14 13
Data Byte
3
2
1
0
7
6
5
4
3
2
1
0
High Impedance
SO
Figure 6. Page Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
Instruction
16 Bit Address
13
Data Byte 1
7
6
5
4
3
2
1
0
3
2
1
0
15
14
CS
SCK
SI
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Characteristics subject to change without notice. 7 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
Figure 7. Write Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15
SCK
SI
Instruction
Data Byte
4
3
2
5
1
0
High Impedance
SO
Characteristics subject to change without notice. 8 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ........................–65 to +135°C
Storage temperature .............................–65 to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; and the functional operation
of the device (at these or any other conditions above
those indicated in the operational sections of this speci-
fication) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
respect to V .........................................–1V to +7V
SS
D.C. output current
5mA (soldering, 10 seconds) ......................... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
Limit
X25256-2.5
2.5V to 5.5V
–40°C
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
SCK = V x 0.1/V x 0.9 @ 5MHz,
CC
CC
I
V
V
Supply Current (Active)
5
mA
CC
CC
SO = Open, CS = V
SS
CS = V , V = V or V – 0.3V,
CC
IN
SS
CC
I
Supply Current (Standby)
1
µA
SB
CC
T = 25°C
A
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
V
V
= V to V
SS
CC
LI
IN
I
= V to V
SS
CC
LO
OUT
(1)
V
–1
V
x 0.3
IL
CC
(1)
V
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
x 0.7
CC
V
+ 0.5
V
IH
CC
V
0.4
V
I
I
I
I
= 3mA, V = 5V
CC
OL1
OH1
OL
OH
OL
OH
V
V
–0.8
–0.4
V
= –1.0mA, V = 5V
CC
CC
V
0.4
V
= 1.0mA, V = 3V
CC
OL2
V
V
V
= –0.4mA, V = 3V
CC
OH2
CC
POWER-UP TIMING
Symbol
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min.
Max.
1
Unit
ms
(3)
T
PUR
(3)
T
5
ms
PUW
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Parameter
Output Capacitance (SO)
Input Capacitance (SCK, SI, CS, WP, HOLD)
Max.
8
Unit
pF
Test Conditions
(3)
C
V
= 0V
I/O
I/O
(3)
C
6
pF
V
IN
= 0V
IN
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
(2) This parameter is periodically sampled and not 100% tested.
(3) t and t are the delays required from the time V
is stable until the specified operation can be initiated. These parameters
CC
PUR
PUW
are periodically sampled and not 100% tested.
Characteristics subject to change without notice. 9 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
5V
Input rise and fall times
Input and output timing levels
10ns
2.06KΩ
V
X 0.5
CC
SO
3.03KΩ
30pF
A.C. OPERATING CHARACTERISTICS
Data Input Timing
V
= 2.5V–5.5V
Max.
CC
Symbol
Parameter
Min.
0
Unit
MHz
ns
f
Clock Frequency
Cycle Time
5.0
SCK
CYC
t
200
100
100
80
t
CS Lead Time
ns
LEAD
t
CS Lag Time
ns
LAG
t
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Data In Rise Time
Data In Fall Time
HOLD Setup Time
HOLD Hold Time
CS Deselect Time
Write Cycle Time
ns
WH
t
80
ns
WL
t
20
ns
SU
t
20
ns
H
(4)
t
t
2
2
µs
RI
(4)
µs
FI
t
40
40
ns
HD
CD
t
ns
t
100
ns
CS
(5)
t
10
ms
WC
Data Output Timing
V
= 2.5V–5.5V
CC
Symbol
Parameter
Min.
Max.
5.0
Unit
MHz
ns
f
Clock Frequency
0
SCK
t
Output Disable Time
100
80
DIS
t
Output Valid from Clock LOW
Output Hold Time
ns
V
t
0
ns
HO
(4)
t
t
Output Rise Time
50
50
ns
RO
(4)
Output Fall Time
ns
FO
(4)
t
HOLD HIGH to Output in Low Z
HOLD LOW to Output in High Z
50
50
ns
LZ
(4)
t
ns
HZ
Notes: (4) This parameter is periodically sampled and not 100% tested.
(5) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
WC
write cycle
Characteristics subject to change without notice. 10 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
Serial Output Timing
CS
t
t
t
LAG
CYC
WH
SCK
t
t
V
t
t
DIS
WL
HO
SO
SI
MSB Out
MSB–1 Out
LSB Out
ADDR
LSB IN
Serial Input Timing
t
CS
CS
t
t
LEAD
LAG
SCK
t
t
t
t
FI
SU
H
RI
SI
MSB IN
LSB IN
High Impedance
SO
Characteristics subject to change without notice. 11 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
Hold Timing
CS
t
t
t
CD
HD
CD
t
HD
SCK
SO
t
t
LZ
HZ
SI
HOLD
Characteristics subject to change without notice. 12 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
PACKAGE INFORMATION
8-Lead Plastic, EIAJ SOIC, Package Code A8
0.020 (.508)
0.012 (.305)
.330 (8.38)
.300 (7.62)
.213 (5.41)
.205 (5.21)
Pin 1 ID
.050 (1.27) BSC
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
.013 (.330)
.004 (.102)
.010 (.254)
.007 (.178)
0°–8° Ref.
.035 (.889)
.020 (.508)
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 13 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
PACKAGING INFORMATION
8-Lead Plastic, SOIC, Package Code S8
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" Typical
X 45°
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 14 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
PACKAGING INFORMATION
20-Lead Plastic, TSSOP, Package Code V20
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 15 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
PACKAGING INFORMATION
8-Lead XBGA
Top Mark
Complete Part Number
X25256B-2.5
X25256BI-2.5
XAAD
XACR
8-Lead XBGA: Top View
1
2
3
4
S0
8
7
6
5
HOLD
V
CS
CC
SI
V
SS
WP
SCK
X25256: Bottom View
A1
HOLD
S0
8-Lead XBGA
B Package
PIN 1
V
CC
CS
Dwg Symbol
Min.
Max.
0.470
0.293
0.388
2.000
3.830
C
A
A1
C
D
E
0.445
0.253
0.360
1.940
3.770
E
E
V
SI
SS
e
SCK
WP
F
e
1.0 nominal
F
1.2 nominal
D
D
A1
A
C
NOTE: ALL DIMENSION IN MM
ALL DIMENSIONS ARETYPICAL VALUES
Characteristics subject to change without notice. 16 of 17
REV 1.02 11/28/00
www.xicor.com
X25256 – Preliminary Information
Ordering Information
T
X25256
P
-V
Device
V
Limits
CC
2.5 = 2.5V to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
A8 = 8-Lead SOIC (EIAJ)
S8 = 8-Lead SOIC (JEDEC)
V20 = 20-Lead TSSOP
B = 8-Lead XBGA
Park Mark Convention
8-Lead SOIC
8-Lead XBGA
Top Mark
XAAK
XAAL
Complete Part Number
X25256B-2.5
Blank = 8-Lead SOIC (JEDEC)
A8 = 8-Lead SOIC (EIAJ)
X5256 X
XX
X25256BI-2.5
J = 2.5 to 5.5V, 0 to +70°C
K = 2.5 to 5.5V, -40 to +85°C
20-Lead TSSOP
X25256 X
J = 2.5 to 5.5V, 0 to +70°C
K = 2.5 to 5.5V, -40 to +85°C
LIMITED WARRANTY
©Xicor, Inc. 2001 Patents Pending
©Xicor, Inc. 2000 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS ANDTRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 17 of 17
REV 1.02 11/28/00
www.xicor.com
相关型号：
©2020 ICPDF网 联系我们和版权申明