X25640 [XICOR]
Advanced SPI Serial E2PROM With Block LockTM Protection; 先进的SPI串行E2PROM带座LockTM保护
| 型号： | X25640 |
| 厂家： | 
XICOR INC. |
| 描述： | Advanced SPI Serial E2PROM With Block LockTM Protection |
| 文件： | 总14页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTES
A V A I L A B L E
AN19 • AN38 • AN41 • AN61
64K
X25640
8K x 8 Bit
Advanced SPI Serial E2PROM With Block LockTM Protection
FEATURES
DESCRIPTION
The X25640 is a CMOS 65,536-bit serial E2PROM,
internally organized as 8K x 8. The X25640 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signalsareaclockinput(SCK)plusseparatedatain(SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.
• 1MHz Clock Rate
• Low Power CMOS
—200µA Standby Current
—5mA Active Current
• 5 Volt Power Supply
• SPI Modes (0,0 & 1,1)
• 8K X 8 Bits
—32 Byte Page Mode
• Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Enable Latch
The X25640 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25640 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts.TheWPinputcanbeusedasahardwireinput
to the X25640 disabling all write attempts to the status
register, thus providing a mechanism for limiting end
usercapabilityofaltering0, 1/4, 1/2orallofthememory.
—Write Protect Pin
• Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• High Reliability
The X25640 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
• 8-Lead PDlP Package
• 14-Lead SOIC Package
FUNCTIONAL DIAGRAM
WRITE
STATUS
PROTECT
REGISTER
LOGIC
X DECODE
LOGIC
8K BYTE
ARRAY
64
64
64 X 256
64 X 256
SO
COMMAND
DECODE
AND
CONTROL
LOGIC
SI
SCK
CS
HOLD
128
128 X 256
WRITE
CONTROL
AND
TIMING
LOGIC
WP
32
8
Y DECODE
DATA REGISTER
3089 ILL F01
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3089-1.8 6/17/96 T4/C4/D1 NS
Characteristics subject to change without notice
1
X25640
PIN DESCRIPTIONS
Serial Output (SO)
SCKisLOW.Toresumecommunication,HOLDisbrought
HIGH, again while SCK is LOW. If the pause feature is not
used, HOLD should be held HIGH at all times.
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
PIN CONFIGURATION
Serial Input (SI)
8-LEAD DIP
CS
SO
WP
1
2
3
4
8
7
6
5
V
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of the
serial clock.
CC
HOLD
SCK
SI
X25640
V
SS
Serial Clock (SCK)
14-LEAD SOIC
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
NC
NC
CS
SO
WP
1
14
NC
NC
2
3
4
5
6
7
13
12
V
CC
X25640 11
HOLD
SCK
SI
10
9
Chip Select (CS)
V
SS
NC
WhenCSisHIGH, theX25640isdeselectedandtheSO
output pin is at high impedance and unless an internal
write operation is underway, the X25640 will be in the
standby power mode. CS LOW enables the X25640,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
8
NC
3089 ILL F02.3
PIN NAMES
Symbol
CS
Description
Chip Select Input
Serial Output
Serial Input
Write Protect (WP)
SO
When WP is LOW and the nonvolatile bit WPEN is high,
nonvolatile writes to the X25640 status register are
disabled, but the part otherwise functions normally.
WhenWPisheldHIGH, allfunctions, includingnonvola-
tile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25640 status
register. If the internal write cycle has already been
initiated, WP going LOW will have no affect on a write.
SI
SCK
WP
VSS
Serial Clock Input
Write Protect Input
Ground
VCC
HOLD
NC
Supply Voltage
Hold Input
No Connect
The WP pin function is blocked when the WPEN bit in
the status register is LOW. This allows the user to install
the X25640 in a system with WP pin grounded and still
be able to write to the status register. The WP pin
functions will be enabled when the WPEN bit is set “1”.
3089 PGM T01
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial com-
munication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while
2
X25640
PRINCIPLES OF OPERATION
Status Register
The X25640 is a 8K x 8 E2PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
The X25640 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
therisingSCK. CSmustbeLOWandtheHOLDandWP
inputs must be HIGH during the entire operation.
7
6
5
4
3
2
1
0
WPEN X
X
X
BP1
BP0 WEL WIP
3089 PGM T02
WPEN, BP0 and BP1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
other operations.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are trans-
ferred MSB first.
The Write-In-Process (WIP) bit indicates whether the
X25640 is busy with a write operation. When set to a “1”,
a write is in progress, when set to a “0”, no write is in
progress. During a write, all other bits are set to “1”.
DatainputissampledonthefirstrisingedgeofSCKafter
CS goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations. If the clock line is
shared with other peripheral devices on the SPI bus, the
usercanasserttheHOLDinputtoplacetheX25640into
a“PAUSE”condition.AfterreleasingHOLD,theX25640
will resume operation from the point when HOLD was
first asserted.
The Write Enable Latch (WEL) bit indicates the status of
the“writeenable”latch.Whensettoa“1”,thelatchisset,
when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protec-
tion. The X25640 is divided into four 16384-bit seg-
ments. One, two, or all four of the segments may be
protected. That is, the user may read the segments but
will be unable to alter (write) data within the selected
segments. The partitioning is controlled as illustrated
below.
Write Enable Latch
The X25640 contains a “write enable” latch. This latch
must be SET before a write operation will be completed
internally. The WREN instruction will set the latch and
the WRDI instruction will reset the latch. This latch is
automatically reset upon a power-up condition and after
the completion of a byte, page, or status register write
cycle.
Status Register Bits
Array Addresses
Protected
BP1
BP0
0
0
1
1
0
1
0
1
None
$1800–$1FFF
$1000–$1FFF
$0000–$1FFF
3834 PGM T03
Table 1. Instruction Set
Instruction Name
WREN
Instruction Format*
0000 0110
Operation
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
WRDI
0000 0100
RDSR
0000 0101
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory Array beginning at selected address
Write Data to Memory Array beginning at Selected Address
(1 to 32 Bytes)
WRITE
0000 0010
3089 PGM T04
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3
X25640
Write-Protect Enable
To read the status register the CS line is first pulled LOW
to select the device followed by the 8-bit RDSR instruc-
tion. After the RDSR opcode is sent, the contents of the
status register are shifted out on the SO line. Figure 2
illustrates the read status register sequence.
The Write-Protect-Enable (WPEN) is available for the
X25640 as a nonvolatile enable bit for the WP pin.
Protected Unprotected Status
WPEN WP WEL Blocks
Blocks
Protected Protected Protected
Protected Writable Writable
Protected Protected Protected
Protected Writable Protected
Protected Protected Protected
Register
Write Sequence
0
0
1
1
X
X
X
0
1
0
1
0
1
Prior to any attempt to write data into the X25640, the
“write enable” latch must first be set by issuing the
WRENinstruction(SeeFigure3). CS isfirsttakenLOW,
then the WREN instruction is clocked into the X25640.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the write
operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.
X
LOW
LOW
HIGH
HIGH
Protected
Writable
Writable
3089 PGM T03
The Write Protect (WP) pin and the nonvolatile Write
ProtectEnable(WPEN)bitintheStatusRegistercontrol
theprogrammablehardwarewriteprotectfeature.Hard-
ware write protection is enabled when WP pin is LOW,
and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is HIGH or the WPEN
bit is “0”. When the chip is hardware write protected,
nonvolatile writes are disabled to the Status Register,
including the Block Protect bits and the WPEN bit itself,
as well as the block-protected sections in the memory
array. Onlythesectionsofthememoryarraythatarenot
block-protected can be written.
To write data to the E2PROM memory array, the user
issuestheWRITEinstruction, followedbytheaddressand
then the data to be written. This is minimally a thirty-two
clockoperation.CSmustgoLOWandremainLOWforthe
durationoftheoperation.Thehostmaycontinuetowriteup
to32bytesofdatatotheX25640. Theonlyrestrictionisthe
32 bytes must reside on the same page. If the address
counter reaches the end of the page and the clock contin-
ues, the counter will “roll over” to the first address of the
page and overwrite any data that may have been written.
For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
databyteNisclockedin.IfitisbroughtHIGHatanyother
time the write operation will not be completed. Refer to
Figures 4 and 5 below for a detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
Note: Since the WPEN bit is write protected, it cannot
be changed back to a “0”, as long as the WP
pin is held LOW.
Clock and Data Timing
Data input on the SI line is latched on the rising edge of
SCK. Data is output on the SO line by the falling edge of
SCK.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5 and
6 must be “0”. Figure 6 illustrates this sequence.
Read Sequence
When reading from the E2PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instructionistransmittedtotheX25640, followedbythe
16-bit address of which the last 13 are used. After the
READ opcode and address are sent, the data stored in
thememoryattheselectedaddressisshiftedoutonthe
SO line. The data stored in memory at the next address
can be read sequentially by continuing to provide clock
pulses. The address is automatically incremented to
the next higher address after each byte of data is
shifted out. When the highest address is reached
($1FFF) the address counter rolls over to address
$0000 allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by taking CS
HIGH. Refer to the read E2PROM array operation
sequence illustrated in Figure 1.
While the write is in progress following a status register
or E2PROM write sequence, the status register may be
readtochecktheWIPbit.DuringthistimetheWIPbitwill
be HIGH.
Hold Operation
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
canbepulledLOWtosuspendthetransferuntilitcanbe
resumed. The only restriction is the SCK input must be
LOWwhenHOLDisfirstpulledLOWandSCKmustalso
be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to VCC
or tied to VCC through a resistor.
4
X25640
Operational Notes
Data Protection
The X25640 powers-up in the following state:
• The device is in the low power standby state.
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
• A WREN instruction must be issued to set the “write
enable” latch.
• SO pin is high impedance.
• CS must come HIGH at the proper clock count in
order to start a write cycle.
• The “write enable” latch is reset.
Figure 1. Read E2PROM Array Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
INSTRUCTION
16 BIT ADDRESS
15 14 13
3
2
1
0
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
3089 ILL F03.1
Figure 2. Read Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
3089 ILL F09.1
5
X25640
Figure 3. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
HIGH IMPEDANCE
SO
3089 ILL F05
Figure 4. Byte Write Operation Sequence
CS
20 21 22 23 24 25 26 27 28 29 30 31
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
INSTRUCTION
16 BIT ADDRESS
15 14 13
DATA BYTE
3
2
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
3089 ILL F04.1
6
X25640
Figure 5. Page Write Operation Sequence
CS
20 21 22 23 24 25 26 27 28 29 30 31
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
INSTRUCTION
16 BIT ADDRESS
15 14 13
DATA BYTE 1
3
2
1
0
7
6
5
4
3
2
1
0
CS
SCK
SI
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2
DATA BYTE 3
DATA BYTE N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
3089 ILL F07
Figure 6. Write Status Register Operation Sequence
CS
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
SCK
SI
INSTRUCTION
DATA BYTE
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
3089 ILL F08.1
7
X25640
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
Voltage on any Pin with Respect to V ......... –1V to +7V
SS
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Limits
Temp
Min.
0°C
Max.
+70°C
+85°C
X25640
5V ±10%
Commercial
Industrial
Military
3089 PGM T07.1
–40°C
–55°C
+125°C
3089 PGM T06.1
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
SCK = V x 0.1/V x 0.9 @ 1MHz,
I
V
V
Supply Current (Active)
5
mA
CC
CC
CC
CC
SO = Open, CS = V
SS
I
*
SB
Supply Current (Standby)
200
µA
CS = V , V = V or V
– 0.3V
CC
CC
CC
IN
SS
V
= 5.5V
CC
V
Output High Voltage
Input Leakage Current
Output Leakage Current
Input LOW Voltage
V
V
– 0.4
V
µA
µA
V
I
= –0.4mA
OH2
CC
OH
I
I
10
10
V
V
= V to V
SS CC
LI
LO
IN
= V to V
CC
OUT
SS
(1)
V
V
V
V
–1
V
x 0.3
IL
CC
(1)
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
x 0.7 V
+ 0.5
V
IH
CC
CC
0.4
V
I = 2mA
OL
OL
OH1
V
–0.8
V
I = –1mA
OH
CC
3089 PGM T08.3
*I is measured after a 2 second settling time upon initial power up.
SB
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
Units
(3)
t
Power-up to Read Operation
1
ms
PUR
(3)
t
Power-up to Write Operation
5
ms
PUW
3089 PGM T09
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V.
A
CC
Symbol
Test
Max.
Units
Conditions
= 0V
(2)
C
C
Output Capacitance (SO)
8
6
pF
pF
V
OUT
OUT
(2)
IN
Input Capacitance (SCK, SI, CS, WP, HOLD)
V
= 0V
3089 PGM T10.1
IN
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
8
X25640
EQUIVALENT A.C. LOAD CIRCUIT, V
= 5V
A.C. TEST CONDITIONS
CC
InputPulseLevels
V
CC
x0.1toV x0.9
CC
5V
2.16KΩ
InputRiseandFallTimes
InputandOutputTimingLevel
10ns
V
x0.5
CC
3089 PGM T11
OUTPUT
3.07KΩ
100pF
3089 ILL F13.1
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
Symbol
Parameter
Clock Frequency
Cycle Time
Min.
0
Max.
Units
MHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
SCK
CYC
LEAD
LAG
WH
WL
1000
500
500
400
400
100
100
CS Lead Time
CS Lag Time
ns
ns
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Data In Rise Time
Data In Fall Time
HOLD Setup Time
HOLD Hold Time
CS Deselect Time
Write Cycle Time
ns
ns
ns
SU
ns
H
(3)
2
2
µs
RI
(3)
FI
µs
200
200
500
ns
HD
CD
ns
(5)
ns
CS
(4)
10
ms
3089 PGM T12.2
WC
Data Output Timing
Symbol
Parameter
Min.
Max.
Units
f
t
t
t
t
t
t
t
Clock Frequency
0
1
MHz
ns
SCK
DIS
V
Output Disable Time
500
400
Output Valid from Clock LOW
Output Hold Time
ns
0
ns
HO
(3)
Output Rise Time
300
300
ns
RO
(3)
Output Fall Time
ns
FO
(3)
HOLD HIGH to Output in Low Z
HOLD LOW to Output in High Z
100
100
ns
LZ
(3)
ns
HZ
3089 PGM T13.1
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
WC
nonvolatile write cycle.
(5) After a read status register operation for WIP bit LOW, t
min. is 500µs.
CS
9
X25640
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
tHO
tWL
tDIS
SO
MSB OUT
MSB–1 OUT
LSB OUT
ADDR
LSB IN
SI
3089 ILL F10.1
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
tRI
tFI
SI
MSB IN
LSB IN
HIGH IMPEDANCE
SO
3089 ILL F11
10
X25640
Hold Timing
CS
SCK
SO
tHD
tCD
tCD
tHD
tHZ
tLZ
SI
HOLD
3089 ILL F12.1
11
X25640
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
12
X25640
PACKAGING INFORMATION
14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0° – 8°
0.050" Typical
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.41)
0.037 (0.937)
0.030" Typical
14 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F10.1
13
X25640
ORDERING INFORMATION
X25640
P
T
-V
V
CC
Limits
Device
Blank = 5V ±10%
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 8-Lead Plastic DIP
S = 14-Lead SOIC
Part Mark Convention
P = 8-Lead Plastic DIP
S = 14-Lead SOIC
X25640
X
X
Blank = 5V ±10%, 0°C to +70°C
I = 5V ±10%, –40°C to +85°C
M = 5V ±10%, –55 ºC to +125 ºC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
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