X25650S14I-2.5 [XICOR]
EEPROM, 8KX8, Serial, CMOS, PDSO14, PLASTIC, SOIC-14;
| 型号： | X25650S14I-2.5 |
| 厂家： | 
XICOR INC. |
| 描述： | EEPROM, 8KX8, Serial, CMOS, PDSO14, PLASTIC, SOIC-14 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总15页 (文件大小：479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Recommended System Management
Alternative: X5643
64K
8K x 8 Bit
X25650
5MHz SPI Serial EEPROM with Block Lock™ Protection
FEATURES
• Packages
—8-lead SOIC
• 5MHz clock rate
• Low Power CMOS
—<1µA standby current
—<5mA active current
—14-lead SOIC
DESCRIPTION
• 2.5V To 5.5V power supply
• SPI modes (0,0 & 1,1)
• 8K X 8 bits
—32 byte page mode
• Block lock protection
—Protect 1/4, 1/2 or all of EEPROM array
• Programmable hardware write protection
—In-circuit programmable ROM mode
• Built-in inadvertent write protection
—Power-up/down protection circuitry
—Write enable latch
The X25650 is a CMOS 65,536-bit serial EEPROM,
internally organized as 8K x 8. The X25650 features a
Serial Peripheral Interface (SPI) and software protocol,
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X25650 also features two additional inputs that pro-
vide the end user with added flexibility. By asserting the
HOLD input, the X25650 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25650 disabling all write attempts to the status
register, thus providing a mechanism for limiting end user
capability of altering 0, 1/4, 1/2 or all of the memory.
—Write protect pin
• Self-timed write cycle
—5ms write cycle time (typical)
• High reliability
—Endurance: 1,000,000 cycles
—Data retention: 100 years
—ESD protection: 2000V on all pins
The X25650 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
BLOCK DIAGRAM
Write
Protect
Logic
Status
Register
X Decode
Logic
8Kbyte
Array
64
64
64 X 256
64 X 256
SO
SI
Command
Decode
and
SCK
CS
HOLD
Control
Logic
128
128 X 256
Write
Control
and
32
8
WP
Timing
Logic
Y Decode
Data Register
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
REV 1.2 11/28/00
Characteristics subject to change without notice. 1 of 15
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X25650
PIN DESCRIPTIONS
Serial Output (SO)
PIN NAMES
Symbol
CS
Description
Chip Select Input
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
SO
Serial Output
Serial Input
SI
SCK
WP
Serial Clock Input
Write Protect Input
Ground
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
V
SS
V
Supply Voltage
Hold Input
CC
HOLD
NC
No Connect
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
PIN CONFIGURATION
SOIC
CS
SO
WP
V
CC
1
2
3
4
8
7
6
5
HOLD
Chip Select (CS)
SCK
SI
When CS is HIGH, the X25650 is deselected and the
SO output pin is at high impedance and unless an
internal write operation is underway, the X25650 will be
in the standby power mode. CS LOW enables the
X25650, placing it in the active power mode. It should
be noted that after power-up, a HIGH to LOW transition
on CS is required prior to the start of any operation.
V
SS
14-Lead SOIC
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
NC
NC
V
NC
CS
SO
WP
CC
HOLD
SCK
SI
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25650 status register are dis-
abled, but the part otherwise functions normally. When
WP is held HIGH, all functions, including nonvolatile
writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25650 status reg-
ister. If the internal write cycle has already been initi-
ated, WP going LOW will have no affect on a write.
V
SS
8
NC
NC
* Pin 3 and Pin 4 are internally connected.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to pause
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume com-
munication, HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25650 in a system with WP pin grounded and still
be able to write to the status register. The WP pin func-
tions will be enabled when the WPEN bit is set “1”.
Characteristics subject to change without notice. 2 of 15
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X25650
PRINCIPLES OF OPERATION
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
The X25650 is a 8K x 8 EEPROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25650 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK. CS must be LOW and the HOLD and WP
inputs must be HIGH during the entire operation.
7
6
5
4
3
2
1
0
WPEN
X
X
X
BL1
BL0
WEL
WIP
WPEN, BL0 and BL1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
other operations.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
The Write-In-Process (WIP) bit indicates whether the
X25650 is busy with a write operation. When set to a “1”,
a write is in progress, when set to a “0”, no write is in
progress. During a write, all other bits are “don’t care”.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25650 into a “PAUSE” condition. After releasing
HOLD, the X25650 will resume operation from the
point when HOLD was first asserted.
The Write Enable Latch (WEL) bit indicates the status
of the “write enable” latch. When set to a “1”, the latch
is set, when set to a “0”, the latch is reset.
The Block Lock (BL0 and BL1) bits are nonvolatile and
allow the user to select one of four levels of protection.
The X25650 is divided into four 16384-bit segments.
One, two, or all four of the segments may be protected.
That is, the user may read the segments but will be
unable to alter (write) data within the selected seg-
ments.The partitioning is controlled as illustrated below.
Write Enable Latch
The X25650 contains a “write enable” latch. This latch
must be SET before a write operation will be com-
pleted internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status reg-
ister write cycle.
Status Register Bits
BL1
BL0
Array Addresses Protected
None
0
0
1
1
0
1
0
1
$1800–$1FFF
$1000–$1FFF
$0000–$1FFF
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
WRDI
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the write enable latch (enable write operations)
Reset the write enable latch (disable write operations)
Read status register
RDSR
WRSR
READ
WRITE
Write status register
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address (1 to 32 bytes)
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Characteristics subject to change without notice. 3 of 15
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X25650
The Write-Protect-Enable (WPEN) bit is available for the X25650 as a nonvolatile enable bit for the WP pin.
WPEN
WP
X
WEL
Protected Blocks
Protected
Unprotected Blocks
Protected
Status Register
Protected
Writable
0
0
1
1
X
X
0
1
0
1
0
1
X
Protected
Writable
LOW
LOW
HIGH
HIGH
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Protected
Protected
Writable
Programmable Hardware Write Protection
next address can be read sequentially by continuing to
provide clock pulses. The address is automatically
incremented to the next higher address after each byte
of data is shifted out. When the highest address is
reached ($1FFF) the address counter rolls over to
address $0000 allowing the read cycle to be continued
indefinitely. The read operation is terminated by taking
CS HIGH. Refer to the read EEPROM array operation
sequence illustrated in Figure 1.
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register con-
trol the Programmable Hardware Write Protect feature.
Hardware Write Protection is enabled when WP pin is
LOW, and the WPEN bit is “1”. Hardware Write Protec-
tion is disabled when either the WP pin is HIGH or the
WPEN bit is “0”. When the chip is hardware write pro-
tected, nonvolatile writes are disabled to the Status
Register, including the Block Lock bits and the WPEN
bit itself, as well as the block-protected sections in the
memory array. Only the sections of the memory array
that are not block-protected can be written.
To read the status register the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the con-
tents of the status register are shifted out on the SO
line. Figure 2 illustrates the read status register
sequence.
In Circuit Programmable ROM Mode
Note that since the WPEN bit is write protected, it can-
not be changed back to a LOW state; so write protec-
tion is enabled as long as the WP pin is held LOW.
Thus an In Circuit Programmable ROM function can be
implemented by hardwiring the WP pin to Vss, writing
to and Block Locking the desired portion of the array to
be ROM, and then programming the WPEN bit HIGH.
The table above defines the program protect status for
each combination of WPEN and WP.
Write Sequence
Prior to any attempt to write data into the X25650, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
X25650. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user con-
tinues the write operation without taking CS HIGH after
issuing the WREN instruction, the write operation will
be ignored.
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
To write data to the EEPROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a thirty-
two clock operation. CS must go LOW and remain LOW
for the duration of the operation.The host may continue to
write up to 32 bytes of data to the X25650. The only
restriction is the 32 bytes must reside on the same page.
If the address counter reaches the end of the page and
the clock continues, the counter will “roll over” to the first
address of the page and overwrite any data that may
have been written.
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25650, followed by
the 16-bit address of which the last 13 are used. After
the READ opcode and address are sent, the data
stored in the memory at the selected address is shifted
out on the SO line. The data stored in memory at the
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X25650
For the write operation (byte or page write) to be com-
pleted, CS can only be brought HIGH after bit 0 of data
byte N is clocked in. If it is brought HIGH at any other
time the write operation will not be completed. Refer to
Figures 4 and 5 below for a detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
The HOLD input may be tied HIGH either directly to
VCC or tied to VCC through a resistor.
Operational Notes
The X25650 powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5
and 6 must be “0”. Figure 6 illustrates this sequence.
While the write is in progress following a status register
or EEPROM write sequence, the status register may
be read to check the WIP bit. During this time the WIP
bit will be HIGH.
Data Protection
The following circuitry has been included to prevent in-
advertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
Hold Operation
• CS must come HIGH at the proper clock count in or-
der to start a write cycle.
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW and SCK must
also be LOW when HOLD is released.
Figure 1. Read EEPROM Array Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
Instruction
16 Bit Address
15 14 13
3
2
1
0
Data Out
High Impedance
SO
7
6
5
4
3
2
1
0
MSB
Characteristics subject to change without notice. 5 of 15
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X25650
Figure 2. Read Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
SI
Instruction
Data Out
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
Figure 3. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
High Impedance
SO
Figure 4. Byte Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16 Bit Address
15 14 13
Data Byte
3
2
1
0
7
6
5
4
3
2
1
0
SI
High Impedance
SO
Characteristics subject to change without notice. 6 of 15
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X25650
Figure 5. Page Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
Instruction
16 Bit Address
15 14 13
Data Byte 1
7
6
5
4
3
2
1
0
3
2
1
0
CS
SCK
SI
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Figure 6. Write Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
Instruction
Data Byte
SI
7
6
5
4
3
2
1
0
High Impedance
SO
Characteristics subject to change without notice. 7 of 15
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X25650
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ....................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Voltage on any pin with respect to V .......–1V to +7V
SS
D.C. output current ............................................... 5mA
(soldering, 10 seconds)......................................300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
Limits
X25650-2.5
2.5V to 5.5V
–40°C
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
SCK = V x 0.1/V x 0.9 @ 5MHz,
I
V
V
supply current (active)
5
mA
CC
CC
CC
CC
SO = Open, CS = V
SS
I
supply current (standby)
1
µA
µA
µA
V
CS = V , V = V or V – 0.3V
SS
CC IN CC
SB
CC
I
Input leakage current
Output leakage current
Input LOW voltage
10
10
V
V
= V to V
SS
CC
LI
IN
I
= V to V
SS
CC
LO
OUT
(1)
V
–1
V
x 0.3
IL
CC
(1)
V
Input HIGH voltage
Output LOW voltage
Output HIGH voltage
Output LOW voltage
Output HIGH voltage
V
V
V
x 0.7
V
+ 0.5
V
IH
CC
CC
CC
CC
V
0.4
V
I
I
I
I
= 3mA, V = 5V
CC
OL1
OH1
OL
OH
OL
OH
V
– 0.8
– 0.3
V
= –1.6mA, V = 5V
CC
V
0.4
V
= 1.5mA, V = 3V
CC
OL2
OH2
V
V
= –0.4mA, V = 3V
CC
POWER-UP TIMING
Symbol
Parameter
Power-up to read operation
Power-up to write operation
Min.
Max.
Unit
(3)
T
1
1
ms
ms
PUR
(3)
T
PUW
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Parameter
Output capacitance (SO)
Input capacitance (SCK, SI, CS, WP, HOLD)
Max.
Unit
pF
Test Conditions
(3)
C
8
6
V
= 0V
= 0V
I/O
I/O
(3)
C
pF
V
IN
IN
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
(2) This parameter is periodically sampled and not 100% tested.
(3) t and t are the delays required from the time V
is stable until the specified operation can be initiated. These parameters
CC
PUR
PUW
are periodically sampled and not 100% tested.
Characteristics subject to change without notice. 8 of 15
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X25650
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
5V
3V
Input rise and fall times
Input and output timing levels
10ns
V
X 0.5
1.44KΩ
Output
1.95KΩ
1.64KΩ
Output
4.63KΩ
CC
100pF
100pF
A.C. OPERATING CHARACTERISTICS
Data Input Timing
Symbol
Parameter
Min.
0
Max.
Unit
MHz
ns
f
Clock frequency
Cycle time
5
SCK
CYC
t
200
100
100
80
t
CS lead time
ns
LEAD
t
CS lag time
ns
LAG
t
Clock HIGH time
Clock LOW time
Data setup time
Data hold time
Data in rise time
Data in fall time
HOLD setup time
HOLD hold time
CS deselect time
Write cycle time
ns
WH
t
80
ns
WL
t
20
ns
SU
t
20
ns
H
(4)
t
t
2
2
µs
RI
(4)
µs
FI
t
40
40
ns
HD
CD
t
ns
t
100
ns
CS
(5)
t
10
ms
WC
Data Output Timing
Symbol
Parameter
Min.
Max.
5
Unit
MHz
ns
f
Clock frequency
0
SCK
t
Output disable time
100
80
DIS
t
Output valid from clock LOW
Output hold time
ns
V
t
0
ns
HO
(4)
t
t
Output rise time
50
50
ns
RO
(4)
Output fall time
ns
FO
(4)
t
HOLD HIGH to output in low Z
HOLD LOW to output in high Z
50
50
ns
LZ
(4)
t
ns
HZ
Notes: (4) This parameter is periodically sampled and not 100% tested.
(5) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
WC
write cycle.
Characteristics subject to change without notice. 9 of 15
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X25650
Serial Output Timing
CS
t
t
t
LAG
CYC
WH
SCK
SO
t
t
t
t
DIS
WL
V
HO
MSB OUT
MSB–1 OUT
LSB OUT
ADDR
SI
LSB IN
Serial Input Timing
t
CS
CS
t
t
LEAD
LAG
SCK
t
t
t
t
FI
SU
H
RI
SI
MSB IN
LSB IN
High Impedance
SO
Characteristics subject to change without notice. 10 of 15
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X25650
Hold Timing
CS
t
t
t
CD
HD
CD
t
HD
SCK
t
t
LZ
HZ
SO
SI
HOLD
Characteristics subject to change without notice. 11 of 15
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X25650
PACKAGING INFORMATION
8-Lead Plastic, SOIC, Package Code S8
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" Typical
X 45°
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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X25650
PACKAGING INFORMATION
14-Lead Plastic, SOIC, Package Code S14
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"Typical
0° – 8°
0.250"
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
0.030"Typical
14 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 13 of 15
REV 1.2 11/28/00
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X25650
PACKAGING INFORMATION
8-Lead XBGA
Complete Part Number
Top Mark
XAAS
XAAT
X25650Z - 2.5
X25650ZI - 2.5
8-Lead XBGA: Top View
SO
HOLD
1 8
2
7
V
CS
V
CC
3
4
6
5
SS
S1
SCK
WP
.083 in.
NOTE: ALL DIMENSIONS IN µM (to convert into inches, 1µm = 3.94 x 10-5 inch)
ALL DIMENSIONS ARE TYPICAL VALUES
Characteristics subject to change without notice. 14 of 15
REV 1.2 11/28/00
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X25650
Ordering Information
T
X25650
P
-V
V
Limits
Device
CC
2.5 = 2.5 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
S8 = 8-Lead SOIC
S14 = 14-Lead SOIC
Part Mark Convention
Other Packages
X
Blank = 8-Lead SOIC
S = 14-Lead SOIC
X25650
X
AE = 2.5V to 5.5V, 0°C to 70°C
AF = 2.5V to 5.5V, –40°C to +85°C
LIMITED WARRANTY
©Xicor, Inc. 2001 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS ANDTRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 15 of 15
REV 1.2 11/28/00
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