X25F064PI [XICOR]
SerialFlash⑩ Memory With Block LockTM Protection; SerialFlash⑩存储器，有块LockTM保护
| 型号： | X25F064PI |
| 厂家： | 
XICOR INC. |
| 描述： | SerialFlash⑩ Memory With Block LockTM Protection |
| 文件： | 总16页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION
NOTE
A V A I L A B L E
AN61 • AN75 • AN77 • AN79 • AN82
X25F064/032/016/008
SerialFlash™ Memory With Block LockTM Protection
FEATURES
DESCRIPTION
• 1MHz Clock Rate
• SPI Serial Interface
• 64K/32K/16K/8K Bits
—32 Byte Small Sector Program Mode
• Low Power CMOS
—<1µA Standby Current
—<5mA Active Current
• 1.8V – 3.6V or 5V “Univolt” Read and
Program Power Supply Versions
• Block Lock Protection
The X25F064/032/016/008 family are 8/16/32/64K-bit
CMOS SerialFlash memory, internally organized
X8. Theyfeaturea“Univolt”ProgramandReadvoltage,
Serial Peripheral Interface (SPI), and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK), plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25F064/032/016/008 also features two additional
inputs that provide the end user with added flexibility. By
asserting the HOLD input, the X25F064/032/016/008
willignoretransitionsonitsinputs,thusallowingthehost
to service higher priority interrupts. The PP input can be
used as a hardwire input to the X25F064/032/016/008
disabling all program attempts to the status register,
thus providing a mechanism for limiting end user capa-
bility of altering 0, 1/4, 1/2, or all of the memory.
—Protect 1/4, 1/2, or all of E2PROM Array
• Built-in Inadvertent Program Protection
—Power-Up/Power-Down protection circuitry
—Program Enable Latch
—Program Protect Pin
• Self-Timed Program Cycle
—5ms Program Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
• 8-Lead PDlP Package
• 8-Lead 150 mil SOIC Packages
• 32K, 16K, 8K available in 14-Lead TSSOP,
64K available in 20-Lead TSSOP
The X25F064/032/016/008 utilizes Xicor’s proprietary
flash cell, providing a minimum endurance
of 100,000 cycles and a minimum data retention of
100 years.
FUNCTIONAL DIAGRAM
DATA REGISTER
SI
SECTOR DECODE LOGIC
SO
32
8
COMMAND
DECODE
AND CONTROL
X
SCK
DECODE
LOGIC
LOGIC
MEMORY
ARRAY
CS
STATUS
HOLD
REGISTER
HIGH VOLTAGE
CONTROL
PROGRAMMING
CONTROL LOGIC
PP
6685 ILL F01.4
SerialFlash™ and Block Lock™ Protection are trademarks of Xicor, Inc.
© Xicor, Inc. 1995, 1996 Patents Pending
6685-3.1 8/29/96 T3/C0/D0 SH
Characteristics subject to change without notice
X25F064/032/016/008
PIN DESCRIPTIONS
Serial Output (SO)
Hold (HOLD)
HOLD isusedinconjunctionwiththeCSpintoselectthe
device. Once the part is selected and a serial sequence
is underway, HOLD may be used to pause the serial
communication with the controller without resetting the
serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
SO is a push-pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of the
serial clock.
PIN CONFIGURATION
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
8-Lead DIP/SOIC
CS
SO
PP
1
2
3
4
8
7
6
5
V
CC
X25F064/
032/016/
008
HOLD
SCK
SI
V
SS
Chip Select (CS)
14-Lead TSSOP
20-Lead TSSOP
When CS is HIGH, the X25F064/032/016/008 is
deselected and the SO output pin is at high impedance
and unless an internal program operation is underway
the X25F064/032/016/008 will be in the standby power
mode. CS LOW enables the X25F064/032/016/008,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
CS
SO
NC
NC
NC
PP
NC
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
14
13
12
11
10
9
20
19
18
17
16
15
14
13
12
11
V
NC
V
CC
CS
NC
SO
NC
NC
PP
HOLD
NC
CC
NC
X25F032/
016/008
NC
HOLD
NC
NC
X25F064
SCK
SI
NC
V
8
SCK
SI
SS
V
SS
NC
NC
NC
NC
Program Protect (PP)
6685 ILL F02.4
When PP is LOW and the nonvolatile bit PPEN is “1”,
nonvolatile programming of the X25F064/032/016/008
status register is disabled, but the part otherwise func-
tions normally. When PP is held HIGH, all functions,
including nonvolatile programming operate normally.
PP going LOW while CS is still LOW will interrupt
programmingoftheX25F064/032/016/008statusregis-
ter. If the internal program cycle has already been
initiated, PP going LOW will have no effect on program-
ming.
PIN NAMES
SYMBOL
DESCRIPTION
CS
Chip Select Input
Serial Output
SO
SI
Serial Input
SCK
PP
VSS
VCC
HOLD
NC
Serial Clock Input
The PP pin function is blocked when the PPEN bit in
thestatusregisteris“0”.Thisallowstheusertoinstallthe
X25F064/032/016/008 into a system with PP pin
groundedandstillbeabletoprogramthestatusregister.
The PP pin functions will be enabled when the PPEN bit
is set “0”.
Program Protect Input
Ground
Supply Voltage
Hold Input
No Connect
6685 PGM T01.1
2
X25F064/032/016/008
PRINCIPLES OF OPERATION
formatted as follows:
The X25F064/032/016/008 family are SerialFlash
Memory designed to interface directly with the synchro-
nous serial peripheral interface (SPI) of many popular
microcontroller families.
7
6
5
4
3
2
1
0
PPEN
X
X
X
BL1
BL0
PEL PIP
6685 PGM T02.2
PPEN, BL0, and BL1 are set by the PRSR instruction.
PEL and PIP are “read-only” and automatically set by
other operations.
The X25F064/032/016/008 family contains an 8-bit
instruction register. It is accessed via the SI input, with
data being clocked in on the rising SCK. CS must be
LOWandtheHOLD andPP inputsmustbeHIGHduring
the entire operation. The PP input is “Don’t Care” if
PPEN is set “0”.
The Programming-In-Process (PIP) bit indicates
whether the X25F064/032/016/008 device is busy
with a program operation. When set to a “1”
programming is in progress, when set to a “0” no
programming is in progress. During programming, all
other bits are set to “1”.
Table 1 contains a list of the instructions and their
operation codes. All instructions, addresses and data
are transferred MSB first.
The Program Enable Latch (PEL) bit indicates the
status of the program enable latch. When set to a “1” the
latch is set; when set to a “0” the latch is reset.
DatainputissampledonthefirstrisingedgeofSCKafter
CS goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations. If the clock line is
shared with other peripheral devices on the SPI bus, the
user can assert the HOLD input to place the X25F064/
032/016/008 into a “PAUSE” condition. After
releasing HOLD, the X25F064/032/016/008 device will
resume operation from the point when HOLD was first
asserted.
The Block Lock (BL0 and BL1) bits are nonvolatile and
allow the user to select one of four levels of protection.
The X25F064/032/016/008 device array is divided into
four equal segments. One, two, or all four of the seg-
ments may be locked. That is, the user may read the
segments, but will be unable to alter (program) data
within the selected segments. The partitioning is con-
trolled as illustrated below.
Program Enable Latch
The X25F064/032/016/008 device contains a
program enable latch. This latch must be SET before a
program operation will be completed internally. The
PREN instruction will set the latch and the PRDI
instruction will reset the latch. This latch is automatically
reset on power-up and after the completion of a sector
program or status register write cycle.
Status Register Bits
Array Addresses
Locked
BL1
BL0
0
0
1
1
0
1
0
1
None
upper fourth
upper half
All
6685 PGM T03.1
Status Register
Program-Protect Enable
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a program cycle. The status register is
The Program-Protect-Enable bit (PPEN) in the
X25F064/032/016/008 status register acts as an
enable bit for the PP pin.
Table 1. Instruction Set
Instruction Name
PREN
Instruction Format*
0000 0110
Operation
Set the Program Enable Latch (Enable Program Operations)
Reset the Program Enable Latch (Disable Program Operations)
Read Status Register
PRDI
0000 0100
RDSR
0000 0101
PRSR
0000 0001
Program Status Register
READ
0000 0011
Read from Memory Array beginning at Selected Address
Program Memory Array beginning at Selected Address
(32 Bytes)
PROGRAM
0000 0010
6685 PGM T04.2
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3
X25F064/032/016/008
tion. After the read status register opcode is sent, the
contents of the status register are shifted out on the SO
line. The Read Status Register Sequence is illustrated
in Figure 2.
Locked Unlocked
Status
Register
PPEN PP PEL Blocks
Blocks
0
0
1
1
X
X
X
0
1
0
1
0
1
Locked
Locked
Locked
X
Locked Programmable Programmable
Programming Sequence
LOW
LOW
HIGH
HIGH
Locked
Locked Programmable
Locked Locked
Locked
Locked
Locked
Locked
Prior to any attempt to program the X25F064/032/016/
008device, theprogramenablelatchmustfirstbesetby
issuing the PREN instruction (See Figure 3). CS is first
taken LOW, then the PREN instruction is clocked into
the X25F064/032/016/008 device. After all eight bits of
the instruction are transmitted, CS must then be taken
HIGH. If the user continues the programming operation
without taking CS HIGH after issuing the PREN instruc-
tion, the programming operation will be ignored.
Locked Programmable Programmable
6685 PGM T05.2
The Program Protect (PP) pin and the nonvolatile
Program Protect Enable (PPEN) bit in the Status Reg-
ister control the programmable hardware write protect
feature. Hardware program protection is enabled when
PP pin is LOW, and the PPEN bit is “1”. Hardware
program protection is disabled when either the PP pin is
HIGH or the PPEN bit is “0”. When the chip is hardware
program protected, nonvolatile programming of the Sta-
tus Register in disabled, including the Block Lock bits
and the PPEN bit itself, as well as the Block Lock
sections in the memory array. Only the sections of the
memory array that are not Block Locked can be pro-
grammed.
To program the SerialFlash memory array, the user
issues the PROGRAM instruction, followed by the ad-
dress of the first location in the sector and then the data
to be programmed. The data is programmed in a 256-
clock operation. CS must go LOW and remain LOW for
the duration of the operation. The 32 bytes must reside
in the same sector and cannot cross sector boundaries.
If the address counter reaches the end of the sector
and the clock continues, or if fewer than 32 bytes are
clockedin, thecontentsofthesectorcannotbeguaranteed.
Note: Since the PPEN bit is program protected, it
cannot be changed back to a “0”, as long as
the PP pin is held LOW.
Fortheprogramoperationtobecompleted, CS canonly
be brought HIGH after bit 0 of data byte 32 is clocked in.
If it is brought HIGH at any other time the program
operation will not be completed. Refer to Figure 4 below
for a detailed illustration of the programming sequence
and time frames in which CS going HIGH is valid.
Clock and Data Timing
Data input on the SI line is latched on the rising edge of
SCK. Data is output on the SO line by the falling edge of
SCK.
Read Sequence
To program the status register, the PRSR instruction is
followed by the data to be programmed. Data bits 0, 1,
4, 5 and 6 must be “0”. This sequence is shown in Figure 5.
WhenreadingfromtheSerialFlashmemoryarray, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25F064/032/016/008
device, followed by the 16-bit address. After the read
opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the SO
line. The data stored in memory at the next address can
be read sequentially by continuing to provide clock
pulses. The address is automatically incremented to the
nexthigheraddressaftereachbyteofdataisshiftedout.
When the highest address is reached the address
counter rolls over to address $0000, allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS HIGH. Refer to the Read
SerialFlashMemoryArrayOperationSequenceillustrated
in Figure 1.
While the program cycle is in progress, following a
status register or memory write sequence, the status
register may be read to check the PIP bit. During this
time the PIP bit will be HIGH.
Hold Operation
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
canbepulledLOWtosuspendthetransferuntilitcanbe
resumed. The only restriction is that the SCK input
must be LOW when HOLD is first pulled LOW and SCK
must also be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to VCC
or tied to VCC through a resistor.
To read the status register, the CS line is first pulled
LOW to select the device followed by the 8-bit instruc-
4
X25F064/032/016/008
Operational Notes
Data Protection
The device powers-up in the following state:
• The device is in the low power standby state.
The following circuitry has been included to prevent
inadvertent programming:
• The program enable latch is reset upon power-up.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
• A program enable instruction must be issued to set
the program enable latch.
• SO pin is high impedance.
• CS must come HIGH at the proper clock count in
order to start a program cycle.
• The program enable latch is reset.
Figure 1. Read SerialFlash Memory Array Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
INSTRUCTION
16 BIT ADDRESS
15 14 13
3
2
1
0
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
6685 ILL F03
Figure 2. Read Status Register Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
6685 ILL F04
5
X25F064/032/016/008
Figure 3. Program Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
INSTRUCTION
SI
HIGH IMPEDANCE
SO
6685 ILL F05.1
6
X25F064/032/016/008
Figure 4. Programming Sequence
CS
20 21 22 23 24 25 26 27 28 29 30 31
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
INSTRUCTION
16 BIT ADDRESS
15 14 13
DATA BYTE 1
3
2
1
0
7
6
5
4
3
2
1
0
CS
SCK
SI
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2
DATA BYTE 3
DATA BYTE 32
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6685 ILL F07.1
Figure 5. Program Status Register Operation Sequence
CS
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
7
9
6
SCK
SI
INSTRUCTION
DATA BYTE
5
4
3
2
1
0
HIGH IMPEDANCE
SO
6685 ILL F08
7
X25F064/032/016/008
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias.................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
thoselistedintheoperationalsectionsofthisspecification
is not implied. Exposure to absolute maximum rating
conditionsforextendedperiodsmayaffectdevicereliability.
Voltage on any Pin with Respect to V ......... –1V to +7V
SS
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 Seconds) ............................. 300°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
X25F064/032/016/008
X25F064/032/016/008–5
Limits
Temp
Min.
0°C
Max.
+70°C
+85°C
1.8V to 3.6V
4.5V to 5.5V
Commercial
Extended
Industrial
–20°C
–40°C
6685 PGM T07.3
+85°C
6685 PGM T06.2
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
SCK = V x 0.1/V x 0.9 @ 1MHz,
I
V
Supply Current (Active)
5
mA
CC
CC
CC CC
SO = Open, CS = V
SS
(2)
I
I
I
I
V
V
Supply Current (Standby)
Supply Current (Standby)
1
µA
µA
µA
µA
V
CS = V , V = V or V , V
= 3.6V
= 5V
SB1
SB2
LI
CC
CC IN SS CC CC
10
10
10
CS = V , V = V or V , V
SS
CC IN CC CC
CC
Input Leakage Current
Output Leakage Current
Input LOW Voltage
V
V
= V
to V
IN
SS
= V
CC
to V
–1
LO
OUT
SS
CC
(1)
V
V
V
V
V
V
V
x 0.7
V
x 0.3
IL
CC
CC
(1)
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
+ 0.5
V
IH
CC
0.4
0.4
V
I
I
I
I
= 1.5mA, V
= 2.7V
= 2.7V
= 5V
OL1
OH1
OL2
OH2
OL
OH
OL
OH
CC
V
V
– 0.3
– 0.8
V
= –0.4mA, V
CC
= 3mA, V
CC
= –1.6mA, V = 5V
CC
CC
CC
V
V
6685 PGM T08.4
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
Units
(3)
t
Power-up to Read Operation
1
ms
PUR
(3)
t
Power-up to Write Operation
5
ms
PUW
6685 PGM T09
CAPACITANCE T = 25°C, f = 1MHz, V
= 5V.
A
CC
Symbol
Test
Output Capacitance (SO)
Input Capacitance (SCK, SI, CS, WP, HOLD)
Max.
Units
Conditions
= 0V
(2)
C
C
8
6
pF
pF
V
OUT
OUT
(2)
IN
V
IN
= 0V
6685 PGM T10.1
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
8
X25F064/032/016/008
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
InputPulseLevels
V
CC
x0.1toV x0.9
CC
2.7V
5V
InputRiseandFallTimes
InputandOutputTimingLevel
10ns
1.64KΩ
OUTPUT
4.63KΩ
1.44KΩ
OUTPUT
1.95KΩ
V
CC
x0.5
6685 PGM T11
100pF
100pF
6685 ILL F09.3
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
Symbol
Parameter
Clock Frequency
Cycle Time
Min.
0
Max.
Units
MHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
SCK
CYC
LEAD
LAG
WH
WL
1000
500
500
400
400
100
100
CS Lead Time
CS Lag Time
ns
ns
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Data In Rise Time
Data In Fall Time
HOLD Setup Time
HOLD Hold Time
CS Deselect Time
Program Cycle Time
ns
ns
ns
SU
ns
H
(4)
2
2
µs
RI
(4)
FI
µs
200
200
2
ns
HD
CD
CS
ns
µs
(5)
10
ms
6685 PGM T12.3
PC
Data Output Timing
Symbol
Parameter
Min.
Max.
Units
f
t
t
t
t
t
t
t
Clock Frequency
0
1
MHz
ns
SCK
DIS
V
Output Disable Time
500
400
Output Valid from Clock LOW
Output Hold Time
ns
0
ns
HO
(4)
Output Rise Time
300
300
ns
RO
(4)
Output Fall Time
ns
FO
(4)
HOLD HIGH to Output in Low Z
HOLD LOW to Output in High Z
100
100
ns
LZ
(4)
ns
HZ
6685 PGM T13.2
Notes: (4) This parameter is periodically sampled and not 100% tested.
(5) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
WC
nonvolatile program cycle.
9
X25F064/032/016/008
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
MSB OUT
tHO
tWL
tDIS
SO
SI
MSB–1 OUT
LSB OUT
ADDR
LSB IN
6685 ILL F10
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
tRI
tFI
SI
MSB IN
LSB IN
HIGH IMPEDANCE
SO
6685 ILL F11
10
X25F064/032/016/008
Hold Timing
CS
tHD
tCD
tCD
tHD
SCK
SO
tHZ
tLZ
SI
HOLD
6685 ILL F12
11
X25F064/032/016/008
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
12
X25F064/032/016/008
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050" TYPICAL
X 45°
0.020 (0.50)
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
13
X25F064/032/016/008
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.002 (.05)
.0118 (.30)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F32
14
X25F064/032/016/008
PACKAGING INFORMATION
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.252 (6.4)
.300 (6.6)
.047 (1.20)
.0075 (.19)
.002 (.05)
.0118 (.30)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F45
15
X25F064/032/016/008
ORDERING INFORMATION
X25FXXX
P
T
–X
V
CC
Range
Device
Blank = 1.8V to 3.6V
5 = 4.5V to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
E = Extended = –20°C to +85°C
I = Industrial = –40°C to +85°C
Package
X25F064
X25F032
P = 8-Lead Plastic DIP X25F016
S = 8-Lead SOIC
X25F008
V = 20-Lead TSSOP
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
V = 14-Lead TSSOP
Part Mark Convention
P = 8-Lead Plastic DIP
Blank = 8-Lead SOIC
V = 14/20-Lead TSSOP
X25FXXX
X25F064
X25F032
X25F016
X25F008
X
Blank = 1.8V to 3.6V, 0°C to +70°C
5 = 4.5V to 5.5V, 0°C to +70°C
I5 = 4.5V to 5.5V, –40°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and backup features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
16
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