X2804CPI-90 [XICOR]
5 Volt, Byte Alterable E2PROM; 5伏，可变的字节E2PROM
| 型号： | X2804CPI-90 |
| 厂家： | 
XICOR INC. |
| 描述： | 5 Volt, Byte Alterable E2PROM |
| 文件： | 总13页 (文件大小：57K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4K
X2804C
5 Volt, Byte Alterable E2PROM
DESCRIPTION
512 x 8 Bit
FEATURES
2
The Xicor X2804C is a 512 x 8 E PROM, fabricated with
anadvanced, highperformanceN-channelfloatinggate
MOS technology. Like all Xicor Programmable nonvola-
tile memories it is a 5V only device. The X2804C
features the JEDEC approved pinout for byte-wide
memories, compatible with industry standard RAMs,
ROMs and EPROMs.
• 90ns Access Time
• Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• High Performance Advanced NMOS Technology
• Fast Write Cycle Times
—16 Byte Page Write Operation
—Byte or Page Write Cycle: 5ms Typical
—Complete Memory Rewrite: 640ms Typical
—Effective Byte Write Cycle Time: 300µs
Typical
The X2804C supports a 16-byte page write operation,
typicallyprovidinga300µs/bytewritecycle,enablingthe
entire memory to be written in less than 640ms. The
X2804C also features DATA Polling, a system software
support scheme used to indicate the early completion of
a write cycle.
2
Xicor E PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
• DATA Polling
—Allows User to Minimize Write Cycle Time
• JEDEC Approved Byte-Wide Pinout
• High Reliability
—Endurance: 10,000 Cycles
—Data Retention: 100 Years
PIN CONFIGURATION
PLASTIC DIP
A
A
1
24
23
22
21
20
19
18
17
16
15
14
13
V
A
7
6
5
4
3
2
1
0
0
1
2
CC
8
2
A
3
NC
A
4
WE
A
5
OE
NC
A
6
X2804C
A
7
CE
I/O
A
8
7
I/O
I/O
I/O
V
9
I/O
I/O
I/0
6
5
10
11
12
4
I/O
SS
3
6612 FHD F02.1
©Xicor, Inc. 1993, 1995 Patents Pending
6612-1.3 3/27/96 T2/C1/D1 NS
Characteristics subject to change without notice
1
X2804C
PIN DESCRIPTIONS
PIN NAMES
Symbol
Addresses (A –A )
Description
0
8
The Address inputs select an 8-bit memory location
during a read or write operation.
A –A
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
0
8
I/O –I/O
0
7
WE
CE
OE
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power con-
sumption is reduced.
V
CC
V
Ground
SS
Output Enable (OE)
NC
No Connect
TheOutputEnableinputcontrolsthedataoutputbuffers
and is used to initiate read operations.
6612 PGM T01
FUNCTIONAL DIAGRAM
4.096-BIT
E PROM
ARRAY
X BUFFERS
LATCHES AND
DECODER
2
A –A
0
8
ADDRESS
INPUTS
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
I/O –I/O
DATA INPUTS/OUTPUTS
0
7
CE
OE
WE
CONTROL
LOGIC
V
CC
V
6612 FHD F01
SS
2
X2804C
DEVICE OPERATION
Read
byte load cycle, started by the WE HIGH to LOW
transition, must begin within 20µs of the falling edge of
the preceding WE. If a subsequent WE HIGH to LOW
transition is not detected within 20µs, the internal auto-
matic programming cycle will commence. There is no
page write window limitation. The page write window is
infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 20µs.
Read operations are initiated by both OE and CE LOW
and WE HIGH. The read operation is terminated by
either CE or OE returning HIGH. This two line control
architecture eliminates bus contention in a system envi-
ronment. The data bus will be in a high impedance state
when either OE or CE is HIGH.
DATA Polling
Write
The X2804C features DATA Polling as a method to
indicate to the host system that the byte write or page
writecyclehascompleted.DATAPollingallowsasimple
bit test operation to determine the status of the X2804C,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
Write operations are initiated when bothCE and WE are
LOW and OE is HIGH. The X2804C supports both a CE
and WE controlled write cycle. That is, the address is
latchedbythefallingedgeofeitherCEorWE,whichever
occurslast. Similarly, thedataislatchedinternallybythe
rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
complement of that data on I/O (i.e., write data = 0xxx
7
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O will reflect true data.
7
Page Write Operation
WRITE PROTECTION
The page write feature of the X2804C allows the entire
memory to be typically written in 450ms. Page write
allows two to sixteen bytes of data to be consecutively
written to the X2804C prior to the commencement of the
internal programming cycle. Although the host system
may read data from any other device in the system to
transfer to the X2804C, the destination page address of
the X2804C should be the same on each subsequent
Therearethreefeaturesthatprotectthenonvolatiledata
from inadvertent writes.
• Noise Protection—A WE pulse which is typically
less than 10ns will not initiate a write cycle.
• V Sense—All functions are inhibited when V is
CC
CC
≤3V, typically.
• Write Inhibit—Holding either OE LOW, WE HIGH,
or CE HIGH during power-up and power-down, will
inhibit inadvertent writes. Write cycle timing specifi-
cations must be observed concurrently.
strobe of the WE and CE inputs. That is, A through A
must be the same for each transfer of data to the
X2804C during a page write cycle.
4
10
The page write mode can be entered during any write
operation. Following the initial byte write cycle, the host
can write an additional one to fifteen bytes in the same
manner as the first byte was written. Each successive
ENDURANCE
2
Xicor E PROMs are designed and tested for applica-
tions requiring extended endurance.
3
X2804C
SYSTEM CONSIDERATIONS
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the l/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high fre-
BecausetheX2804Cisfrequentlyusedinlargememory
arrays, it is provided with a two line control architecture
for both read and write operations. Proper usage can
provide the lowest possible power dissipation and elimi-
nate the possibility of contention where multiple I/O pins
share the same bus.
quency ceramic capacitor be used between V
and
To gain the most benefit, it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
CC
V
SS
at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V and V for each
CC
SS
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
Because the X2804C has two power modes, standby
and active, proper decoupling of the memory array is of
4
X2804C
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecificationis
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
X2804C....................................... –10°C to +85°C
X2804CI..................................... –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
.................................. –1V to +7V
SS
D.C. Output Current ............................................. 5mA
Lead Temperature (Soldering, 10 seconds)...... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
Industrial
0°C
+70°C
X2804C
5V ±10%
6612 PGM T03
–40°C
+85°C
6612 PGM T02.2
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
(1)
Symbol
Parameter
Min. Typ.
Max.
Units
Test Conditions
I
V
V
Current (Active)
70
110
mA
CE = OE = V
CC
CC
IL
All I/O’s = Open
Other Inputs = V
CC
I
SB
Current (Standby)
35
50
mA
CE = V , OE = V
CC
IH
IL
All I/O’s = Open
Other Inputs = V
CC
I
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V , CE = V
LO
OUT
SS
CC
IH
(2)
V
V
V
V
–1
2
0.8
lL
(2)
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
+1
V
IH
CC
0.4
V
I
I
= 2.1mA
OL
OH
OL
2.4
V
= –400µA
OH
6612 PGM T02.1
Notes: (1) Typical values are for T = 25°C and nominal supply voltage and are not tested.
A
(2) V min. and V max. are for reference only and are not tested.
IL IH
5
X2804C
ENDURANCE AND DATA RETENTION
Parameter
Min.
Max.
Unit
Minimum Endurance
Data Retention
10,000
100
Cycles/Byte
Years
6612 PGM T03
POWER-UP TIMING
(1)
Typ.
Symbol
Parameter
Units
(3)
t
t
Power-Up to Read Operation
Power-Up to Write Operation
1
5
ms
ms
PUR
(3)
PUW
6612 PGM T04
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Test
Max.
Units
Conditions
(3)
C
C
Input/Output Capacitance
Input Capacitance
10
6
pF
pF
V
= 0V
= 0V
I/O
I/O
(3)
IN
V
IN
6612 PGM T05.1
A.C. CONDITIONS OF TEST
MODE SELECTION
Input Pulse Levels
0V to 3V
CE
OE
WE
Mode
I/O
Power
Input Rise and
Fall Times
L
L
L
H
X
L
H
L
Read
Write
D
D
Active
Active
OUT
5ns
IN
Input and Output
Timing Levels
H
X
X
X
X
H
Standby and Write Inhibit
Write Inhibit
High Z Standby
1.5V
3852 PGM T06.1
—
—
—
X
Write Inhibit
—
6612 PGM T07
Note: (3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUITS
5V
1.92KΩ
OUTPUT
1.37KΩ
100pF
6612 FHD F22.3
6
X2804C
A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Read Cycle Limits
X2804C-90 X2804C-15
X2804C-20
X2804C-25
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Units
t
t
t
t
t
t
t
t
t
Read Cycle Time
90
150
200
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
CE
AA
OE
Chip Enable Access Time
Address Access Time
90
90
60
150
150
80
200
200
100
250
250
100
Output Enable Access Time
CE LOW to Active Output
OE LOW to Active Output
CE HIGH to High Z Output
OE HIGH to High Z Output
(4)
0
0
0
0
0
0
0
0
LZ
(4)
OLZ
(4)
50
50
60
60
60
60
60
60
HZ
(4)
OHZ
OH
Output Hold from
Address Change
0
0
0
0
6612 PGM T10.1
Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
WE
t
t
OLZ
OHZ
t
t
t
LZ
OH
HZ
HIGH Z
DATA I/O
DATA VALID
DATA VALID
t
AA
6612 FHD F04
Notes: (4) t min., t , t
LZ HZ OLZ
, and t
OHZ
are periodically sampled and not 100% tested. t max. and t max. are measured from the
HZ OHZ
point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
7
X2804C
Write Cycle Limits
X2804C-90
X2804C-15,-20,-25
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
(5)
t
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery
Data Valid
10
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
WC
t
5
80
0
5
100
0
AS
AH
CS
CH
t
t
t
0
0
t
80
10
5
100
10
10
100
50
CW
t
OES
t
OEH
t
80
50
WP
t
WPH
t
t
100
100
100
100
DV
DS
DH
Data Setup
35
5
50
10
10
1
t
Data Hold
t
Delay to Next Write
Byte Load Cycle
10
1
DW
t
µs
BLC
6612 PGM T09.1
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AS
AH
t
t
CS
CH
CE
OE
t
t
OES
t
OEH
t
WP
WE
DV
DATA IN
DATA OUT
DATA VALID
DS
t
t
DH
HIGH Z
6612 FHD F05
Notes: (5) t
WC
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation. For faster t , please refer to X28C16 and
WC
X28HC16 product data sheets.
8
X2804C
CE Controlled Write Cycle
ADDRESS
t
WC
t
t
AS
AH
t
CW
CE
t
OES
OE
t
OEH
t
t
CS
CH
WE
t
DV
DATA IN
DATA VALID
t
t
DS
HIGH Z
DH
DATA OUT
6612 FHD F06
Page Mode Write Cycle
(6)
OE
CE
t
t
BLC
WP
WE
(7)
t
WPH
ADDR.*
I/O
LAST BYTE
BYTE n+2
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
t
WC
*For each successive write within the page write operation, A –A should be the same or
10
4
writes to an unknown address could occur.
6612 FHD F07.1
Notes: (6) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively
performing a polling operation.
(7) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform
to either the CE or WE controlled write cycle timing.
9
X2804C
DATA Polling Timing Diagram(10)
ADDRESS
CE
An
An
An
WE
t
t
OEH
OES
OE
t
DW
=X
D
=X
D
=X
D
I/O
7
IN
OUT
OUT
t
WC
6612 FHD F08
Note: (10) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
10
X2804C
Normalized Active Supply Current
vs. Ambient Temperature
Normalized Standby Supply Current
vs. Ambient Temperature
1.4
1.4
V
= 5V
V
= 5V
CC
CC
1.2
1.0
0.8
0.6
1.2
1.0
0.8
0.6
–55
+25
+125
–55
+25
+125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
6612 FHD F09.1
6612 FHD F10.1
Normalized Access Time
vs. Ambient Temperature
1.4
1.2
1.0
0.8
0.6
V
= 5V
CC
–55
+25
+125
AMBIENT TEMPERATURE (°C)
6612 FHD F11.1
11
X2804C
PACKAGING INFORMATION
24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.265 (32.13)
1.230 (31.24)
0.557 (14.15)
0.530 (13.46)
PIN 1 INDEX
PIN 1
0.080 (2.03)
0.065 (1.65)
1.100 (27.94)
REF.
0.162 (4.11)
0.140 (3.56)
SEATING
PLANE
0.030 (0.76)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.022 (0.56)
0.014 (0.36)
0.625 (15.87)
0.600 (15.24)
0°
TYP. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F03
12
X2804C
ORDERING INFORMATION
X2804C
X
X
-X
Access Time
–90 = 90ns
Device
–15 = 150ns
–20 = 200ns
–25 = 250ns
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
P = 24-Lead Plastic DIP
13
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