X28C010EMB-25 [XICOR]
5 Volt, Byte Alterable E2PROM; 5伏，可变的字节E2PROM
| 型号： | X28C010EMB-25 |
| 厂家： | 
XICOR INC. |
| 描述： | 5 Volt, Byte Alterable E2PROM |
| 文件： | 总25页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1M
X28C010
5 Volt, Byte Alterable E2PROM
DESCRIPTION
128K x 8 Bit
FEATURES
2
The Xicor X28C010 is a 128K x 8 E PROM, fabricated
with Xicor's proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C010 is a 5V only device. The
X28C010 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard
EPROMs.
• Access Time: 120ns
• Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or V Control Circuits
—Self-Timed
PP
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS:
TheX28C010supportsa256-bytepagewriteoperation,
effectively providing a 19µs/byte write cycle and en-
abling the entire memory to be typically written in less
than 2.5 seconds. The X28C010 also features DATA
Polling and Toggle Bit Polling, system software support
schemes used to indicate the early completion of a write
cycle. In addition, the X28C010 supports Software Data
Protection option.
—Active: 50mA
—Standby: 500µA
• Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
• High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
• Early End of Write Detection
—DATA Polling
2
Xicor E PROMs are designed and tested for applica-
tions requiring extended endurance. Data retention is
specified to be greater than 100 years.
—Toggle Bit Polling
EXTENDED LCC
PLCC
PIN CONFIGURATIONS
LCC
30
CERDIP
FLAT PACK
SOIC (R)
4
3
2
32 31
30
29
1
4
3
2
32 31
A
A
A
A
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
A
A
A
5
6
7
8
9
A
A
A
A
A
7
6
5
4
3
2
1
0
0
7
6
5
4
3
2
1
0
0
14
13
8
14
13
8
PGA
1
28
27
26
25
24
23
22
A
A
I/O
15
I/O
17
I/O
I/O
21
I/O
22
0
2
3
5
6
NC
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
V
19
9
9
CC
X28C010
(TOP VIEW)
X28C010
(TOP VIEW)
A
A
11
11
A
2
WE
CE
24
A
13
A
14
I/O
16
V
I/O
20
I/O
23
16
15
12
1
0
1
SS
4
7
A
A
10
11
12
13
10
11
12
13
OE
A
OE
A
18
A
A
3
NC
A
A
10
10
OE
26
A
12
A
A
25
A
A
CE
I/O
CE
I/O
2
4
3
10
11
4
A
14
11
I/O
I/O
7
7
15 16 17 18 19 20
21
A
A
5
A
14
7
6
5
4
3
2
1
0
0
1
2
13
A
10
A
A
27
A
28
5
X28C010
(BOTTOM VIEW)
9
15 16 17 18 19 20
14
9
7
6
A
8
A
9
A
A
A
29
A
13
30
A
7
6
7
8
8
6
A
8
A
11
3858 FHD F03.1
X28C010
NC
NC
NC
32
A
V
36
NC
34
A
A
31
TSOP
15
16
CC
12
14
A
9
OE
5
4
2
A
10
11
12
13
14
15
16
A
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
OE
A
10
CE
I/O
I/O
I/O
I/O
I/O
11
9
8
13
14
10
A
NC
NC
33
WE
35
A
A
A
CE
3
1
A
A
NC
NC
NC
WE
7
6
5
4
3
A
I/O
7
I/O
6
I/O
5
I/O
4
3858 FHD F20
I/O
I/O
I/O
V
9
NC
NC
10
11
12
13
14
15
16
17
18
19
20
V
CC
NC
NC
NC
A
A
A
X28C010
V
NC
NC
SS
I/O
3
SS
3858 FHD F02.1
I/O
I/O
I/O
16
15
12
2
1
0
A
A
A
A
A
A
A
A
7
6
5
4
0
1
2
3
3858 ILL F21
Characteristics subject to change without notice
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3858-3.1 4/3/97 T1/C0/D0 SH
1
X28C010
PIN DESCRIPTIONS
PIN NAMES
Symbol
A –A
Addresses (A –A )
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
0
16
The Address inputs select an 8-bit memory location
during a read or write operation.
0
16
I/O –I/O
0
7
WE
CE
OE
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
writeoperations.WhenCEisHIGH,powerconsumption
is reduced.
V
CC
V
SS
Ground
Output Enable (OE)
NC
No Connect
TheOutputEnableinputcontrolsthedataoutputbuffers
and is used to initiate read operations.
3858 PGM T01
Data In/Data Out (I/O –I/O )
0
7
Data is written to or read from the X28C010 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C010.
FUNCTIONAL DIAGRAM
1M-BIT
E PROM
ARRAY
X BUFFERS
LATCHES AND
DECODER
2
A –A
8
16
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
A –A
0
7
I/O –I/O
DATA INPUTS/OUTPUTS
0
7
CE
OE
WE
CONTROL
LOGIC AND
TIMING
V
CC
V
3858 FHD F01
SS
2
X28C010
DEVICE OPERATION
Read
Write Operation Status Bits
The X28C010 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
natesbuscontentioninasystemenvironment. Thedata
bus will be in a high impedance state when either OE or
CE is HIGH.
Figure 1. Status Bit Assignment
Write
I/O DP TB
5
4
3
2
1
0
Write operations are initiated when bothCE and WE are
LOW and OE is HIGH. The X28C010 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE, which-
everoccurslast.Similarly,thedataislatchedinternallyby
therisingedgeofeitherCE orWE, whicheveroccursfirst.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
RESERVED
TOGGLE BIT
DATA POLLING
3858 FHD F11
DATA Polling (I/O )
7
Page Write Operation
The X28C010 features DATA Polling as a method to
indicate to the host system that the byte write or page
writecyclehascompleted.DATAPollingallowsasimple
bittestoperationtodeterminethestatusoftheX28C010,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
The page write feature of the X28C010 allows the entire
memory to be written in 5 seconds. Page write allows
two to two hundred fifty-six bytes of data to be consecu-
tively written to the X28C010 prior to the commence-
ment of the internal programming cycle. The host can
fetch data from another device within the system during
apagewriteoperation(changethesourceaddress), but
complement of that data on I/O (i.e., write data = 0xxx
7
xxxx, read data = 1xxx xxxx). Once the programming
the page address (A through A ) for each subsequent
8
16
cycle is complete, I/O will reflect true data. Note: If the
7
valid write cycle to the part during this operation must be
the same as the initial page address.
X28C010 is in the protected state and an illegal write
operation is attempted DATA Polling will not operate.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty six bytes
in the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to
LOW transition, must begin within 100µs of the falling
edge of the preceding WE. If a subsequent WE HIGH to
LOW transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continuestoaccessthedevicewithinthebyteloadcycle
time of 100µs.
Toggle Bit (I/O )
6
The X28C010 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle, I/O will toggle from
HIGH to LOW and LOW to HIGH on subsequent at-
tempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
6
3
X28C010
DATA Polling I/O
7
Figure 2. DATA Polling Bus Sequence
LAST
WRITE
WE
CE
OE
V
IH
V
HIGH Z
OH
I/O
7
V
OL
X28C010
READY
A –A
0
14
An
An
An
An
An
An
An
3858 FHD F12
Figure 3. DATA Polling Software Flow
DATA Polling can effectively halve the time for writing to
the X28C010. The timing diagram in Figure 2 illustrates
the sequence of events on the bus. The software flow
diagraminFigure3illustratesonemethodofimplement-
ing the routine.
WRITE DATA
NO
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
I/O
NO
7
COMPARE?
YES
X28C010
READY
3858 FHD F13
4
X28C010
The Toggle Bit I/O
6
Figure 4. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
V
OH
HIGH Z
I/O
6
*
*
V
OL
X28C010
READY
* Beginning and ending state of I/O will vary.
6
3858 FHD F14
Figure 5. Toggle Bit Software Flow
TheToggleBitcaneliminatethesoftwarehousekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C010 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagraminFigure4illustratesthesequenceofeventson
thebus. ThesoftwareflowdiagraminFigure5illustrates
a method for polling the Toggle Bit.
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
NO
COMPARE
OK?
YES
X28C010
READY
3858 FHD F15
5
X28C010
HARDWARE DATA PROTECTION
The X28C010 can be automatically protected during
power-upandpower-downwithouttheneedforexternal
circuits by employing the software data protection fea-
ture. The internal software data protection circuit is
enabled after the first write operation utilizing the soft-
warealgorithm. Thiscircuitisnonvolatileandwillremain
set for the life of the device unless the reset command
is issued.
The X28C010 provides three hardware features that
protect nonvolatile data from inadvertent writes.
• Noise Protection—A WE pulse less than 10ns will not
initiate a write cycle.
• Default V Sense—All functions are inhibited when
CC
V
CC
is ≤3.5V.
Once the software protection is enabled, the X28C010
is also protected from inadvertent and accidental writes
in the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
• Write inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle
during power-up and power-down, maintaining data
integrity.
SOFTWARE DATA PROTECTION
SOFTWARE ALGORITHM
The X28C010 offers a software controlled data protec-
tionfeature.TheX28C010isshippedfromXicorwiththe
software data protection NOT ENABLED: that is the
device will be in the standard operating mode. In this
mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific ad-
dresses. Refer to Figures 6 and 7 for the sequence. The
three byte sequence opens the page write window
enabling the host to write from one to two hundred fifty-
six bytes of data. Once the page load cycle has been
completed, the device will automatically be returned to
the data protected state.
device once V was stable.
CC
6
X28C010
Software Data Protection
Figure 6. Timing Sequence—Byte or Page Write
V
(V
)
CC
CC
0V
DATA
ADDR
AA
5555
55
2AAA
A0
5555
WRITES
OK
t
WRITE
PROTECTED
WC
CE
≤t
BYTE
OR
PAGE
BLC MAX
WE
3858 FHD F16
Figure 7. Write Sequence for
Software Data Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithmisusedanddatahasbeenwritten,theX28C010
will automatically disable further writes unless another
command is issued to cancel it. If no further commands
are issued the X28C010 will be write protected during
power-down and after any subsequent power-up. The
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
state of A and A while executing the algorithm is
15
16
don’t care.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA A0
TO ADDRESS
5555
WRITE DATA XX
TO ANY
ADDRESS
OPTIONAL
BYTE/PAGE
LOAD OPERATION
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER t
RE-ENTERS DATA
WC
PROTECTED STATE
3858 FHD F17
7
X28C010
Resetting Software Data Protection
Figure 8. Reset Software Data Protection Timing Sequence
V
CC
STANDARD
OPERATING
MODE
DATA
AA
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
≥t
WC
ADDR 5555
CE
WE
3858 FHD F18
Figure 9. Software Sequence to Deactivate
Software Data Protection
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E PROM programmer, the following six step algo-
WRITE DATA AA
TO ADDRESS
5555
2
rithm will reset the internal protection circuit. After t
the X28C010 will be in standard operating mode.
,
WC
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 80
TO ADDRESS
5555
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 20
TO ADDRESS
5555
3858 FHD F19
8
X28C010
SYSTEM CONSIDERATIONS
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high fre-
BecausetheX28C010isfrequentlyusedinlargememory
arrays it is provided with a two line control architecture
for both read and write operations. Proper usage can
provide the lowest possible power dissipation and elimi-
nate the possibility of contention where multiple I/O pins
share the same bus.
quency ceramic capacitor be used between V
and
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
CC
V
SS
at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V and V for each
CC
SS
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
Because the X28C010 has two power modes, standby
and active, proper decoupling of the memory array is of
Active Supply Current vs. Ambient Temperature
I
(RD) by Temperature over Frequency
CC
18
60
5.0 V
CC
V
= 5V
CC
50
16
14
12
10
–55°C
+25°C
40
30
20
10
+125°C
–10
+35
+80
+125
–55
3
6
9
12
15
0
AMBIENT TEMPERATURE (°C)
FREQUENCY (MHz)
3858 ILL F26
3858 ILL F24
Standby Supply Current vs. Ambient Temperature
0.3
V
= 5V
CC
0.25
0.2
0.15
0.1
0.05
–10
+35
+80
+125
–55
AMBIENT TEMPERATURE (°C)
3858 ILL F25
9
X28C010
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecificationis
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
X28C010...................................... –10°C to +85°C
X28C010I................................... –65°C to +135°C
X28C010M................................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
....................................... –1V to +7V
SS
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
RECOMMEND OPERATING CONDITIONS
Supply Voltage
Limits
Temperature
Min.
Max.
X28C010
5V ±10%
Commercial
Industrial
Military
0°C
+70°C
+85°C
+125°C
3858 PGM T03
–40°C
–55°C
3858 PGM T02
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
I
V
Current (Active)
50
mA CE = OE = V , WE = V ,
CC
CC
IL
IH
(TTL Inputs)
All I/O’s = Open, Address Inputs =
.4V/2.4V Levels @ f = 5MHz
I
I
V
Current (Standby)
3
mA CE = V , OE = V
IH IL
SB1
CC
(TTL Inputs)
All I/O’s = Open, Other Inputs = V
IH
V
CC
Current (Standby)
500
µA
CE = V – 0.3V, OE = V
CC IL
SB2
(CMOS Inputs)
All I/O’s = Open, Other Inputs = V
CC
I
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V , CE = V
IH
LO
OUT
SS
CC
(1)
V
V
V
V
–1
2
0.8
lL
(1)
V
+ 1
CC
V
IH
0.4
V
I
I
= 2.1mA
OL
OH
OL
2.4
V
= –400µA
OH
3858 PGM T04.2
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
10
X28C010
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(2)
t
t
Power-up to Read Operation
Power-up to Write Operation
100
5
µs
PUR
(2)
ms
PUW
3858 PGM T05
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Parameter
Max.
Units
Test Conditions
(2)
C
C
Input/Output Capacitance
Input Capacitance
10
10
pF
pF
V
V
= 0V
= 0V
I/O
I/O
(2)
IN
IN
3858 PGM T06
ENDURANCE AND DATA RETENTION
Parameter
Min.
Max.
Units
Endurance
10,000
100,000
100
Cycles Per Byte
Cycles Per Page
Years
Endurance
Data Retention
3858 PGM T07.1
A.C. CONDITIONS OF TEST
MODE SELECTION
Input Pulse Levels
0V to 3V
CE
L
OE
L
WE
H
Mode
I/O
Power
Read
D
Active
OUT
IN
Input Rise and
Fall Times
L
H
L
Write
D
Active
10ns
1.5V
H
X
X
Standby and
Write Inhibit
High Z
Standby
Input and Output
Timing Levels
3858 PGM T05.1
X
X
L
X
H
Write Inhibit
Write Inhibit
—
—
—
X
—
3858 PGM T08
EQUIVALENT A.C. LOAD CIRCUIT
SYMBOL TABLE
5V
WAVEFORM
INPUTS
OUTPUTS
1.92KΩ
Must be
steady
Will be
steady
OUTPUT
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
1.37KΩ
100pF
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
3858 FHD F04.3
N/A
Center Line
is High
Impedance
Note: (2) This parameter is periodically sampled and not 100%
tested.
11
X28C010
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28C010-12 X28C010-15 X28C010-20 X28C010-25
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Units
t
t
t
t
t
t
t
t
t
Read Cycle Time
120
150
200
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
CE
AA
OE
Chip Enable Access Time
Address Access Time
120
120
50
150
150
50
200
200
50
250
250
50
Output Enable Access Time
CE LOW to Active Output
OE LOW to Active Output
CE HIGH to High Z Output
OE HIGH to High Z Output
(3)
0
0
0
0
0
0
0
0
LZ
(3)
OLZ
(3)
50
50
50
50
50
50
50
50
HZ
(3)
OHZ
OH
Output Hold from
Address Change
0
0
0
0
3858 PGM T09.1
Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
WE
t
t
OLZ
OHZ
t
t
t
LZ
OH
HZ
HIGH Z
DATA I/O
DATA VALID
DATA VALID
t
AA
3858 FHD F05
Note: (3) t min.,t , t
min., and t
are periodically sampled and not 100% tested. t max. and t
max. are measured, with C =
OHZ L
LZ
HZ OLZ
OHZ
HZ
5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
12
X28C010
Write Cycle Limits
Symbol
Parameter
Min.
Max.
Units
(4)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery
Data Valid
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
WC
AS
0
50
0
AH
CS
0
CH
100
10
10
100
100
CW
OES
OEH
WP
WPH
DV
1
Data Setup
50
0
DS
Data Hold
DH
Delay to Next Write
Byte Load Cycle
10
0.2
DW
BLC
100
µs
3858 PGM T10.1
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AS
AH
t
t
CS
CH
CE
OE
t
t
OES
OEH
t
WP
WE
t
WPH
t
DV
DATA IN
DATA OUT
DATA VALID
t
t
DS
DH
HIGH Z
3858 FHD F06
Notes: (4) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WC
time the device requires to complete internal write operation.
13
X28C010
CE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
CW
CE
t
WPH
t
OES
OE
t
OEH
t
t
CS
CH
DH
WE
t
DV
DATA IN
DATA VALID
t
t
DS
HIGH Z
DATA OUT
3858 FHD F07
Page Write Cycle
(5)
OE
CE
t
t
BLC
WP
WE
t
WPH
(6)
ADDRESS *
I/O
LAST BYTE
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
BYTE n+2
t
WC
*For each successive write within the page write operation, A –A should be the same or
16
8
writes to an unknown address could occur.
3858 FHD F08
Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively
performing a polling operation.
(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must
conform to either the CE or WE controlled write cycle timing.
14
X28C010
(7)
DATA Polling Timing Diagram
ADDRESS
CE
A
A
A
N
N
N
WE
t
t
OEH
OES
OE
t
DW
=X
D
=X
D
=X
D
I/O
7
IN
OUT
OUT
t
WC
3858 FHD F09
Toggle Bit Timing Diagram
CE
WE
t
t
OES
OEH
OE
t
DW
HIGH Z
I/O
6
*
*
t
WC
* I/O beginning and ending state will vary.
6
3858 FHD F10
Note: (7) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
15
X28C010
NOTES
16
X28C010
PACKAGING INFORMATION
32-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
1.690 (42.95)
MAX.
0.610 (15.49)
0.500 (12.70)
PIN 1
0.005 (0.13) MIN.
0.100 (2.54) MAX.
SEATING
PLANE
0.232 (5.90) MAX.
0.060 (1.52)
0.015 (0.38)
0.150 (3.8)
MIN.
0.200 (5.08)
0.150 (3.18)
0.065 (1.65)
0.023 (0.58)
0.033 (0.84)
TYP. 0.055 (1.40)
0.014 (0.36)
TYP. 0.018 (0.46)
0.110 (2.79)
0.090 (2.29)
TYP. 0.018 (0.46)
0.620 (15.75)
0.590 (14.99)
TYP. 0.614 (15.60)
0°
0.015 (0.33)
0.008 (0.20)
15°
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F09
17
X28C010
PACKAGING INFORMATION
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
0.150 (3.81) BSC
0.020 (0.51) x 45° REF.
0.095 (2.41)
0.075 (1.91)
PIN 1
0.022 (0.56)
0.006 (0.15)
0.055 (1.39)
0.200 (5.08)
BSC
0.045 (1.14)
TYP. (4) PLCS.
0.028 (0.71)
0.040 (1.02) x 45° REF.
0.022 (0.56)
(32) PLCS.
TYP. (3) PLCS.
0.050 (1.27) BSC
0.458 (11.63)
0.442 (11.22)
0.088 (2.24)
0.050 (1.27)
0.458 (11.63)
––
0.300 (7.62)
BSC
0.120 (3.05)
0.060 (1.52)
0.560 (14.22)
0.540 (13.71)
0.558 (14.17)
––
0.400 (10.16)
BSC
PIN 1 INDEX CORDER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
3926 FHD F14
18
X28C010
PACKAGING INFORMATION
32-LEAD CERAMIC FLAT PACK
0.019 (0.48)
0.015 (0.38)
PIN 1 INDEX
1
32
0.828 (21.04)
0.812 (20.64)
0.055 (1.40)
0.045 (1.14)
0.045 (1.14) MAX.
0.005 (0.13) MIN.
0.440 (11.18)
0.430 (10.93)
0.130 (3.30)
0.090 (2.29)
0.0065 (0.17)
0.004 (0.10)
0.370 (9.40)
0.300 (7.62)
0.047 (1.19)
0.026 (0.66)
0.347 (8.82)
0.333 (8.46)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F20
19
X28C010
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.030" TYPICAL
32 PLACES
0.050"
0.420 (10.67)
TYPICAL
0.050"
TYPICAL
0.510"
TYPICAL
0.400"
0.050 (1.27) TYP.
0.300"
REF
0.410"
FOOTPRINT
0.021 (0.53)
0.013 (0.33)
TYP. 0.017 (0.43)
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.045 (1.14) x 45°
0.015 (0.38)
0.095 (2.41)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
0.060 (1.52)
0.140 (3.56)
0.453 (11.51)
0.100 (2.45)
TYP. 0.136 (3.45)
0.447 (11.35)
TYP. 0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
REF.
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
20
X28C010
PACKAGING INFORMATION
36-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K
15
14
11
9
17
16
19
18
21
20
22
23
25
27
29
32
33
A
0.008 (0.20)
0.050 (1.27)
13
12
10
8
24
26
A
28
30
31
NOTE: LEADS 5, 14, 23, & 32
7
TYP. 0.100 (2.54)
ALL LEADS
6
5
2
3
36
1
34
35
TYP. 0.180 (.010)
(4.57 ± .25)
4 CORNERS
4
TYP. 0.180 (.010)
(4.57 ± .25)
4 CORNERS
0.120 (3.05)
0.100 (2.54)
0.072 (1.83)
0.062 (1.57)
PIN 1 INDEX
0.770 (19.56)
0.750 (19.05)
SQ
0.020 (0.51)
0.016 (0.41)
A
A
0.185 (4.70)
0.175 (4.45)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F21
21
X28C010
PACKAGING INFORMATION
32-LEAD CERAMIC SMALL OUTLINE GULL WING PACKAGE TYPE R
0.060 NOM.
SEE DETAIL “A”
FOR LEAD
INFORMATION
0.020 MIN.
0.165 TYP.
0.035 TYP.
0.340
±0.007
0.015 R TYP.
0.015 R
TYP.
0.035 MIN.
DETAIL “A”
0.050"
TYPICAL
0.0192
0.0138
0.050"
TYPICAL
0.560"
TYPICAL
0.840
MAX.
0.750
±0.005
0.030" TYPICAL
32 PLACES
0.050
FOOTPRINT
0.440 MAX.
0.560 NOM.
NOTES:
1. ALL DIMENSIONS IN INCHES
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3926 FHD F27
22
X28C010
PACKAGING INFORMATION
32-PAD STRETCHED CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE N
0.300 BSC
0.035 x 45° REF.
DETAIL A
0.005/0.015
0.006/0.022
0.085 ± 0.010
PIN 1
0.025 ± 0.003
DETAIL A
0.400 BSC
0.050 ± 0.005
0.020 (1.02) x 45° REF.
TYP. (3) PLCS.
0.050 BSC
0.450 ± 0.008
0.060/0.120
0.458 MAX.
0.700 ± 0.010
0.708 MAX.
PIN #1 INDEX CORNER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
3926 FHD F35
23
X28C010
PACKAGING INFORMATION
40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T
12.522 (0.493)
12.268 (0.483)
1.143 (0.045)
0.889 (0.035)
0.965
PIN #1 IDENT.
(0.038)
O 1.016 (0.040) 0.127 (0.005) DP.
O 0.762 (0.030) 0.076 (0.003) DP.
X
1.219 (0.048)
0.500 (0.0197)
1
10.058 (0.396)
9.957 (0.392)
0.178 (0.007)
15° TYP.
SEATING
PLANE
0.254 (0.010)
0.152 (0.006)
A
0.065 (0.0025)
1.016 (0.040)
SEATING
PLANE
DETAIL A
0.813 (0.032) TYP.
0.432 (0.017)
14.148 (0.557)
13.894 (0.547)
0.152 (0.006)
TYP.
4° TYP.
0.432 (0.017)
0.508 (0.020) TYP.
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
(0.012 ± 0.002)
SOLDER PADS
TYPICAL
40 PLACES
15 EQ. SPC. @ 0.50 ± 0.04
0.0197 ± 0.016 = 9.50 ± 0.06
(0.374 ± 0.0024) OVERALL
TOL. NON-CUMULATIVE
0.17 (0.007)
0.03 (0.001)
0.50 ± 0.04
(0.0197 ± 0.0016)
1.30 ± 0.05
(0.051 ± 0.002)
FOOTPRINT
NOTE:
3926 ILL F39.2
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
24
X28C010
ORDERING INFORMATION
X28C010
X
X
-X
Access Time
–12 = 120ns
–15 = 150ns
–20 = 200ns
–25 = 250ns
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
D = 32-Lead Cerdip
E = 32-Pad LCC
F = 32-Lead Flat Pack
J = 32-Lead PLCC
K = 36-Lead Pin Grid Array
R = 32-Lead Hermetic SOIC (Gull Wing)
N = 32-Lead Extended LCC
T = 40-Lead TSOP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
25
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