X28C16J-12 [XICOR]
EEPROM, 2KX8, 120ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32;
| 型号： | X28C16J-12 |
| 厂家： | 
XICOR INC. |
| 描述： | EEPROM, 2KX8, 120ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总18页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16K
2K x 8 Bit
X28C16
2
5 Volt, Byte Alterable E PROM
FEATURES
DESCRIPTION
• 70ns Access Time
• Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or V
Control Circuits
—Self-Timed
The X28C16 is an 2K x 8 E2PROM, fabricated with
Xicor’s proprietary, high performance, floating gate CMOS
technology. Like all Xicor programmable nonvolatile
memories the X28C16 is a 5V only device. The X28C16
features the JEDEC approved pinout for byte-wide
memories, compatible with industry standard RAMs.
PP
—No Erase Before Write
The X28C16 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle and enabling
the entire memory to be typically written in 0.1 seconds.
The X28C16 also features DATA Polling and Toggle Bit
Polling, two methods providing early end of write
detection. In addition, the X28C16 includes a user-
optional software data protection mode that further
enhances Xicor’s hardware write protect capability.
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS
—40 mA Active Current Max.
—200 µA Standby Current Max.
• Fast Write Cycle Times
—64 Byte Page Write Operation
—Byte or Page Write Cycle: 2ms Typical
—Complete Memory Rewrite: 0.1 sec.Typical
—Effective Byte Write Cycle Time: 32µs Typical
• Software Data Protection
Xicor E2PROMs are designed and tested for applications
requiring extended endurance. Inherent data retention is
greater than 100 years.
• End of Write Detection
—DATA Polling
—Toggle Bit
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100Years
• JEDEC Approved Byte-Wide Pinout
PIN CONFIGURATION
LCC
PLCC
4
3
2
1
32 31 30
A
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
6
8
9
A
5
NC
NC
OE
A
4
A
3
X28C16
(TOP VIEW)
A
2
A
10
11
12
13
10
A
1
CE
I/O
A
0
7
NC
I/O
I/O
6
0
14 15 16 17 18 19 20
3857 FRM F03
Xicor, Inc. 1998 Patents Pending
7069 8/26/98 T2/C0/D0 RZ
Characteristics subject to change without notice
1
X28C16
PIN DESCRIPTIONS
Addresses (A0–A10)
PIN NAMES
Symbol
Description
Address Inputs
The Address inputs select an 8-bit memory location
during a read or write operation.
A0–A10
I/O0–I/O7
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Chip Enable (CE)
WE
CE
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
OE
VCC
Output Enabl (OE)
VSS
NC
Ground
The Output Enable input controls the data output buffers
and is used to initiate read operations.
No Connect
Data In/Data Out (I/O0–I/O7)
3857 FRM T01
Data is written to or read from the X28C16 through the I/O
pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C16.
FUNCTIONAL DIAGRAM
16,384-BIT
2
E PROM
X BUFFERS
LATCHES AND
DECODER
ARRAY
A –A
0
10
ADDRESS
INPUTS
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
I/O –I/O
0
7
DATA INPUTS/OUTPUTS
CE
CONTROL
LOGICAND
TIMING
OE
WE
V
CC
V
SS
3857 FRM F01
2
X28C16
DEVICE OPERATION
Read
Write Operation Status Bits
The X28C16 provides the user two write operation status
bits. These can be used to optimize a system write cycle
time. The status bits are mapped onto the I/O bus as
shown in Figure 1.
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture
eliminates bus contention in a system environment. The
data bus will be in a high impedance state when either OE
or CE is HIGH.
Figure 1. Status Bit Assignment
Write
I/O DP TB
5
4
3
2
1
0
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C16 supports both a CE
and WE controlled write cycle. That is, the address is
latched by the falling edge of either CE or WE, whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either CE or WE, whichever occurs first. A
byte write operation, once initiated, will automatically
continue to completion, typically within 2ms.
RESERVED
TOGGLE BIT
DATA POLLING
3857 FRM F11
DATA Polling (I/O )
7
The X28C16 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28C16,
eliminating additional interrupt inputs or external
hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the
Page Write Operation
The page write feature of the X28C16 allows the entire
memory to be written in 0.1 seconds. Page write allows
two to sixty-four bytes of data to be consecutively written
to the X28C16 prior to the commencement of the internal
programming cycle. The host can fetch data from another
device within the system during a page write operation
complement of that data on I/O (i.e. write data = 0xxx
7
(change the source address), but the page address (A
6
xxxx, read data = 1xxx xxxx). Once the programming
through A ) for each subsequent valid write cycle to the
10
cycle is complete, I/O will reflect true data.
7
part during this operation must be the same as the initial
page address.
Toggle Bit (I/O )
6
The X28C16 also provides another method for
determining when the internal write cycle is complete.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to sixty-three bytes in the
same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to
LOW transition, must begin within 100µs of the falling
edge of the preceding WE. If a subsequent WE HIGH to
LOW transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is no
page write window limitation. Effectively the page write
window is infinitely wide, so long as the host continues to
access the device within the byte load cycle time of
100µs.
During the internal programming cycle I/O will toggle
6
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
3
X28C16
DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
LAST
WRITE
WE
CE
OE
VIH
An
V
HIGH Z
OH
I/O
7
V
OL
X28C16
READY
A –A
0
10
An
An
An
An
An
An
3857 FRM F12
Figure 3. DATA Polling Software Flow
DATA Polling can effectively reduce the time for writing to
the X28C16.The timing diagram in Figure 2 illustrates the
sequence of events on the bus. The software flow
WRITE DATA
diagram in Figure
3
illustrates one method of
implementing the routine.
NO
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
NO
7
COMPARE?
YES
READY
3857 FRM F13
4
X28C16
THE POLLING I/O
6
Figure 4. Toggle Bit Software Flow
LAST
WRITE
WE
CE
OE
V
HIGH Z
OH
I/O
6
*
*
V
X28C16
READY
OL
* Beginning and ending state of I/O6 will vary.
3857 FRM F14
Figure 5. Toggle Bit Software Flow
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C16 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on
the bus. The software flow diagram in Figure 5 illustrates
a method for polling the Toggle Bit.
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
NO
COMPARE
OK?
YES
READY
3857 FRM F15
5
X28C16
HARDWARE DATA PROTECTION
The internal software data protection circuit is enabled
after the first write operation utilizing the software
algorithm. This circuit is nonvolatile and will remain set for
the life of the device unless the reset command is issued.
The X28C16 provides two hardware features that protect
nonvolatile data from inadvertent writes.
• Default V Sense—All write functions are inhibited
CC
Once the software protection is enabled, the X28C16 is
also protected from inadvertent and accidental writes in
the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
when V is ≤3V typically.
CC
• Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
SOFTWARE DATA PROTECTION
SOFTWARE ALGORITHM
The X28C16 offers a software controlled data protection
feature. The X28C16 is shipped from Xicor with the
software data protection NOT ENABLED; that is, the
device will be in the standard operating mode. In this
mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the device
Selecting the software data protection mode requires the
host system to precede data write operations by a series
of three write operations to three specific addresses.
Refer to Figure 6 and 7 for the sequence. The three-byte
sequence opens the page write window enabling the host
to write from one to sixty-four bytes of data. Once the
page load cycle has been completed, the device will
automatically be returned to the data protected state.
once V was stable.
CC
The X28C16 can be automatically protected during
power-up and power-down without the need for external
circuits by employing the software data protection feature.
6
X28C16
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
V
(V
)
CC
CC
0V
DATA
ADDR
AA
555
55
2AA
A0
555
WRITES
OK
t
WRITE
PROTECTED
WC
CE
≤t
BYTE
OR
PAGE
BLC MAX
WE
3857 FRM F16
Figure 7. Write Sequence for
Software Data Protedction
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used, the X28C16 will automatically disable
further writes unless another command is issued to
deactivate it. If no further commands are issued the
X28C16 will be write protected during power-down and
after any subsequent power-up.
WRITE DATA AA
TO ADDRESS
555
WRITE DATA 55
TO ADDRESS
2AA
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA A0
TO ADDRESS
555
BYTE/PAGE
LOAD ENABLED
WRITE DATA XX
TO ANY
ADDRESS
OPTIONAL BYTE
OR PAGE WRITE
ALLOWED
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER t
WC
RE-ENTERS DATA
PROTECTED STATE
3857 FRM F17
7
X28C16
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
V
CC
DATA
AA
55
2AA
A0
555
AA
555
55
AAA
20
555
STANDARD
OPERATING
MODE
≥t
ADDR 555
WC
CE
WE
3857 FRM F18.2
Figure 9. Software Sequence to
Deactivate Software Data Protection
In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an
E PROM programmer, the following six step algorithm will
2
WRITE DATA AA
TO ADDRESS
555
reset the internal protection circuit. After t , the X28C16
WC
will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA 55
TO ADDRESS
2AA
WRITE DATA A0
TO ADDRESS
555
WRITE DATA AA
TO ADDRESS
555
WRITE DATA 55
TO ADDRESS
AAA
WRITE DATA 20
TO ADDRESS
555
3857 FRM F19.2
8
X28C16
SYSTEM CONSIDERATIONS
The magnitude of these spikes is dependent on the
output capacitive loading of the I/Os. Therefore, the larger
the array sharing a common bus, the larger the transient
spikes. The voltage peaks associated with the current
transients can be suppressed by the proper selection and
placement of decoupling capacitors. As a minimum, it is
recommended that a 0.1µF high frequency ceramic
Because the X28C16 is frequently used in large memory
arrays, it is provided with a two line control architecture for
both read and write operations. Proper usage can provide
the lowest possible power dissipation and eliminate the
possibility of contention where multiple I/O pins share the
same bus.
capacitor be used between V and V at each device.
CC
SS
Depending on the size of the array, the value of the
capacitor may have to be larger.
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V and V for each
CC
SS
eight devices employed in the array. This bulk capacitor is
employed to overcome the voltage droop caused by the
inductive effects of the PC board traces.
Because the X28C16 has two power modes, standby and
active, proper decoupling of the memory array is of prime
concern. Enabling CE will cause transient current spikes.
Normalized I (RD) by Temperature
Normalized ICC (RD) @ 25% Over
CC
Over Frequency
the V Range and Frequency
CC
1.4
1.4
1.2
1.0
0.8
5.5 V
CC
- 55°C
5.5 V
1.2
1.0
0.8
CC
+ 25°C
+ 125°C
5.0 V
CC
4.5 V
CC
0.6
0.4
0.2
0.6
0.4
0.2
0
10
FREQUENCY (MHz)
20
0
10
FREQUENCY (MHz)
20
3857 FRM F20.1
3857 FRM F21.1
9
X28C16
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
X28C16..............................................–10°C to +85°C
X28C16I, X28C16M ........................–65°C to +135°C
Storage Temperature..............................–65°C to +150°C
Voltage on any Pin with
Respect to V ...................................... –1V to +7.0V
SS
D.C. Output Current ....................................................5mA
Lead Temperature
(Soldering, 10 seconds) ...................................300°C
RECOMMEND OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
+125°C
Supply Voltage
Limits
X28C16
5V ±10%
–40°C
–55°C
3857 FRM TO3.1
Military
3857 FRM TO2.1
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Limits
(1)
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
15
40
mA
CE = OE = VIL, WE = VIH,
VCC Current (Active)
(TTL Inputs)
ICC
All I/O’s = Open, Address Inputs =
TTL Levels @ f = 10 MHz
1
2
mA
µA
CE = VIH, OE = VIL
VCC Current (Standby)
(TTL Inputs)
ISB1
All I/O’s = Open, Other Inputs = VIH
100
200
CE = VCC – 0.3V, OE = GND
VCC Current (Standby)
(CMOS Inputs)
ISB2
All I/O’s = Open, Other Inputs =
VCC — 0.3V
ILI
V
IN = VSS to VCC
Input Leakage Current
Output Leakage Current
Input LOW Voltage
±10
±10
0.8
µA
µA
V
ILO
VOUT = VSS to VCC, CE = VIH
(2)
VlL
–1
2
(2)
V
CC + 1
VIH
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
VOL
VOH
I
I
OL = 5mA
0.4
V
OH = –5mA
2.4
V
3857 FRM TO4.2
Notes: (1) Typical values are for T = 25°C and nominal supply voltage
A
(2) VIL min. and VIH max. are for reference only and are not tested.
10
X28C16
ENDURANCE AND DATA RETENTION
Parameter
Minimum Endurance
Data Retention
Min.
100,000
100
Max.
Units
Cycles
Years
3857 FRM TO5.3
POWER-UP TIMING
Symbol
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
100
5
Units
µs
(3)
tPUR
(3)
tPUW
ms
3857 FRM TO6
CAPACITANCE TA = +25°C, f = 1MHZ, VCC = 5V
Symbol
Parameter
Max.
10
Units
pF
Test Conditions
I/O = 0V
VIN = 0V
(3)
V
CI/O
Input/Output Capacitance
Input Capacitance
(3)
CIN
6
pF
3857 FRM TO7.1
MODE SELECTION
A.C. CONDITIONS OF TEST
CE
L
OE
L
WE
Mode
Read
Write
I/O
DOUT
DIN
Power
Active
Active
Input Pulse Levels
0V to 3V
5ns
H
L
Input Rise and
Fall Times
L
H
Input and Output
Timing Levels
Standby and
Write Inhibit
1.5V
H
X
X
High Z
Standby
3857 FRM TO8.1
X
X
L
X
H
Write Inhibit
Write Inhibit
—
—
—
—
X
3857 FRM FTO9
EQUIVALENT A.C. LOAD CIRCUIT
SYMBOL TABLE
5V
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
1.92KΩ
OUTPUT
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
1.37KΩ
30pF
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
3857 FRM F22.3
N/A
Center Line
is High
Impedance
Note: (3) This parameter is periodically sampled and not 100%
tested.
11
X28C16
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28C16-70
X28C16-12
–40° to +85°C
–55° to +125°C
Symbol
tRC
Parameter
Read Cycle Time
Min.
Max.
Min.
Max.
Units
70
120
ns
Chip Enable
Access Time
tCE
tAA
tOE
70
70
35
120
120
50
ns
ns
ns
ns
Address Access
Time
Output Enable
Access Time
CE LOW to Active
Output
(4)
tLZ
0
0
0
0
OE LOW to Active
Output
(4)
tOLZ
ns
ns
ns
CE HIGH to High
Z Output
(4)
tHZ
30
30
30
30
OE HIGH to High
Z Output
(4)
tOHZ
tOH
Output Hold from
Address Change
0
0
ns
3857 FRM T10.1
Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
WE
t
t
OLZ
OHZ
t
t
t
t
LZ
OH
AA
HZ
HIGH Z
DATA I/O
DATA VALID
DATA VALID
3857 FRM F05
Notes: (4) tLZ min.,tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured from the point when CE
or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
12
X28C16
Write Cycle Limits
(1)
Symbol
Parameter
Write Cycle Time
Address Setup Time
Min.
Typ.
Max.
Units
ms
ns
(5)
tWC
tAS
2
5
0
50
0
tAH
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery
Data Valid
ns
tCS
ns
tCH
0
ns
tCW
tOES
tOEH
tWP
tWPH
50
0
ns
ns
0
ns
50
50
ns
(6)
ns
(6)
tDV
tDS
tDH
1
µs
Data Setup
50
0
ns
Data Hold
ns
(6)
tDW
Delay to Next Write
Byte Load Cycle
10
µs
tBLC
0.15
100
µs
3857 FRM T11.2
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AS
AH
t
t
CS
CH
CE
OE
t
t
OES
t
OEH
t
WP
WE
DV
DATA IN
DATA OUT
DATA VALID
t
t
DS
DH
HIGH Z
3857 FRM F06
Notes: (5) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the
device requires to automatically complete internal write operation.
(6) t , t
and t are periodically sampled and not 100% tested.
DV WPH
DW
13
X28C16
CE Controlled Write Cycle
t
WC
ADDRESS
t
t
AS
AH
t
CW
CE
t
OES
OE
t
OEH
t
CS
t
t
CH
DH
WE
t
DV
DATA VALID
DATA IN
t
DS
HIGH Z
DATA OUT
3857 FRM F07
Page Write Cycle
(7)
OE
CE
t
t
WP
BLC
WE
t
WPH
(8)
ADDRESS *
I/O
LASTBYTE
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
BYTE n+2
t
WC
*For each successive write within the page write operation, A –A should be the same or
10
6
writes to an unknown address could occur.
3857 FRM F08
Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to
fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a poll-
ing operation.
(8) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either
the CE or WE controlled write cycle timing.
14
X28C16
(9)
DATA Polling Timing Diagram
ADDRESS
CE
An
An
An
WE
t
t
OEH
OES
OE
t
DW
D
=X
D
=X
I/O
D
=X
OUT
OUT
IN
7
t
WC
3857 FRM F09
(9)
Toggle Bit Timing Diagram
CE
WE
t
OES
t
OEH
OE
t
DW
HIGH Z
I/O
*
6
*
t
WC
* I/O beginning and ending state will vary, depending upon actual t
.
WC
6
3857 FRM F10
Notes: (9) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
15
X28C16
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.420 (10.67)
0.050 (1.27) TYP.
0.021 (0.53)
0.013 (0.33)
TYP.0.017 (0.43)
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.045 (1.14) x 45°
0.495 (12.57)
0.015 (0.38)
0.095 (2.41)
0.485 (12.32)
TYP.0.490 (12.45)
0.060 (1.52)
0.140 (3.56)
0.453 (11.51)
0.100 (2.45)
TYP.0.136 (3.45)
0.447 (11.35)
TYP.0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
REF.
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP.0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP.0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
16
X28C16
PACKAGING INFORMATION
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
0.150 (3.81) BSC
0.020 (0.51) x 45° REF.
0.095 (2.41)
0.075 (1.91)
PIN 1
0.022 (0.56)
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
0.200 (5.08)
BSC
TYP. (4) PLCS.
0.028 (0.71)
0.040 (1.02) x 45° REF.
TYP. (3) PLCS.
0.022 (0.56)
(32) PLCS.
0.050 (1.27) BSC
0.458 (11.63)
0.442 (11.22)
0.458 (11.63)
––
0.088 (2.24)
0.050 (1.27)
0.120 (3.05)
0.060 (1.52)
0.300 (7.62)
BSC
0.560 (14.22)
0.540 (13.71)
0.400 (10.16)
BSC
0.558 (14.17)
––
PIN 1 INDEX CORNER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
3926 FHD F14
17
X28C16
ORDERING INFORMATION
X
X28C16
X
-X
AccessTime
–70 = 70ns
Device
–12 = 120ns
Temperature Range
Blank = Commercial = 0°C to 70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
J = 32-Lead PLCC
E = 32-Pad LCC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
18
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