X28C513JM-15 [XICOR]
5 Volt, Byte Alterable E2PROM; 5伏，可变的字节E2PROM
| 型号： | X28C513JM-15 |
| 厂家： | 
XICOR INC. |
| 描述： | 5 Volt, Byte Alterable E2PROM |
| 文件： | 总25页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512K
X28C512/X28C513
64K x 8 Bit
5 Volt, Byte Alterable E2PROM
FEATURES
• Two PLCC and LCC Pinouts
—X28C512
—X28C010 E PROM Pin Compatible
—X28C513
• Access Time: 90ns
2
• Simple Byte and Page Write
—Single 5V Supply
2
—Compatible with Lower Density E PROMs
— No External High Voltages or V Control
PP
Circuits
—Self-Timed
DESCRIPTION
2
The X28C512/513 is an 64K x 8 E PROM, fabricated
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS:
with Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C512/513 is a 5V only device.
TheX28C512/513featurestheJEDECapprovedpinout
for bytewide memories, compatible with industry stan-
dard EPROMS.
—Active: 50mA
—Standby: 500µA
• Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
• High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
• Early End of Write Detection
—DATA Polling
The X28C512/513 supports a 128-byte page write op-
eration, effectivelyprovidinga39µs/bytewritecycleand
enabling the entire memory to be written in less than 2.5
seconds. TheX28C512/513alsofeaturesDATA Polling
andToggleBitPolling,systemsoftwaresupportschemes
used to indicate the early completion of a write cycle. In
addition, the X28C512/513 supports the Software Data
Protection option.
—Toggle Bit Polling
TSOP
PIN CONFIGURATIONS
PLCC / LCC
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
A
A
A
A
NC
NC
NC
WE
OE
A
10
CE
11
9
8
13
14
30
29
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
4
3
2
32 31
A
A
5
6
7
8
9
A
A
A
A
A
PLASTIC DIP
CERDIP
7
6
5
4
3
2
1
0
0
14
13
8
1
28
27
26
25
24
23
22
FLAT PACK
SOIC (R)
A
A
9
9
NC
NC
V
X28C512
(TOP VIEW)
A
10
11
12
13
14
15
16
17
18
19
20
V
X28C512
11
CC
NC
A
OE
A
SS
10
11
12
13
NC
NC
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
NC
NC
NC
NC
I/O
A
10
2
WE
NC
A
CE
I/O
NC
A
A
A
A
A
A
2
1
0
A
3
I/O
I/O
I/O
15
12
15
12
7
6
5
4
7
15 16 17 18 19 20
21
14
A
4
A
14
A
A
A
A
0
1
2
3
A
5
A
7
6
5
4
3
2
1
0
0
1
2
13
A
6
A
8
A
9
3856 FHD F03
A
7
3856 ILL F22
A
8
PGA
A
11
X28C512
A
9
I/O
15
I/O
17
I/O
I/O
21
I/O
22
OE
0
2
3
5
6
30
19
4
3
2
32 31
A
10
11
12
13
14
15
16
A
A
A
A
A
A
A
5
29
28
27
26
25
24
23
22
A
A
A
A
6
5
4
3
2
1
0
8
10
CE
24
A
13
A
14
I/O
16
V
I/O
20
I/O
23
1
1
0
1
SS
4
7
6
9
A
CE
18
7
11
OE
26
A
A
12
A
A
25
I/O
7
I/O
6
I/O
5
I/0
4
2
4
3
10
11
NC
OE
A
8
11
X28C513
(TOP VIEW)
9
I/O
I/O
I/O
V
A
10
A
A
27
A
28
5
9
BOTTOM
VIEW
10
11
12
13
9
7
10
CE
A
A
A
29
A
13
30
6
7
8
NC
I/O
8
6
7
I/O
I/O
I/O
3
0
6
15 16 17 18 19 20
SS
21
NC
NC
32
A
V
36
NC
34
A
A
31
15
CC
14
12
14
5
4
2
3856 FHD F01
NC
NC
NC
1
NC
33
WE
35
3
3856 FHD F04
3856 FHD F02
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3856-3.2 8/5/97 T1/C0/D0 EW
Characteristics subject to change without notice
1
X28C512/X28C513
PIN DESCRIPTIONS
PIN NAMES
Symbol
A –A
Addresses (A –A )
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
0
15
The Address inputs select an 8-bit memory location
during a read or write operation.
0
15
I/O –I/O
0
7
WE
CE
OE
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
writeoperations.WhenCEisHIGH,powerconsumption
is reduced.
V
CC
V
SS
Ground
Output Enable (OE)
NC
No Connect
TheOutputEnableinputcontrolsthedataoutputbuffers
and is used to initiate read operations.
3856 PGM T01
Data In/Data Out (I/O –I/O )
0
7
Data is written to or read from the X28C512/513 through
the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C512/513.
FUNCTIONAL DIAGRAM
512K-BIT
E PROM
ARRAY
X BUFFERS
LATCHES AND
DECODER
2
A –A
7
15
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
A –A
0
6
I/O –I/O
0
7
DATA INPUTS/OUTPUTS
CE
OE
CONTROL
LOGIC AND
TIMING
WE
V
CC
V
SS
3856 FHD F05
2
X28C512/X28C513
DEVICE OPERATION
Read
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100µs.
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
natesbuscontentioninasystemenvironment. Thedata
bus will be in a high impedance state when either OE or
CE is HIGH.
Write Operation Status Bits
TheX28C512/513providestheusertwowriteoperation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Write
Figure 1. Status Bit Assignment
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C512/513 supports both
a CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE, which-
ever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
5ms.
I/O DP TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
3856 FHD F06
Page Write Operation
DATA Polling (I/O )
7
The page write feature of the X28C512/513 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to one hundred twenty-eight bytes of data to
beconsecutivelywrittentotheX28C512/513priortothe
commencement of the internal programming cycle. The
host can fetch data from another device within the
systemduringapagewriteoperation(changethesource
The X28C512/513 features DATA Polling as a method
to indicate to the host system that the byte write or page
writecyclehascompleted.DATAPollingallowsasimple
bittestoperationtodeterminethestatusoftheX28C512/
513, eliminating additional interrupt inputs or external
hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the
address), but the page address (A through A ) for
7
15
complement of that data on I/O (i.e. write data = 0xxx
7
each subsequent valid write cycle to the part during this
operation must be the same as the initial page address.
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O will reflect true data.
7
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by the
WE HIGH to LOW transition, must begin within 100µs of
the falling edge of the preceding WE. If a subsequent
WE HIGH to LOW transition is not detected within
100µs, the internal automatic programming cycle will
commence. There is no page write window limitation.
Toggle Bit (I/O )
6
The X28C512/513 also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle, I/O will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
6
3
X28C512/X28C513
DATA Polling I/O
7
Figure 2a. DATA Polling Bus Sequence
LAST
WRITE
WE
CE
OE
V
IH
V
HIGH Z
OH
I/O
7
V
OL
X28C512/513
READY
A –A
0
15
An
An
An
An
An
An
An
3856 FHD F07.1
Figure 2b. DATA Polling Software Flow
DATA Polling can effectively halve the time for writing to
the X28C512/513. The timing diagram in Figure 2a
illustrates the sequence of events on the bus. The
softwareflowdiagraminFigure2billustratesonemethod
of implementing the routine.
WRITE DATA
NO
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
NO
7
COMPARE?
YES
X28C512
READY
3856 FHD F08
4
X28C512/X28C513
The Toggle Bit I/O
6
Figure 3a. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
V
OH
HIGH Z
I/O
6
*
*
V
OL
X28C512/513
READY
3856 FHD F09.1
* Beginning and ending state of I/O will vary.
6
Figure 3b. Toggle Bit Software Flow
TheToggleBitcaneliminatethesoftwarehousekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C512/513 memories that is frequently up-
dated. Toggle Bit Polling can also provide a method for
status checking in multiprocessor applications. The
timing diagram in Figure 3a illustrates the sequence of
events on the bus. The software flow diagram in Figure
3b illustrates a method for polling the Toggle Bit.
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
NO
COMPARE
OK?
YES
X28C512
READY
3856 FHD F10
5
X28C512/X28C513
HARDWARE DATA PROTECTION
The X28C512/513 can be automatically protected dur-
ing power-up and power-down without the need for
external circuits by employing the software data protec-
tion feature. The internal software data protection circuit
is enabled after the first write operation utilizing the
software algorithm. This circuit is nonvolatile and will
remain set for the life of the device unless the reset
command is issued.
The X28C512/513 provides three hardware features
that protect nonvolatile data from inadvertent writes.
• Noise Protection—A WE pulse typically less than
10ns will not initiate a write cycle.
• Default V Sense—All write functions are inhibited
CC
when V is ≤3.6V.
CC
• Write Inhibit—Holding either OE LOW, WE HIGH,
or CE HIGH will prevent an inadvertent write cycle
during power-up and power-down, maintaining data
integrity. Write cycle timing specifications must be
observed concurrently.
Once the software protection is enabled, the X28C512/
513 is also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional data
to the device. Note: The data in the three-byte enable
sequence is not written to the memory array.
SOFTWARE DATA PROTECTION
The X28C512/513 offers a software controlled data
protection feature. The X28C512/513 is shipped from
Xicor with the software data protection NOT ENABLED;
thatis,thedevicewillbeinthestandardoperatingmode.
In this mode data should be protected during power-up/
-down operations through the use of external circuits.
The host would then have open read and write access
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific ad-
dresses. Refer to Figure 4a and 4b for the sequence.
The three byte sequence opens the page write window
enabling the host to write from one to one hundred
twenty-eightbytesofdata.Oncethepageloadcyclehas
been completed, the device will automatically be re-
turned to the data protected state.
of the device once V was stable.
CC
6
X28C512/X28C513
Software Data Protection
Figure 4a. Timing Sequence—Software Data Protect Enable Sequence followed by Byte or Page Write
V
(V
)
CC
0V
CC
DATA
ADDR
AA
5555
55
2AAA
A0
5555
WRITES
OK
t
WC
WRITE
PROTECTED
CE
≤t
BYTE
OR
PAGE
BLC MAX
WE
NOTE: All other timings and control pins are per page write timing requirements.
3856 FHD F11
Figure 4b. Write Sequence for Software Data
Protection
Regardless of whether the device has previously been
protected or not, once the software data protected
algorithm is used and data has been written, the
X28C512/513 will automatically disable further writes
unless another command is issued to cancel it. If no
further commands are issued the X28C512/513 will be
writeprotectedduringpower-downandafteranysubse-
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
quent power-up. The state of A while executing the
15
algorithm is don’t care.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA A0
TO ADDRESS
5555
WRITE DATA XX
TO ANY
ADDRESS
OPTIONAL
BYTE/PAGE
LOAD OPERATION
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER t
RE-ENTERS DATA
WC
PROTECTED STATE
3856 FHD F12
7
X28C512/X28C513
Resetting Software Data Protection
Figure 5a. Reset Software Data Protection Timing Sequence
V
CC
STANDARD
OPERATING
MODE
DATA
AA
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
≥t
WC
ADDR 5555
CE
WE
NOTE: All other timings and control pins are per page write timing requirements.
3856 FHD F13
Figure 5b. Software Sequence to Deactivate
Software Data Protection
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E PROM programmer, the following six step algo-
WRITE DATA AA
TO ADDRESS
5555
2
rithm will reset the internal protection circuit. After t
,
WC
the X28C512/513 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 80
TO ADDRESS
5555
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 20
TO ADDRESS
5555
3856 FHD F14
8
X28C512/X28C513
SYSTEM CONSIDERATIONS
array is of prime concern. Enabling CE will cause
transient current spikes. The magnitude of these spikes
is dependent on the output capacitive loading of the I/
Os. Therefore, the larger the array sharing a common
bus, the larger the transient spikes. The voltage peaks
associated with the current transients can be sup-
pressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recom-
mended that a 0.1µF high frequency ceramic capacitor
be used between V and V at each device. Depend-
Because the X28C512/513 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usagecanprovidethelowestpossiblepowerdissipation
and eliminate the possibility of contention where mul-
tiple I/O pins share the same bus.
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
CC
SS
ing on the size of the array, the value of the capacitor
may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V and V for each
CC
SS
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
Because the X28C512/513 has two power modes,
standby and active, proper decoupling of the memory
Active Supply Current vs. Ambient Temperature
I
(RD) by Temperature over Frequency
CC
70
14
5.0 V
CC
V
= 5V
CC
13
12
11
10
9
60
–55°C
+25°C
50
40
30
20
10
+125°C
8
–55
–10
+35
+80
+125
AMBIENT TEMPERATURE (°C)
3856 ILL F24
3
6
9
12
15
0
FREQUENCY (MHz)
3856 ILL F25
Standby Supply Current vs. Ambient Temperature
0.24
V
= 5V
CC
0.22
0.2
0.18
0.16
0.14
0.12
0.1
–10
+35
+80
+125
–55
AMBIENT TEMPERATURE (°C)
3856 ILL F26
9
X28C512/X28C513
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecificationis
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
X28C512/513............................... –10°C to +85°C
X28C512I/513I........................... –65°C to +135°C
X28C512M/513M....................... –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
....................................... –1V to +7V
SS
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
RECOMMEND OPERATING CONDITIONS
Supply Voltage
Limits
Temperature
Min.
Max.
X28C512/513
5V ±10%
Commercial
Industrial
Military
0°C
+70°C
+85°C
+125°C
3856 PGM T03.1
–40°C
–55°C
3856 PGM T02
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
I
V
Current (Active)
50
mA CE = OE = V , WE = V ,
CC
CC
IL
IH
(TTL Inputs)
All I/O’s = Open, Address Inputs =
.4V/2.4V Levels @ f = 5MHz
I
I
V
Current (Standby)
3
mA CE = V , OE = V
IH IL
SB1
CC
(TTL Inputs)
All I/O’s = Open, Other Inputs = V
IH
V
CC
Current (Standby)
500
µA
CE = V – 0.3V, OE = V
CC IL
SB2
(CMOS Inputs)
All I/O’s = Open, Other Inputs = V
IH
I
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V , CE = V
IH
LO
OUT
SS
CC
(1)
V
V
V
V
–1
2
0.8
lL
(1)
V
+ 1
CC
V
IH
0.4
V
I
I
= 2.1mA
OL
OH
OL
2.4
V
= –400µA
OH
3856 PGM T04.2
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
10
X28C512/X28C513
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(2)
t
t
Power-up to Read Operation
Power-up to Write Operation
100
5
µs
PUR
(2)
ms
PUW
3856 PGM T05
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Parameter
Max.
Units
Test Conditions
(2)
C
C
Input/Output Capacitance
Input Capacitance
10
10
pF
pF
V
V
= 0V
= 0V
I/O
I/O
(2)
IN
IN
3856 PGM T06.1
ENDURANCE AND DATA RETENTION
Parameter
Min.
Max.
Units
Endurance
Endurance
10,000
100,000
100
Cycles Per Byte
Cycles Per Page
Years
Data Retention
3856 PGM T07.1
A.C. CONDITIONS OF TEST
MODE SELECTION
Input Pulse Levels
0V to 3V
CE
L
OE
L
WE
H
Mode
Read
Write
I/O
Power
D
Active
OUT
IN
Input Rise and
Fall Times
L
H
L
D
Active
10ns
1.5V
H
X
X
Standby and
Write Inhibit
High Z
Standby
Input and Output
Timing Levels
3856 PGM T07.1
X
X
L
X
H
Write Inhibit
Write Inhibit
—
—
—
X
—
3856 PGM T08
EQUIVALENT A.C. LOAD CIRCUIT
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
5V
Must be
steady
Will be
steady
1.92KΩ
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
OUTPUT
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
100pF
1.37KΩ
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
3856 FHD F15.3
N/A
Center Line
is High
Impedance
Note: (2) This parameter is periodically sampled and not 100%
tested.
11
X28C512/X28C513
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28C512-90 X28C512-12 X28C512-15 X28C512-20 X28C512-25
X28C513-90 X28C513-12 X28C513-15 X28C513-20 X28C513-25
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t
t
t
t
t
t
t
t
t
Read Cycle Time
90
120
150
200
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
CE
AA
OE
Chip Enable Access Time
Address Access Time
90
90
40
120
120
50
150
150
50
200
200
50
250
250
50
Output Enable Access Time
CE LOW to Active Output
OE LOW to Active Output
CE HIGH to High Z Output
OE HIGH to High Z Output
(3)
0
0
0
0
0
0
0
0
0
0
LZ
(3)
OLZ
(3)
40
40
50
50
50
50
50
50
50
50
HZ
(3)
OHZ
OH
Output Hold from
Address Change
0
0
0
0
0
3856 PGM T09.4
Read Cycle
ADDRESS
CE
t
RC
t
CE
t
OE
OE
V
IH
WE
t
t
OLZ
OHZ
t
t
t
t
LZ
OH
HZ
HIGH Z
DATA I/O
DATA VALID
DATA VALID
AA
3856 FHD F16
Notes: (3) t min., t , t
min., and tOHZ are periodically sampled and not 100% tested. t max. and t
max. are measured, with
OHZ
LZ
HZ OLZ
HZ
C = 5pF from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
L
12
X28C512/X28C513
WRITE CYCLE LIMITS
Symbol
Parameter
Min.
Max.
Units
(4)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery
Data Valid
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
WC
AS
0
50
0
AH
CS
0
CH
100
10
10
100
100
CW
OES
OEH
WP
WPH
DV
1
Data Setup
50
0
DS
Data Hold
DH
Delay to Next Write
Byte Load Cycle
10
0.2
DW
BLC
100
3856 PGM T10.2
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
t
CS
CH
CE
OE
t
t
OEH
OES
t
t
WP
WE
DV
DATA IN
DATA OUT
DATA VALID
DS
t
t
DH
HIGH Z
3856 FHD F17
Notes: (4) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time
WC
the device requires to complete the internal write operation.
13
X28C512/X28C513
CE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
CW
CE
t
WPH
t
OES
OE
t
OEH
t
t
CS
CH
DH
WE
t
DV
DATA IN
DATA VALID
t
t
DS
HIGH Z
DATA OUT
3856 FHD F18
Page Write Cycle
OE(5)
CE
t
t
BLC
WP
WE
t
WPH
*ADDRESS(6)
I/O
LAST BYTE
BYTE n+2
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
t
WC
*For each successive write within the page write operation, A –A should be the same or
15
7
writes to an unknown address could occur.
3856 FHD F19.1
Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH
to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing
a polling operation.
(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform
to either the CE or WE controlled write cycle timing.
14
X28C512/X28C513
(7)
DATA Polling Timing Diagram
A
A
A
ADDRESS
CE
n
n
n
WE
t
t
OEH
OES
OE
t
DW
=X
D
=X
D
=X
D
I/O
7
IN
OUT
OUT
t
WC
3856 FHD F20
Toggle Bit Timing Diagram
CE
WE
t
t
OES
OEH
OE
t
DW
HIGH Z
I/O
6
*
*
t
WC
* Starting and ending state of I/O will vary, depending upon actual t
.
6
WC
3856 FHD F21
Note: (7) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
15
X28C512/X28C513
NOTES
16
X28C512/X28C513
PACKAGING INFORMATION
32-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
1.690 (42.95)
MAX.
0.610 (15.49)
0.500 (12.70)
PIN 1
0.005 (0.13) MIN.
0.100 (2.54) MAX.
SEATING
PLANE
0.232 (5.90) MAX.
0.060 (1.52)
0.015 (0.38)
0.150 (3.81) MIN.
0.200 (5.08)
0.125 (3.18)
0.065 (1.65)
0.023 (0.58)
0.033 (0.84)
TYP. 0.055 (1.40)
0.014 (0.36)
TYP. 0.018 (0.46)
0.110 (2.79)
0.090 (2.29)
TYP. 0.018 (0.46)
0.620 (15.75)
0.590 (14.99)
TYP. 0.614 (15.60)
0°
0.015 (0.38)
0.008 (0.20)
15°
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F09
17
X28C512/X28C513
PACKAGING INFORMATION
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
0.300 (7.62)
BSC
0.150 (3.81) BSC
0.020 (0.51) x 45° REF.
0.015 (0.38)
0.003 (0.08)
0.095 (2.41)
0.075 (1.91)
PIN 1
0.022 (0.56)
DIA.
0.006 (0.15)
0.055 (1.39)
0.200 (5.08)
BSC
0.045 (1.14)
TYP. (4) PLCS.
0.015 (0.38)
MIN.
0.028 (0.71)
0.040 (1.02) x 45° REF.
0.022 (0.56)
(32) PLCS.
TYP. (3) PLCS.
0.050 (1.27) BSC
0.458 (11.63)
0.088 (2.24)
0.050 (1.27)
0.442 (11.22)
0.120 (3.05)
0.458 (11.63)
––
0.060 (1.52)
0.558 (14.17)
––
0.560 (14.22)
0.540 (13.71)
0.400 (10.16)
BSC
PIN 1 INDEX CORNER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
3926 FHD F14
18
X28C512/X28C513
PACKAGING INFORMATION
32-LEAD CERAMIC FLAT PACK TYPE F
0.019 (0.48)
0.015 (0.38)
PIN 1 INDEX
1
32
0.50 (1.27) BSC
0.828 (21.04)
0.812 (20.64)
0.045 (1.14) MAX.
0.005 (0.13) MIN.
0.488
0.130 (3.30)
0.090 (2.29)
0.007 (0.18)
0.004 (0.10)
0.430 (10.93)
0.370 (9.40)
0.270 (6.86)
0.047 (1.19)
0.026 (0.66)
0.347 (8.82)
0.330 (8.38)
0.030 (0.76)
MIN
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F20
19
X28C512/X28C513
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.420 (10.67)
0.050 (1.27) TYP.
0.021 (0.53)
0.013 (0.33)
TYP. 0.017 (0.43)
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.045 (1.14) x 45°
0.015 (0.38)
0.095 (2.41)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
0.060 (1.52)
0.140 (3.56)
0.453 (11.51)
0.100 (2.45)
TYP. 0.136 (3.45)
0.447 (11.35)
TYP. 0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
REF.
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
20
X28C512/X28C513
PACKAGING INFORMATION
36-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K
15
14
11
9
17
16
19
18
21
20
22
23
25
27
29
32
33
A
0.008 (0.20)
13
12
10
8
24
26
0.050 (1.27)
A
28
30
31
NOTE: LEADS 5, 14, 23, & 32
7
TYP. 0.100 (2.54)
ALL LEADS
6
5
2
3
36
1
34
35
0.090 (2.29)
0.070 (1.78)
4
0.090 (2.29)
0.070 (1.78)
0.120 (3.05)
0.100 (2.54)
0.072 (1.83)
0.062 (1.57)
PIN 1 INDEX
0.770 (19.56)
0.750 (19.05)
SQ.
0.020 (0.51)
0.016 (0.41)
A
A
0.185 (4.70)
0.175 (4.45)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F21
21
X28C512/X28C513
PACKAGING INFORMATION
32-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.665 (42.29)
1.644 (41.76)
0.557 (14.15)
0.510 (12.95)
PIN 1 INDEX
PIN 1
0.085 (2.16)
0.040 (1.02)
1.500 (38.10)
REF.
0.160 (4.06)
0.140 (3.56)
SEATING
PLANE
0.030 (0.76)
0.015 (0.38)
0.160 (4.06)
0.125 (3.17)
0.110 (2.79)
0.090 (2.29)
0.070 (17.78)
0.030 (7.62)
0.022 (0.56)
0.014 (0.36)
0.625 (15.88)
0.590 (14.99)
0°
TYP. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F25
22
X28C512/X28C513
PACKAGING INFORMATION
32-LEAD CERAMIC SMALL OUTLINE GULL WING PACKAGE TYPE R
0.060 NOM.
SEE DETAIL “A”
FOR LEAD
INFORMATION
0.020 MIN.
0.165 TYP.
0.035 TYP.
0.340
±0.007
0.015 R TYP.
0.015 R
TYP.
0.035 MIN.
DETAIL “A”
0.050"
TYPICAL
0.0192
0.0138
0.050"
TYPICAL
0.560"
TYPICAL
0.840
MAX.
0.750
±0.005
0.030" TYPICAL
32 PLACES
0.050
FOOTPRINT
0.440 MAX.
0.560 NOM.
NOTES:
1. ALL DIMENSIONS IN INCHES
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3926 FHD F27
23
X28C512/X28C513
PACKAGING INFORMATION
40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T
12.522 (0.493)
12.268 (0.483)
1.143 (0.045)
0.889 (0.035)
0.965
PIN #1 IDENT.
(0.038)
O 1.016 (0.040) 0.127 (0.005) DP.
O 0.762 (0.030) 0.076 (0.003) DP.
X
1.219 (0.048)
0.500 (0.0197)
1
10.058 (0.396)
9.957 (0.392)
0.178 (0.007)
15° TYP.
SEATING
PLANE
0.254 (0.010)
0.152 (0.006)
A
0.065 (0.0025)
1.016 (0.040)
SEATING
PLANE
DETAIL A
0.813 (0.032) TYP.
0.432 (0.017)
14.148 (0.557)
13.894 (0.547)
0.152 (0.006)
TYP.
4° TYP.
0.432 (0.017)
0.508 (0.020) TYP.
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
(0.012 ± 0.002)
SOLDER PADS
TYPICAL
40 PLACES
15 EQ. SPC. @ 0.50 ± 0.04
0.0197 ± 0.016 = 9.50 ± 0.06
(0.374 ± 0.0024) OVERALL
TOL. NON-CUMULATIVE
0.17 (0.007)
0.03 (0.001)
0.50 ± 0.04
(0.0197 ± 0.0016)
1.30 ± 0.05
(0.051 ± 0.002)
FOOTPRINT
NOTE:
3926 ILL F39.2
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
24
X28C512/X28C513
ORDERING INFORMATION
X28C512
X
X
-X
Access Time
–90 = 90ns
Device
–12 = 120ns
–15 = 150ns
–20 = 200ns
–25 = 250ns
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = Mil-STD-883
X28C513
X
X
-X
Package
D = 32-Lead CerDip
E = 32-Pad LCC
Access Time
–90 = 90ns
–12 = 120ns
–15 = 150ns
–20 = 200ns
–25 = 250ns
Device
F = 32-Lead Flat Pack
J = 32-Lead PLCC
K = 36-Lead Pin Grid Array
P = 32-Lead Plastic Dip
R = 32-Lead Ceramic SOIC
T = 40-Lead TSOP
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = Mil-STD-883
Package
E = 32-Pad LCC
J = 32-Lead PLCC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475;4,450,402;4,486,769;4,488,060;4,520,461;4,533,846;4,599,706;4,617,652;4,668,932;4,752,912;4,829,482;4,874,967;4,883,976.
Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. Acriticalcomponentisanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocausethefailure
of the life support device or system, or to affect its satety or effectiveness.
25
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