X28HC64 [XICOR]
5 Volt, Byte Alterable E2PROM; 5伏，可变的字节E2PROM
| 型号： | X28HC64 |
| 厂家： | 
XICOR INC. |
| 描述： | 5 Volt, Byte Alterable E2PROM |
| 文件： | 总24页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
64K
X28HC64
8K x 8 Bit
5 Volt, Byte Alterable E2PROM
FEATURES
• High Reliability
—Endurance: 100,000 Cycles
• 55ns Access Time
• Simple Byte and Page Write
—Single 5V Supply
—Data Retention: 100 Years
• JEDEC Approved Byte-Wide Pinout
—No External High Voltages or VPP Control
Circuits
—Self-Timed
DESCRIPTION
The X28HC64 is an 8K x 8 E2PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatilememoriestheX28HC64isa5Vonlydevice. The
X28HC64featurestheJEDECapprovedpinoutforbyte-
widememories,compatiblewithindustrystandardRAMs.
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS
—40 mA Active Current Max.
—200 µA Standby Current Max.
• Fast Write Cycle Times
—64 Byte Page Write Operation
—Byte or Page Write Cycle: 2ms Typical
—Complete Memory Rewrite: 0.25 sec. Typical
—Effective Byte Write Cycle Time: 32µs Typical
• Software Data Protection
• End of Write Detection
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle and en-
abling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features DATA Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Xicor’s hardware write protect capability.
—DATA Polling
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
—Toggle Bit
TSOP
PIN CONFIGURATIONS
A
A
A
I/O
I/O
I/O
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
A
A
A
A
NC
NC
V
NC
WE
NC
A
A
A
2
1
0
0
1
2
3
4
5
6
7
12
PLASTIC DIP
LCC
FLAT PACK
PLCC
NC
CERDIP
SOIC
V
SS
NC
I/O
I/O
I/O
I/O
I/O
X28HC64
9
CC
10
11
12
13
14
15
16
3
4
5
6
7
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
4
3
2
1
32 31 30
29
CC
A
2
WE
8
9
11
12
A
A
A
A
A
A
A
5
6
7
8
9
A
A
A
6
5
4
3
2
1
0
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
3
NC
28
27
26
25
24
23
22
21
CE
9
A
OE
10
4
A
8
A
9
11
5
NC
OE
A
3857 ILL F22
X28HC64
PGA
6
A
11
10
11
12
13
7
OE
10
I/O
12
I/O
13
I/O
15
I/O
17
I/O
18
1
2
3
5
6
X28HC64
CE
8
A
10
NC
I/O
I/O
7
I/O
11
A
10
V
14
I/O
16
I/O
19
9
CE
0
0
SS
4
7
I/O
0
6
10
11
12
13
14
I/O
7
I/O
6
I/O
5
I/0
4
14 15 16 17 18 19 20
A
A
A
8
CE
20
A
21
1
3
2
4
10
11
I/O
0
1
2
9
7
I/O
I/O
V
X28HC64
A
6
OE
22
A
23
3857 FHD F03
I/O
3
A
A
V
28
A
24
A
25
SS
5
6
12
7
CC
9
8
5
4
2
3
3857 FHD F02.1
A
A
NC
1
WE
27
NC
26
3857 FHD F04
BOTTOM VIEW
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
3857-3.0 8/5/97 T1/C0/D0 EW
Characteristics subject to change without notice
1
X28HC64
PIN DESCRIPTIONS
Addresses (A0–A12)
PIN NAMES
Symbol
A –A
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
The Address inputs select an 8-bit memory location
during a read or write operation.
0
12
I/O –I/O
0
7
WE
CE
OE
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
writeoperations.WhenCEisHIGH,powerconsumption
is reduced.
V
CC
V
SS
Ground
Output Enable (OE)
NC
No Connect
TheOutputEnableinputcontrolsthedataoutputbuffers
and is used to initiate read operations.
3857 PGM T01
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28HC64 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC64.
FUNCTIONAL DIAGRAM
65,536-BIT
2
E PROM
X BUFFERS
LATCHES AND
DECODER
ARRAY
A –A
0
12
ADDRESS
INPUTS
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
I/O –I/O
0
7
DATA INPUTS/OUTPUTS
CE
OE
WE
CONTROL
LOGIC AND
TIMING
V
CC
V
3857 FHD F01
SS
2
X28HC64
DEVICE OPERATION
Read
Write Operation Status Bits
The X28HC64 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
natesbuscontentioninasystemenvironment. Thedata
bus will be in a high impedance state when either OE or
CE is HIGH.
Figure 1. Status Bit Assignment
Write
I/O DP TB
5
4
3
2
1
0
Write operations are initiated when bothCE and WE are
LOW and OE is HIGH. The X28HC64 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE, which-
ever occurs first. A byte write operation, once initiated,
willautomaticallycontinuetocompletion,typicallywithin
2ms.
RESERVED
TOGGLE BIT
DATA POLLING
3857 FHD F11
DATA Polling (I/O7)
The X28HC64 features DATA Polling as a method to
indicate to the host system that the byte write or page
writecyclehascompleted.DATAPollingallowsasimple
bittestoperationtodeterminethestatusoftheX28HC64,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
complement of that data on I/O7 (i.e. write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O7 will reflect true data.
Page Write Operation
The page write feature of the X28HC64 allows the entire
memorytobewrittenin0.25seconds. Pagewriteallows
twotosixty-fourbytesofdatatobeconsecutivelywritten
to the X28HC64 prior to the commencement of the
internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A6 through A12) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.
Toggle Bit (I/O6)
The X28HC64 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle I/O6 will toggle from
HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to sixty-three bytes in the
samemannerasthefirstbytewaswritten. Eachsucces-
sive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of
the preceding WE. If a subsequent WE HIGH to LOW
transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continuestoaccessthedevicewithinthebyteloadcycle
time of 100µs.
3
X28HC64
DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
LAST
WRITE
WE
CE
OE
V
IH
V
HIGH Z
OH
I/O
7
V
OL
X28HC64
READY
A –A
0
12
An
An
An
An
An
An
An
3857 FHD F12
Figure 3. DATA Polling Software Flow
DATA Polling can effectively reduce the time for writing
to the X28HC64. The timing diagram in Figure 2 illus-
trates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
WRITE DATA
NO
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
NO
7
COMPARE?
YES
READY
3857 FHD F13
4
X28HC64
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
V
OH
HIGH Z
I/O
6
*
*
V
OL
X28HC64
READY
* Beginning and ending state of I/O will vary.
6
3857 FHD F14
Figure 5. Toggle Bit Software Flow
TheToggleBitcaneliminatethesoftwarehousekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28HC64 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagraminFigure4illustratesthesequenceofeventson
thebus. ThesoftwareflowdiagraminFigure5illustrates
a method for polling the Toggle Bit.
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
NO
COMPARE
OK?
YES
READY
3857 FHD F15
5
X28HC64
HARDWARE DATA PROTECTION
ture. The internal software data protection circuit is
enabled after the first write operation utilizing the soft-
warealgorithm. Thiscircuitisnonvolatileandwillremain
set for the life of the device unless the reset command
is issued.
The X28HC64 provides two hardware features that
protect nonvolatile data from inadvertent writes.
• Default VCC Sense—All write functions are inhibited
when VCC is ≤3V typically.
• Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGHwillpreventaninadvertentwritecycleduring
power-up and power-down, maintaining data integrity.
Once the software protection is enabled, the X28HC64
is also protected from inadvertent and accidental writes
in the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
SOFTWARE DATA PROTECTION
The X28HC64 offers a software controlled data protec-
tion feature. The X28HC64 is shipped from Xicor with
thesoftwaredataprotectionNOTENABLED;thatis, the
device will be in the standard operating mode. In this
mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the
device once VCC was stable.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific ad-
dresses. Refer to Figure 6 and 7 for the sequence. The
three-byte sequence opens the page write window
enabling the host to write from one to sixty-four bytes of
data. Oncethepageloadcyclehasbeencompleted, the
device will automatically be returned to the data pro-
tected state.
The X28HC64 can be automatically protected during
power-upandpower-downwithouttheneedforexternal
circuits by employing the software data protection fea-
6
X28HC64
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
V
(V
)
CC
CC
0V
AA
1555
55
0AAA
A0
1555
WRITES
OK
WRITE
PROTECTED
DATA
ADDR
t
WC
CE
≤t
BYTE
OR
PAGE
BLC MAX
WE
3857 FHD F16
Figure 7. Write Sequence for
Software Data Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used, the X28HC64 will automatically dis-
able further writes unless another command is issued to
deactivate it. If no further commands are issued the
X28HC64 will be write protected during power-down
and after any subsequent power-up.
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
Note: Onceinitiated,thesequenceofwriteoperations
should not be interrupted.
WRITE DATA A0
TO ADDRESS
1555
BYTE/PAGE
LOAD ENABLED
WRITE DATA XX
TO ANY
ADDRESS
OPTIONAL BYTE
OR PAGE WRITE
ALLOWED
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER t
RE-ENTERS DATA
WC
PROTECTED STATE
3857 FHD F17
7
X28HC64
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
Vcc
STANDARD
OPERATING
MODE
DATA AA
ADDR 1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
≥t
WC
CE
WE
3857 ILL F18.2
Figure 9. Software Sequence to
Deactivate Software Data Protection
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E2PROM programmer, the following six step algo-
WRITE DATA AA
TO ADDRESS
1555
rithm will reset the internal protection circuit. After tWC
,
the X28HC64 will be in standard operating mode.
Note: Onceinitiated,thesequenceofwriteoperations
should not be interrupted.
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 80
TO ADDRESS
1555
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 20
TO ADDRESS
1555
3857 ILL F19.2
8
X28HC64
SYSTEM CONSIDERATIONS
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high fre-
quency ceramic capacitor be used between VCC and
VSS at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
BecausetheX28HC64isfrequentlyusedinlargememory
arrays, it is provided with a two line control architecture
for both read and write operations. Proper usage can
provide the lowest possible power dissipation and elimi-
nate the possibility of contention where multiple I/O pins
share the same bus.
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
Because the X28HC64 has two power modes, standby
and active, proper decoupling of the memory array is of
Normalized ICC(RD) by Temperature
Over Frequency
Normalized ICC(RD) @ 25% Over
the VCC Range and Frequency
1.4
1.4
5.5 V
CC
- 55°C
1.2
5.5 V
5.0 V
1.2
1.0
0.8
0.6
0.4
0.2
CC
CC
+ 25°C
1.0
+ 125°C
4.5 V
CC
0.8
0.6
0.4
0.2
0
10
20
0
10
20
FREQUENCY (MHz)
FREQUENCY (MHz)
3857 FHD F20.1
3857 FHD F21.1
9
X28HC64
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecificationis
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
X28HC64 ..................................... –10°C to +85°C
X28HC64I, X28HC64M ............. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
....................................... –1V to +7V
SS
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
Industrial
Military
0°C
+70°C
+85°C
+125°C
X28HC64
5V ±10%
3857 PGM T03.1
–40°C
–55°C
3857 PGM T02.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
(1)
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
CE = OE = V , WE = V , All
I
V
Current (Active)
15
40
mA
CC
CC
IL
IH
(TTL Inputs)
I/O’s = Open, Address Inputs =
TTL Levels @ f = 10 MHz
I
I
V
Current (Standby)
1
2
mA
CE = V , OE = V
IH IL
All I/O’s = Open, Other Inputs = V
SB1
CC
(TTL Inputs)
IH
V
CC
Current (Standby)
100
200
µA
CE = V – 0.3V, OE = GND
SB2
CC
(CMOS Inputs)
All I/O’s = Open, Other Inputs =
V
V
V
– 0.3V
CC
I
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
±10
±10
0.8
µA
µA
V
= V to V
SS CC
LI
IN
= V to V , CE = V
IH
LO
OUT
SS
CC
(2)
V
V
V
V
–1
2
lL
(2)
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
+ 1
V
IH
CC
0.4
V
I = 5mA
OL
OL
OH
2.4
V
I = –5mA
OH
3857 PGM T04.2
Notes: (1) Typical values are for T = 25°C and nominal supply voltage
A
(2) V min. and V max. are for reference only and are not tested.
IL IH
10
X28HC64
ENDURANCE AND DATA RETENTION
Parameter
Min.
Max.
Unit
Minimum Endurance
Data Retention
100,000
100
Cycles
Years
3857 PGM T05.3
POWER-UP TIMING
(1)
Symbol
Parameter
Typ.
Units
(3)
t
t
Power-up to Read Operation
Power-up to Write Operation
100
µs
PUR
(3)
5
ms
PUW
3857 PGM T06
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
Parameter
Max.
Units
Test Conditions
(3)
C
C
Input/Output Capacitance
Input Capacitance
10
6
pF
pF
V
V
= 0V
= 0V
I/O
I/O
(3)
IN
IN
3857 PGM T07.1
A.C. CONDITIONS OF TEST
MODE SELECTION
Input Pulse Levels
0V to 3V
CE
L
OE
L
WE
H
Mode
Read
I/O
Power
Active
D
D
OUT
IN
Input Rise and
Fall Times
L
H
L
Write
Active
5ns
H
X
X
Standby and
Write Inhibit
High Z
Standby
Input and Output
Timing Levels
1.5V
3857 PGM T08.1
X
X
L
X
H
Write Inhibit
Write Inhibit
—
—
—
X
—
3857 PGM T09
Note: (3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUITS
SYMBOL TABLE
5V
WAVEFORM
INPUTS
OUTPUTS
1.92KΩ
Must be
steady
Will be
steady
OUTPUT
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
1.37KΩ
30pF
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
3857 FHD F22.3
N/A
Center Line
is High
Impedance
11
X28HC64
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Read Cycle Limits
X28HC64-70 X28HC64-90 X28HC64-12
–55°Cto+125°C –55°Cto+125°C –55°Cto+125°C
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Units
t
t
t
t
t
t
t
t
t
Read Cycle Time
70
90
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
CE
AA
OE
Chip Enable Access Time
Address Access Time
70
70
35
90
90
40
120
120
50
Output Enable Access Time
CE LOW to Active Output
OE LOW to Active Output
CE HIGH to High Z Output
OE HIGH to High Z Output
(4)
0
0
0
0
0
0
LZ
(4)
OLZ
(4)
30
30
30
30
30
30
HZ
(4)
OHZ
OH
Output Hold from
Address Change
0
0
0
3857 PGM T10.1
Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
WE
t
t
OLZ
OHZ
t
t
t
LZ
OH
HZ
HIGH Z
DATA I/O
DATA VALID
DATA VALID
t
AA
3857 FHD F05
Notes: (4) t min., t , t
LZ HZ OLZ
min., and t
are periodically sampled and not 100% tested. t max. and t
HZ
max. are measured from the
OHZ
OHZ
point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
12
X28HC64
WRITE CYCLE LIMITS
(1)
Symbol
Parameter
Min.
Typ.
Max.
Units
(5)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery
Data Valid
2
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
WC
AS
0
50
0
AH
CS
0
CH
50
0
CW
OES
OEH
WP
WPH
0
50
50
(6)
(6)
1
DV
DS
Data Setup
50
0
Data Hold
DH
(6)
Delay to Next Write
Byte Load Cycle
10
DW
0.15
100
µs
BLC
3857 PGM T11.2
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AS
AH
t
t
CS
CH
CE
OE
t
t
OES
t
OEH
t
WP
WE
DV
DATA IN
DATA OUT
DATA VALID
DS
t
t
DH
HIGH Z
3857 FHD F06
Notes: (5) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WC
time the device requires to automatically complete the internal write operation.
(6) t
and t
are periodically sampled and not 100% tested.
WPH
DW
13
X28HC64
CE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
CW
CE
t
OES
OE
t
OEH
t
t
CH
CS
WE
t
DV
DATA IN
DATA VALID
t
t
DH
DS
HIGH Z
DATA OUT
3857 FHD F07
Page Write Cycle
OE(7)
CE
WE
t
t
BLC
WP
t
WPH
ADDRESS *(8)
I/O
LAST BYTE
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
BYTE n+2
t
WC
*For each successive write within the page write operation, A –A should be the same or
12
6
writes to an unknown address could occur.
3857 FHD F08
Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively
performing a polling operation.
(8) The timings shown above are unique to page write operations. Individual byte load operations within the page write must
conform to either the CE or WE controlled write cycle timing.
14
X28HC64
(9)
DATA Polling Timing Diagram
ADDRESS
CE
An
An
An
WE
t
t
OEH
OES
OE
t
DW
=X
D
=X
D
=X
D
I/O
7
IN
OUT
OUT
t
WC
3857 FHD F09
(9)
Toggle Bit Timing Diagram
CE
WE
t
t
OES
OEH
OE
t
DW
HIGH Z
I/O
6
*
*
t
WC
* I/O beginning and ending state will vary, depending upon actual t
.
6
WC
3857 FHD F10
Note: (9) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
15
X28HC64
PACKAGING INFORMATION
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.460 (37.08)
1.400 (35.56)
0.550 (13.97)
0.510 (12.95)
PIN 1 INDEX
PIN 1
0.085 (2.16)
0.040 (1.02)
1.300 (33.02)
REF.
0.160 (4.06)
0.125 (3.17)
SEATING
PLANE
0.030 (0.76)
0.015 (0.38)
0.150 (3.81)
0.125 (3.17)
0.110 (2.79)
0.090 (2.29)
0.062 (1.57)
0.050 (1.27)
0.020 (0.51)
0.016 (0.41)
0.610 (15.49)
0.590 (14.99)
0°
15°
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F04
16
X28HC64
PACKAGING INFORMATION
28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
1.490 (37.85)
1.435 (36.45)
0.610 (15.49)
0.500 (12.70)
PIN 1
0.100 (2.54)
0.035 (0.89)
1.30 (33.02)
REF.
0.225 (5.72)
0.140 (3.56)
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.070 (1.78)
0.030 (0.76)
0.026 (0.66)
0.014 (0.36)
TYP. 0.100 (2.54)
TYP. 0.055 (1.40)
TYP. 0.018 (0.46)
0.620 (15.75)
0.590 (14.99)
TYP. 0.614 (15.60)
0°
15°
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F08
17
X28HC64
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.420 (10.67)
0.050 (1.27) TYP.
0.021 (0.53)
0.013 (0.33)
TYP. 0.017 (0.43)
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.045 (1.14) x 45°
0.015 (0.38)
0.095 (2.41)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
0.060 (1.52)
0.140 (3.56)
0.453 (11.51)
0.100 (2.45)
TYP. 0.136 (3.45)
0.447 (11.35)
TYP. 0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
REF.
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
18
X28HC64
PACKAGING INFORMATION
28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.2980 (7.5692) 0.4160 (10.5664)
0.2920 (7.4168) 0.3980 (10.1092)
0.0192 (0.4877)
0.0138 (0.3505)
0.7080 (17.9832)
0.7020 (17.8308)
0.1040 (2.6416)
0.0940 (2.3876)
BASE PLANE
SEATING PLANE
0.0110 (0.2794)
0.050 (1.270)
BSC
0.0040 (0.1016)
0.0160 (0.4064)
0.0100 (0.2540)
X 45°
0.0125 (0.3175)
0.0090 (0.2311)
0° – 8°
0.0350 (0.8890)
0.0160 (0.4064)
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3. BACK EJECTOR PIN MARKED “KOREA”
4. CONTROLLING DIMENSION: INCHES (MM)
3926 FHD F17
19
X28HC64
PACKAGING INFORMATION
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
0.150 (3.81) BSC
0.020 (0.51) x 45° REF.
0.095 (2.41)
0.075 (1.91)
PIN 1
0.022 (0.56)
0.006 (0.15)
0.055 (1.39)
0.200 (5.08)
BSC
0.045 (1.14)
TYP. (4) PLCS.
0.028 (0.71)
0.040 (1.02) x 45° REF.
0.022 (0.56)
(32) PLCS.
TYP. (3) PLCS.
0.050 (1.27) BSC
0.458 (11.63)
0.442 (11.22)
0.088 (2.24)
0.050 (1.27)
0.458 (11.63)
––
0.300 (7.62)
BSC
0.120 (3.05)
0.060 (1.52)
0.560 (14.22)
0.540 (13.71)
0.558 (14.17)
––
0.400 (10.16)
BSC
PIN 1 INDEX CORDER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
3926 FHD F14
20
X28HC64
PACKAGING INFORMATION
28-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K
12
11
13
10
15
14
17
16
18
19
A
A
0.008
9
7
5
4
8
6
2
3
20
22
24
27
21
23
25
26
0.050
28
1
NOTE: LEADS 4,12,18 & 26
0.080
0.070
TYP. 0.100
ALL LEADS
4 CORNERS
0.080
0.070
0.100
0.080
0.072
0.061
PIN 1 INDEX
0.020
0.016
0.660 (16.76)
0.640 (16.26)
A
A
0.185 (4.70)
0.175 (4.44)
0.561 (14.25)
0.541 (13.75)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F15
21
X28HC64
PACKAGING INFORMATION
28-LEAD CERAMIC FLAT PACK
0.019 (0.48)
0.015 (0.38)
PIN 1 INDEX
1
28
0.050 (1.27) BSC
0.740 (18.80)
MAX.
0.045 (1.14) MAX.
0.440 (11.18)
MAX.
0.130 (3.30)
0.090 (2.29)
0.006 (0.15)
0.003 (0.08)
0.370 (9.40)
0.250 (6.35)
0.045 (1.14)
0.025 (0.66)
TYP. 0.300 2 PLCS.
0.180 (4.57)
MIN.
0.030 (0.76)
MIN.
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F16
22
X28HC64
PACKAGING INFORMATION
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T
SEE NOTE 2
12.50 (0.492)
12.30 (0.484)
PIN #1 IDENT.
O 0.76 (0.03)
0.50 (0.0197) BSC
SEE NOTE 2
8.02 (0.315)
7.98 (0.314)
0.26 (0.010)
0.14 (0.006)
1.18 (0.046)
1.02 (0.040)
0.17 (0.007)
0.03 (0.001)
SEATING
PLANE
0.58 (0.023)
0.42 (0.017)
14.15 (0.557)
13.83 (0.544)
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
(0.012 ± 0.002)
SOLDER PADS
TYPICAL
32 PLACES
15 EQ. SPC. 0.50 ± 0.04
0.0197 ± 0.016 = 7.50 ± 0.06
(0.295 ± 0.0024) OVERALL
TOL. NON-CUMULATIVE
0.17 (0.007)
0.03 (0.001)
0.50 ± 0.04
(0.0197 ± 0.0016)
1.30 ± 0.05
(0.051 ± 0.002)
FOOTPRINT
NOTE:
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
3926 ILL F38.1
23
X28HC64
ORDERING INFORMATION
X28HC64
X
X
-X
Access Time
–55 = 55ns
–70 = 70ns
–90 = 90ns
–12 = 120ns
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
P = 28-Lead Plastic DIP
D = 28-Lead Cerdip
J = 32-Lead PLCC
S = 28-Lead Plastic SOIC
E = 32-Pad LCC
K = 28-Lead Pin Grid Array
F = 28-Lead Flat Pack
T = 32-Lead TSOP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967;
4,883,976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. Acriticalcomponentisanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocausethefailure
of the life support device or system, or to affect its satety or effectiveness.
24
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