X28LV010JI-12T1 [XICOR]
EEPROM, 128KX8, 120ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32;
| 型号： | X28LV010JI-12T1 |
| 厂家： | 
XICOR INC. |
| 描述： | EEPROM, 128KX8, 120ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总18页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1M
128K x 8 Bit
X28LV010
3.3 Volt, Byte Alterable E2PROM
DESCRIPTION
FEATURES
• Access Time: 70, 90, 120, 150ns
• Simple Byte and Page Write
—Single 3.3V±10% supply
The Xicor X28LV010 is a 128K x 8 E2PROM, fabri-
cated with Xicor's proprietary, high performance, float-
ing gate CMOS technology. Like all Xicor
programmable non-volatile memories the X28LV010
requires a single voltage supply. The X28LV010 fea-
tures the JEDEC approved pinout for byte-wide memo-
ries, compatible with industry standard EPROMs.
—No external high voltages or V control circuits
PP
—Self-timed
• no erase before write
• no complex programming algorithms
• no overerase problem
• Low Power CMOS
—Active: 20mA
—Standby: 20µA
• Software Data Protection
—Protects data against system level inadvertant
writes
• High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
—Endurance: 100,000 write cycles
—Data retention: 100Years
• Early End of Write Detection
—DATA polling
The X28LV010 supports a 256-byte page write opera-
tion, effectively providing a 12µs/byte write cycle and
enabling the entire memory to be typically written in
less than 2.5 seconds. The X28LV010 also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion
of a write cycle. In addition, the X28LV010 supports
Software Data Protection option.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Data retention is
specified to be greater than 100 years.
—Toggle bit polling
BLOCK DIAGRAM
1M-Bit
E2PROM
Array
X Buffers
Latches and
Decoder
A –A
8
16
I/O Buffers
and Latches
Y Buffers
Latches and
Decoder
A –A
0
7
I/O –I/O
0
7
Data Inputs/Outputs
CE
OE
WE
Control
Logic and
Timing
V
CC
SS
V
Xicor, Inc. 2000 Patents Pending
2000-4003 9/6/00 EP
Characteristics subject to change without notice. 1 of 18
X28LV010
PIN CONFIGURATIONS
PDIP
PLCC
TSOP
X28LV010
X28LV010
NC
1
2
3
32
31
30
V
CC
WE
NC
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
A
A
A
A
OE
10
11
9
30
29
A
A
16
15
A
4 3
2
32 31
A
A
A
5
6
7
A
A
A
A
A
7
6
5
14
13
8
CE
I/O
1
8
13
28
27
26
25
24
23
22
A
4
5
6
29
28
27
A
7
12
14
I/O
I/O
I/O
I/O
A
A
14
6
5
4
3
7
6
13
A
A
A
A
A
8
9
4
3
2
1
0
9
NC
NC
NC
A
A
8
X28LV010
(Top View)
11
A
A
7
8
26
25
A
A
5
4
9
10
11
OE
A
11
9
WE
NC
NC
V
10
A
A
9
24
23
22
21
20
19
18
17
OE
3
2
1
0
0
V
10
11
12
13
14
15
16
17
18
19
20
CC
NC
NC
NC
12
13
CE
10
11
12
13
14
15
16
A
10
SS
I/O
I/O
7
0
15 1617 18 1920
A
CE
21
NC
NC
I/O
14
A
I/O
7
A
A
A
16
15
12
I/O
I/O
I/O
2
6
I/O
I/O
1
0
I/O
I/O
I/O
1
2
5
4
3
I/O
A
A
A
1
7
6
0
V
SS
A
A
A
A
A
5
4
2
3
PIN DESCRIPTIONS
Addresses (A –A )
PIN NAMES
Symbol
A –A
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+3.3V
0
16
0
16
The Address inputs select an 8-bit memory location
during a read or write operation.
I/O –I/O
0
7
WE
CE
OE
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power con-
sumption is reduced.
V
CC
V
Ground
SS
Output Enable (OE)
NC
No Connect
The Output Enable input controls the data output buff-
ers and is used to initiate read operations.
DEVICE OPERATION
Read
Data In/Data Out (I/O –I/O )
0
7
Data is written to or read from the X28LV010 through
the I/O pins.
Read operations are initiated by both OE and CE
LOW. The read operation is terminated by either CE or
OE returning HIGH. This two line control architecture
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE or CE is HIGH.
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28LV010.
Characteristics subject to change without notice. 2 of 18
X28LV010
Write
Figure 1. Status Bit Assignment
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28LV010 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 5ms.
I/O DP TB
5
4
3
2
1
0
Reserved
Toggle Bit
DATA Polling
DATA Polling (I/O7)
The X28LV010 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a sim-
ple bit test operation to determine the status of the
X28LV010, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
Page Write Operation
The page write feature of the X28LV010 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to two hundred fifty-six bytes of data to be
consecutively written to the X28LV010 prior to the
commencement of the internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the
duce the complement of that data on I/O (i.e., write
7
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
source address), but the page address (A through
programming cycle is complete, I/O will reflect true
8
7
A ) for each subsequent valid write cycle to the part
data. Note: If the X28LV010 is in the protected state
and an illegal write operation is attempted DATA Polling
will not operate.
16
during this operation must be the same as the initial
page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty five
bytes in the same manner as the first byte was written.
Each successive byte load cycle, started by the WE
HIGH to LOW transition, must begin within 100µs of
the falling edge of the preceding WE. If a subsequent
WE HIGH to LOW transition is not detected within
100µs, the internal automatic programming cycle will
commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100µs.
Toggle Bit (I/O )
6
The X28LV010 also provides another method for deter-
mining when the internal write cycle is complete. Dur-
ing the internal programming cycle, I/O will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
6
Write Operation Status Bits
The X28LV010 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Characteristics subject to change without notice. 3 of 18
X28LV010
DATA Polling I/O
7
Figure 2. DATA Polling Bus Sequence
Last
Write
WE
CE
OE
V
IH
V
High Z
OH
I/O
7
V
OL
X28LV010
Ready
A –A
0
14
An
An
An
An
An
An
An
Figure 3. DATA Polling Software Flow
DATA Polling can effectively halve the time for writing to
the X28LV010. The timing diagram in Figure 2 illus-
trates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implement-ing the routine.
Write Data
NO
Writes
Complete?
YES
Save Last Data
and Address
Read Last
Address
IO
7
NO
Compare?
YES
X28LV010
Ready
Characteristics subject to change without notice. 4 of 18
X28LV010
The Toggle Bit I/O
6
Figure 4. Toggle Bit Bus Sequence
Last
Write
WE
CE
OE
V
OH
High Z
I/O
6
V
OL
X28LV010
Ready
Figure 5. Toggle Bit Software Flow
prised of multiple X28LV010 memories that is fre-
quently updated. Toggle Bit Polling can also provide a
method for status checking in multiprocessor applica-
tions. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow dia-
gram in Figure 5 illustrates a method for polling the
Toggle Bit.
Last Write
Load ACCUM
from ADDR n
HARDWARE DATA PROTECTION
The X28LV010 provides three hardware features that
protect nonvolatile data from inadvertent writes.
Compare
ACCUM with
ADDR n
– Noise Protection—A WE pulse less than 10ns will
not initiate a write cycle.
– Default V Sense—All functions are inhibited when
CC
V
is ≤ 2.5V.
CC
NO
Compare
OK?
– Write inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle dur-
ing power-up and power-down, maintaining data
integrity.
YES
SOFTWARE DATA PROTECTION
Ready
The X28LV010 offers a software controlled data pro-
tection feature. The X28LV010 is shipped from Xicor
with the software data protection NOT ENABLED: that
is the device will be in the standard operating mode. In
this mode data should be protected during power-up/
-down operations through the use of external circuits.
The host would then have open read and write access
The Toggle Bit can eliminate the software housekeep-
ing chore of saving and fetching the last address and
data written to a device in order to implement DATA
Polling. This can be especially helpful in an array com-
of the device once V was stable.
CC
Characteristics subject to change without notice. 5 of 18
X28LV010
The X28LV010 can be automatically protected during
power-up and power-down without the need for exter-
nal circuits by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation utilizing the soft-
ware algorithm. This circuit is nonvolatile and will
remain set for the life of the device unless the reset
command is issued.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific
addresses. Refer to Figures 6 and 7 for the sequence.
The three byte sequence opens the page write window
enabling the host to write from one to two hundred fifty-
six bytes of data. Once the page load cycle has been
completed, the device will automatically be returned to
the data protected state.
Once the software protection is enabled, the X28LV010
is also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional
data to the device.
Software Data Protection
Figure 6. Timing Sequence—Byte or Page Write
V
CC
(V
)
CC
0V
Data
ADDR
AA
5555
55
2AAA
A0
5555
t
Write
Protected
WC
Writes
OK
CE
≤ t
Byte
or
Page
BLC MAX
WE
Characteristics subject to change without notice. 6 of 18
X28LV010
Figure 7. Write Sequence for Software Data
Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the
X28LV010 will automatically disable further writes
unless another command is issued to cancel it. If no
further commands are issued the X28LV010 will be
write protected during power-down and after any sub-
sequent power-up. The state of A15 and A16 while exe-
cuting the algorithm is don’t care.
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Data A0
to Address
5555
Write Data XX
to any
Address
Optional
Byte/Page
Load Operation
Write Last
Byte to
Last Address
After t
WC
Re-Enters Data
Protected State
Resetting Software Data Protection
Figure 8. Reset Software Data Protection Timing Sequence
V
CC
Data
AA
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
Standard
Operating
Mode
≥ t
ADDR 5555
WC
CE
WE
Characteristics subject to change without notice. 7 of 18
X28LV010
Figure 9. Software Sequence to Deactivate
Software Data Protection
SYSTEM CONSIDERATIONS
Because the X28LV010 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipa-
tion and eliminate the possibility of contention where
multiple I/O pins share the same bus.
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the pri-
mary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
Write Data 80
to Address
5555
Because the X28LV010 has two power modes,
standby and active, proper decoupling of the memory
array is of prime concern. Enabling CE will cause tran-
sient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the I/Os.
Therefore, the larger the array sharing a common bus,
the larger the transient spikes. The voltage peaks
associated with the current transients can be sup-
pressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recom-
mended that a 0.1µF high frequency ceramic capacitor
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Write Data 20
to Address
5555
be used between V
and V
at each device.
CC
SS
Depending on the size of the array, the value of the
capacitor may have to be larger.
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E2PROM programmer, the following six step algo-
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V
and V for
CC
SS
each eight devices employed in the array. This bulk
capacitor is employed to overcome the voltage drop
caused by the inductive effects of the PC board traces.
rithm will reset the internal protection circuit. After t
the X28LV010 will be in standard operating mode.
,
WC
Note: Once initiated, the sequence of write operations
should not be interrupted.
Characteristics subject to change without notice. 8 of 18
X28LV010
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
indicated in the operational sections of this specifica-
tion) is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect device
reliability.
X28LV010 ....................................... –10°C to +85°C
X28LV010I .................................... –65°C to +135°C
Storage temperature ........................ –65°C to +150°C
Voltage on any input pins (including
NC pins) with respect to ground.......... –0.5 to 6.25V
Voltage on any output pins with
respect to ground.........................–0.5 to V +0.5V
CC
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMEND OPERATING CONDITIONS
Supply Voltage
Limits
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
X28LV010
3.3V ±10%
–40°C
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
CE = OE = V , WE = V , All I/O’s = Open,
Address Inputs = .4V/2.4V Levels @
f = 10MHz
I
V
V
Current (Active) (TTL Inputs)
20
mA
CC
CC
IL
IH
I
Current (Standby)
(CMOS Inputs)
Com.
Ind.
20
50
10
10
0.8
µA
µA
µA
µA
V
CE = V – 0.3V, OE = V , All I/O’s = Open,
CC IL
SB2
CC
Other Inputs = V
CC
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
V
V
= V to V
SS CC
LI
IN
I
= V to V , CE = V
SS CC IH
LO
OUT
(1)
lL
V
0.5
2
(1)
lH
V
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
+ 0.3
V
CC
V
0.4
V
I
I
= 2.1mA
OL
OL
V
2.4
V
= –400µA
OH
OH
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
POWER-UP TIMING
Symbol
Parameter
Max.
100
5
Units
(2)
PUR
t
Power-up to Read Operation
Power-up to Write Operation
µs
(2)
PUW
t
ms
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Parameter
Max.
10
Units
pF
Test Conditions
(2)
I/O
C
Input/Output Capacitance
Input Capacitance
V
= 0V
= 0V
I/O
(2)
IN
C
10
pF
V
IN
Characteristics subject to change without notice. 9 of 18
X28LV010
ENDURANCE AND DATA RETENTION
Parameter
Endurance(2)
Endurance(2)
Min.
10,000
100,000
100
Max.
Units
Cycles Per Byte
Cycles Per Page
Years
Data Retention(2)
Notes: (2) This parameter is periodically sampled and not 100% tested.
A.C. CONDITIONS OF TEST
SYMBOL TABLE
Input pulse levels
0V to 3V
10ns
Input rise and fall times
Input and output timing levels
WAVEFORM
INPUTS
OUTPUTS
1.5V
Must be
steady
Will be
steady
MODE SELECTION
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
CE OE WE
Mode
Read
Write
I/O
DOUT
DIN
Power
Active
Active
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
L
L
L
H
L
H
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
Standby and
write inhibit
H
X
X
High Z
Standby
X
X
L
X
H
Write inhibit
Write inhibit
—
—
—
—
N/A
Center Line
is High
Impedance
X
EQUIVALENT A.C. LOAD CIRCUIT
3.3V
1.92KΩ
Output
1.37KΩ
100pF
Characteristics subject to change without notice. 10 of 18
X28LV010
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28LV010-70 X28LV010-90 X28LV010-120 X28LV010-150
Symbol
Parameter
Min. Max. Min. Max.
Min.
Max.
120
120
40
Min.
Max. Units
t
Chip Enable Access Time
Address Access Time
70
70
35
90
90
40
150
150
40
ns
ns
ns
ns
ns
ns
ns
ns
CE
t
AA
t
Output Enable Access Time
CE LOW to Active Output
OE LOW to Active Output
CE HIGH to High Z Output
OE HIGH to High Z Output
OE
(3)
LZ
t
0
0
0
0
0
0
0
0
(3)
OLZ
t
(3)
HZ
t
40
40
50
50
50
50
50
50
(3)
OHZ
t
t
Output Hold from Address
Change
0
0
0
0
OH
Notes: (3) t min., t , t
min., and t
are periodically sampled and not 100% tested. t max. and t
max. are measured, with C = 5pF,
OHZ L
LZ
HZ OLZ
OHZ
HZ
from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
Read Cycle
t
RC
Address
CE
t
CE
t
OE
OE
V
IH
WE
t
t
OHZ
OLZ
t
t
t
t
LZ
OH
AA
HZ
High Z
Data I/O
Data Valid
Data Valid
Characteristics subject to change without notice. 11 of 18
X28LV010
Write Cycle Limits
Symbol
Parameter
Write Cycle Time
Min.
Max.
Units
ms
ns
(4)
WC
t
5
t
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery
Data Setup
0
50
0
AS
AH
CS
CH
t
t
ns
ns
t
0
ns
t
50
0
ns
CW
t
ns
OES
t
0
ns
OEH
t
50
50
50
10
10
0.2
ns
WP
t
ns
WPH
t
ns
DS
t
Data Hold
ns
DH
t
Delay to Next Write
Byte Load Cycle
µs
DW
t
100
µs
BLC
Notes: (4) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the
WC
device requires to complete internal write operation.
WE Controlled Write Cycle
t
WC
Address
t
t
AH
AS
t
t
CS
CH
CE
OE
t
t
OEH
OES
t
WP
WE
t
WPH
Data In
Data Out
Data Valid
t
t
DH
DS
High Z
Characteristics subject to change without notice. 12 of 18
X28LV010
CE Controlled Write Cycle
t
WC
Address
CE
t
t
AH
AS
t
CW
t
WPH
t
OES
OE
t
OEH
t
t
CH
CS
WE
Data Valid
Data In
t
t
DH
DS
Data Out
High Z
Page Write Cycle
OE(5)
CE
t
t
BLC
WP
WE
t
WPH
Address *(6)
Last Byte
Byte n+2
I/O
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
t
WC
*For each successive write within the page write operation, A –A
8
16
should be the same or writes to an unknown address could occur.
Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively per-
forming a polling operation.
(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to
either the CE or WE controlled write cycle timing.
Characteristics subject to change without notice. 13 of 18
X28LV010
DATA Polling Timing Diagram(7)
Address
CE
An
An
An
WE
t
t
OEH
OES
OE
t
DW
D
= X
D
= X
D
= X
OUT
I/O
7
IN
OUT
t
WC
Toggle Bit Timing Diagram
CE
WE
t
OES
t
OEH
OE
t
DW
High Z
I/O
*
6
*
t
WC
* I/O beginning and ending state will vary.
6
Notes: (7) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
Characteristics subject to change without notice. 14 of 18
X28LV010
PACKAGING INFORMATION
32-Lead Plastic Leaded Chip Carrier Package Type J
0.030" Typical
32 Places
0.050"
Typical
0.420 (10.67)
0.050"
Typical
0.510"
Typical
0.400"
0.050 (1.27) Typ.
0.300"
Ref.
0.410"
FOOTPRINT
0.021 (0.53)
0.013 (0.33)
Typ. 0.017 (0.43)
Seating Plane
0.045 (1.14) x 45°
±0.004 Lead
CO – Planarity
—
0.015 (0.38)
0.495 (12.57)
0.485 (12.32)
Typ. 0.490 (12.45)
0.095 (2.41)
0.060 (1.52)
0.140 (3.56)
0.100 (2.45)
Typ. 0.136 (3.45)
0.453 (11.51)
0.447 (11.35)
Typ. 0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
Ref.
Pin 1
0.595 (15.11)
0.585 (14.86)
Typ. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
Typ. 0.550 (13.97)
0.400
Ref.
(10.16)
3° Typ.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
Characteristics subject to change without notice. 15 of 18
X28LV010
PACKAGING INFORMATION
32-Lead Plastic Dual In-Line Package Type P
1.665 (42.29)
1.644 (41.76)
0.557 (14.15)
0.510 (12.95)
Pin 1 Index
Pin 1
0.085 (2.16)
0.040 (1.02)
1.500 (38.10)
Ref.
0.160 (4.06)
0.140 (3.56)
Seating
Plane
0.030 (0.76)
0.015 (0.38)
0.160 (4.06)
0.125 (3.17)
0.110 (2.79)
0.090 (2.29)
0.070 (17.78)
0.030 (7.62)
0.022 (0.56)
0.014 (0.36)
0.625 (15.88)
0.590 (14.99)
0°
15°
Typ. 0.010 (0.25)
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 16 of 18
X28LV010
PACKAGING INFORMATION
40-Lead Thin Small Outline Package (TSOP) Type T
0.493 (12.522)
0.483 (12.268)
0.045 (1.143)
(0.038)
0.965
Pin #1 Ident
0.035 (0.889)
0.005 (0.127) Dp.
O 0.040 (1.016)
X
O 0.030 (0.762) 0.003 (0.076) Dp.
0.048 (1.219)
0.0197 (0.500)
1
0.396 (10.058)
0.392 (9.957)
0.007 (0.178)
15° Typ.
Seating
Plane
0.010 (0.254)
0.006 (0.152)
0.040 (1.016)
A
0.0025 (0.065)
Seating
Plane
Detail A
0.032 (0.813) Typ.
0.557 (14.148)
0.547 (13.894)
0.006 (0.152)
0.017 (0.432)
0.017 (0.432)
Typ.
4° Typ.
0.020 (0.508) Typ.
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
(0.012 ± 0.002)
Solder
Pads
Typical
40 Places
15 Eq. Spc.@ 0.50 ± 0.04
0.0197 0.016 = 9.50 ± 0.06
(0.374 ± 0.0024) Overall
Tol. Non-Cumulative
0.17 (0.007)
0.03 (0.001)
0.50 ± 0.04
(0.0197 ± 0.0016)
1.30 ± 0.05
(0.051 ± 0.002)
FOOTPRINT
NOTE: ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
Characteristics subject to change without notice. 17 of 18
X28LV010
Ordering Information
X
X28LV010
X
-X
AccessTime
–70 = 70ns
–90 = 90ns
–12 = 120ns
–15 = 150ns
Device
Temperature Range
Blank = Commercial = 0°C to 70°C
I = Industrial = –40°C to +85°C
Package
P = 32-Lead PDIP
J = 32-Lead PLCC
T = 40-Lead TSOP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes
no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and
without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137;
5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and
correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 18 of 18
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