X28VC256JMB-70 [XICOR]
5 Volt, Byte Alterable E2PROM; 5伏，可变的字节E2PROM
| 型号： | X28VC256JMB-70 |
| 厂家： | 
XICOR INC. |
| 描述： | 5 Volt, Byte Alterable E2PROM |
| 文件： | 总24页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256K
X28VC256
5 Volt, Byte Alterable E2PROM
DESCRIPTION
32K x 8 Bit
FEATURES
• Access Time: 45ns
• Simple Byte and Page Write
—Single 5V Supply
The X28VC256 is a second generation high perfor-
mance CMOS 32K x 8 E PROM. It is fabricated with
Xicor’s proprietary, textured poly floating gate tech-
nology, providing a highly reliable 5 Volt only nonvolatile
memory.
2
—No External High Voltages or V Control
PP
Circuits
—Self-Timed
The X28VC256 supports a 128-byte page write opera-
tion, effectively providing a 24µs/byte write cycle and
enabling the entire memory to be typically rewritten in
less than 0.8 seconds. The X28VC256 also features
DATA Polling and Toggle Bit Polling, two methods of
providing early end of write detection. The X28VC256
also supports the JEDEC standard Software Data Pro-
tection feature for protecting against inadvertent writes
during power-up and power-down.
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS:
—Active: 80mA
—Standby: 10mA
• Software Data Protection
—Protects Data Against System Level
Inadvertent Writes
• High Speed Page Write Capability
Endurance for the X28VC256 is specified as a minimum
100,000 write cycles per byte and an inherent data
retention of 100 years.
™
• Highly Reliable Direct Write Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
• Early End of Write Detection
—DATA Polling
—Toggle Bit Polling
PIN CONFIGURATION
PLASTIC DIP
CERDIP
FLAT PACK
LCC
PLCC
SOIC
TSOP
A14
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
4
3
2
1
32 31 30
29
A
WE
A
A
A
I/O
I/O
I/O
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
A
A
A
A
A
NC
V
NC
WE
12
2
1
0
0
1
2
3
4
5
6
7
12
14
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
A
A
A
A
A
A
A
5
6
7
8
9
A
A
A
13
6
5
4
3
2
1
0
8
A
8
A
9
28
27
26
25
24
23
22
21
9
11
A
NC
OE
A
11
NC
X28VC256
OE
V
SS
NC
X28VC256
X28VC256
9
CC
A
10
11
12
13
10
10
I/O
10
11
12
13
14
15
16
3
4
5
6
7
CE
CE
I/O
I/O
I/O
I/O
I/O
A
A
A
A
13
8
9
10
11
12
13
14
I/O
7
I/O
6
I/O
5
I/0
4
NC
I/O
7
I/O
0
I/O
1
I/O
2
I/O
0
6
14 15 16 17 18 19 20
CE
11
A
OE
10
V
I/O
3
SS
3869 FHD F03
3869 ILL F22
3869 FHD F02
©Xicor, Inc. 1991, 1995 Patents Pending
3869-2.6 4/2/96 T4/C4/D0 NS
Characteristics subject to change without notice
1
X28VC256
PIN DESCRIPTIONS
Addresses (A –A )
PIN NAMES
Symbol
Description
0
14
The Address inputs select an 8-bit memory location
during a read or write operation.
A –A
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
0
14
I/O –I/O
0
7
WE
CE
OE
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
writeoperations.WhenCEisHIGH,powerconsumption
is reduced.
V
V
CC
SS
Ground
Output Enable (OE)
NC
No Connect
TheOutputEnableinputcontrolsthedataoutputbuffers
and is used to initiate read operations.
3869 PGM T01
PIN CONFIGURATION
Data In/Data Out (I/O –I/O )
0
7
PGA
DataiswrittentoorreadfromtheX28VC256throughthe
I/O pins.
I/O
12
I/O
13
I/O
15
I/O
17
I/O
18
1
2
3
5
6
I/O
11
A
10
V
14
I/O
16
I/O
19
0
0
SS
4
7
Write Enable (WE)
A
A
A
A
CE
20
A
21
1
3
2
4
10
11
The Write Enable input controls the writing of data to the
X28VC256.
9
7
8
6
OE
22
A
23
A
A
V
28
A
24
A
25
5
6
12
7
CC
9
8
5
4
2
3
A
A
WE
27
A
13
26
A
14
1
3869 FHD F04
X28VC256
(BOTTOM VIEW)
FUNCTIONAL DIAGRAM
256K-BIT
E PROM
ARRAY
X BUFFERS
LATCHES AND
DECODER
2
A –A
0
14
ADDRESS
INPUTS
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
I/O –I/O
0
7
DATA INPUTS/OUTPUTS
CE
OE
WE
CONTROL
LOGIC AND
TIMING
V
CC
3869 FHD F01
V
SS
2
X28VC256
DEVICE OPERATION
Read
Write Operation Status Bits
The X28VC256 provides the user two write operation
status bits. These can be used to optimize a system write
cycletime. ThestatusbitsaremappedontotheI/Obusas
shown in Figure 1.
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
natesbuscontentioninasystemenvironment. Thedata
bus will be in a high impedance state when either OE or
CE is HIGH.
Figure 1. Status Bit Assignment
I/O DP TB
5
4
3
2
1
0
Write
Write operations are initiated when bothCE and WE are
LOW and OE is HIGH. The X28VC256 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE,
whichever occurs first. A byte write operation, once
initiated, will automatically continue to completion, typi-
cally within 3ms.
RESERVED
TOGGLE BIT
DATA POLLING
3869 FHD F11
DATA Polling (I/O )
7
The X28VC256 features DATA Polling as a method to
indicate to the host system that the byte write or page
writecyclehascompleted.DATAPollingallowsasimple
bit test operation to determine the status of the
X28VC256, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will
Page Write Operation
The page write feature of the X28VC256 allows the
entire memory to be written in typically 0.8 seconds.
Page write allows up to one hundred twenty-eight bytes
of data to be consecutively written to the X28VC256
prior to the commencement of the internal programming
cycle. The host can fetch data from another device
within the system during a page write operation (change
produce the complement of that data on I/O (i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
7
programming cycle is complete, I/O will reflect true
7
data.
the source address), but the page address (A through
7
A ) for each subsequent valid write cycle to the part
14
Toggle Bit (I/O )
6
during this operation must be the same as the initial
page address.
The X28VC256 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle I/O will toggle from
6
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by the
WE HIGH to LOW transition, must begin within 100µs of
the falling edge of the preceding WE. If a subsequent
WE HIGH to LOW transition is not detected within
100µs, the internal automatic programming cycle will
commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100µs.
HIGH to LOW and LOW to HIGH on subsequent at-
tempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read and write operations.
3
X28VC256
DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
LAST
WRITE
WE
CE
OE
V
IH
V
HIGH Z
OH
I/O
7
V
OL
X28VC256
READY
A –A
An
An
An
An
An
An
An
0
14
3869 FHD F12
Figure 3. DATA Polling Software Flow
DATA Polling can effectively halve the time for writing to
the X28VC256. The timing diagram in Figure 2 illus-
trates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
WRITE DATA
NO
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
NO
7
COMPARE?
YES
X28VC256
READY
3869 FHD F13
4
X28VC256
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
V
OH
HIGH Z
I/O
*
6
*
V
OL
X28VC256
READY
* I/O beginning and ending state of I/O will vary.
6
6
3869 FHD F14
Figure 5. Toggle Bit Software Flow
TheToggleBitcaneliminatethesoftwarehousekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28VC256 memories that is frequently up-
dated. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow
diagram in Figure 5 illustrates a method for polling the
Toggle Bit.
LAST WRITE
YES
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
NO
COMPARE
OK?
YES
X28VC256
READY
3869 FHD F15
5
X28VC256
HARDWARE DATA PROTECTION
circuits by employing the software data protection fea-
ture. The internal software data protection circuit is
enabled after the first write operation utilizing the soft-
warealgorithm. Thiscircuitisnonvolatileandwillremain
set for the life of the device unless the reset command
is issued.
The X28VC256 provides two hardware features that
protect nonvolatile data from inadvertent writes.
•Default V Sense—All write functions are inhibited
CC
when V is ≤ 3.5V typically.
CC
•Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
Once the software protection is enabled, the X28VC256
is also protected from inadvertent and accidental writes
in the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
SOFTWARE DATA PROTECTION
TheX28VC256offersasoftwarecontrolleddataprotec-
tion feature. The X28VC256 is shipped from Xicor with
thesoftwaredataprotectionNOTENABLED;thatis, the
device will be in the standard operating mode. In this
mode data should be protected during power-up/down
operations through the use of external circuits. The host
would then have open read and write access of the
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific ad-
dresses. Refer to Figure 6 and 7 for the sequence. The
three-byte sequence opens the page write window
enabling the host to write from one to one hundred
twenty-eightbytesofdata.Oncethepageloadcyclehas
been completed, the device will automatically be re-
turned to the data protected state.
device once V was stable.
CC
The X28VC256 can be automatically protected during
power-upandpower-downwithouttheneedforexternal
6
X28VC256
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
V
(V
)
CC
CC
0V
DATA
ADDRESS
AA
5555
55
2AAA
A0
5555
t
WRITE
PROTECTED
WC
WRITES
OK
CE
≤t
BYTE
OR
PAGE
BLC MAX
WE
3869 FHD F16
Figure 7. Write Sequence for
Software Data Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the
X28VC256 will automatically disable further writes un-
less another command is issued to cancel it. If no further
commands are issued the X28VC256 will be write
protected during power-down and after any subsequent
power-up.
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
Note: Onceinitiated,thesequenceofwriteoperations
should not be interrupted.
WRITE DATA A0
TO ADDRESS
5555
BYTE/PAGE
LOAD ENABLED
WRITE DATA XX
TO ANY
ADDRESS
OPTIONAL
BYTE OR
PAGE WRITE
ALLOWED
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER t
RE-ENTERS DATA
WC
PROTECTED STATE
3869 FHD F17
7
X28VC256
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
V
CC
DATA
ADDRESS
STANDARD
OPERATING
MODE
t
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
WC
CE
WE
3869 FHD F18
Figure 9. Write Sequence for Resetting
Software Data Protection
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E PROM programmer, the following six step algo-
WRITE DATA AA
TO ADDRESS
5555
2
rithm will reset the internal protection circuit. After t
the X28VC256 will be in standard operating mode.
,
WC
WRITE DATA 55
TO ADDRESS
2AAA
Note: Onceinitiated,thesequenceofwriteoperations
should not be interrupted.
WRITE DATA 80
TO ADDRESS
5555
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 20
TO ADDRESS
5555
AFTER t
,
WC
RE-ENTERS
UNPROTECTED
STATE
3869 FHD F19
8
X28VC256
SYSTEM CONSIDERATIONS
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the l/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high fre-
Because the X28VC256 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usagecanprovidethelowestpossiblepowerdissipation
and eliminate the possibility of contention where mul-
tiple I/O pins share the same bus.
quency ceramic capacitor be used between V
and
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
CC
V
SS
at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V and V for each
CC
SS
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
BecausetheX28VC256hastwopowermodes, standby
and active, proper decoupling of the memory array is of
9
X28VC256
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecificationis
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
X28VC256 .................................. –10°C to +85°C
X28VC256I, X28VC256M .......... –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
.................................. –1V to +7V
SS
D.C. Output Current ........................................... 10mA
Lead Temperature (Soldering, 10 seconds)...... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
Industrial
Military
0°C
+70°C
+85°C
+125°C
X28VC256
5V ±10%
3869 PGM T03.1
–40°C
–55°C
3869 PGM T02.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
(1)
Symbol
Parameter
Min. Typ.
Max.
Units
Test Conditions
CE = OE = V , WE = V ,
All I/O’s = Open, Address Inputs =
0.4V/2.4V Levels @ f = 10MHz
I
V
V
Active Current
30
80
mA
CC
CC
IL
IH
I
SB
Standby Current
10
25
mA
CE = V , OE = V , All I/O’s =
IH IL
CC
Open, Other Inputs = V
IH
I
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V , CE = V
LO
OUT
SS
CC
IH
(2)
V
V
V
V
–1
2
0.8
lL
(2)
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
+ 1
CC
V
IH
0.4
V
I = 6mA
OL
OL
OH
2.4
V
I = –4mA
OH
3869 PGM T04.2
Notes: (1) Typical values are for T = 25°C and nominal supply voltage.
A
(2) V min. and V max. are for reference only and are not tested.
IL IH
10
X28VC256
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(3)
t
Power-Up to Read
Power-Up to Write
100
5
µs
PUR
(3)
t
ms
PUW
3869 PGM T05
CAPACITANCE T = +25°C, f = 1MHZ, V = 5V.
A
CC
Symbol
Test
Max.
Units
Conditions
(3)
C
C
Input/Output Capacitance
Input Capacitance
10
6
pF
pF
V
= 0V
= 0V
I/O
I/O
(3)
V
IN
IN
3869 PGM T06.1
ENDURANCE AND DATA RETENTION
Parameter
Min.
Max.
Units
Endurance
100,000
100
Cycles
Years
Data Retention
3869 PGM T07.3
A.C. CONDITIONS OF TEST
MODE SELECTION
Input Pulse Levels
0V to 3V
CE
OE
WE
Mode
I/O
Power
Input Rise and
Fall Times
L
L
L
H
X
L
H
L
Read
Write
D
Active
Active
OUT
5ns
D
IN
Input and Output
Timing Levels
H
X
X
X
X
H
Standby and Write Inhibit
Write Inhibit
High Z Standby
1.5V
3869 PGM T08.1
—
—
—
X
Write Inhibit
—
3869 PGM T09
Note: (3) This parameter is periodically sampled and not 100%
tested.
SYMBOL TABLE
EQUIVALENT A.C. LOAD CIRCUIT
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
5V
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
1.92KΩ
OUTPUT
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
1.37KΩ
30pF
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
3869 FHD F20.3
11
X28VC256
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28VC256-45 X28VC256-55 X28VC256-70 X28VC256-90
–40°C to 85°C –55°C to 125°C –55°C to 125°C –55°C to 125°C
Symbol
Parameter
Read Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Units
t
t
t
t
t
t
t
t
t
45
55
70
90
ns
90
90
40
RC
CE
AA
OE
LZ
Chip Enable Access Time
Address Access Time
45
45
30
55
55
30
70
70
35
ns
ns
ns
ns
ns
ns
ns
ns
Output Enable Access Time
CE LOW to Active Output
OE LOW to Active Output
CE HIGH to High Z Output
OE HIGH to High Z Output
Output Hold From Address Change
(4)
0
0
0
0
0
0
0
0
(4)
OLZ
(4)
30
30
30
30
35
35
40
40
HZ
(4)
OHZ
OH
0
0
0
0
3869 PGM T10.1
Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
WE
t
t
OLZ
OHZ
t
t
t
LZ
OH
HZ
HIGH Z
DATA I/O
DATA VALID
DATA VALID
t
AA
3869 FHD F05
Notes: (4)
t
LZ
min., t , t
HZ OLZ
min. and t
OHZ
are periodically sampled and not 100% tested, t and t are measured, with CL = 5pF,
HZ OHZ
from the point whin CE, OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
12
X28VC256
Write Cycle Limits
(5)
Symbol
Parameter
Write Cycle Time
Min.
Typ.
Max.
Units
(6)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
WC
Address Setup Time
Address Hold Time
Write Setup Time
0
50
0
AS
AH
CS
Write Hold Time
0
CH
CE Pulse Width
50
0
CW
OES
OEH
WP
WPH
DV
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery (page write only)
Data Valid
0
50
50
(7)
1
Data Setup
50
0
DS
Data Hold
DH
(7)
Delay to Next Write after Polling is True
Byte Load Cycle
10
DW
0.150
100
µs
BLC
3869 PGM T11.2
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AS
AH
t
t
CS
CH
CE
OE
t
t
OES
OEH
t
WP
WE
DATA IN
DATA OUT
DATA VALID
t
t
DS
DH
HIGH Z
3869 FHD F06
Notes: (5) Typical values are for T = 25°C and nominal supply voltage.
A
(6) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WC
time the device requires to automatically complete the internal write operation.
(7) t and t are periodically sampled and not 100% tested.
WPH
DW
13
X28VC256
CE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
CW
CE
t
t
OES
OEH
OE
t
t
CH
CS
WE
DATA IN
DATA VALID
t
t
DH
DS
HIGH Z
DATA OUT
3869 FHD F07
Page Write Cycle
OE(8)
CE
t
t
WP
BLC
WE
t
WPH
ADDRESS*(9)
I/O
LAST BYTE
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
BYTE n+2
t
WC
*For each successive write within the page write operation, A –A should be the same or
14
7
writes to an unknown address could occur.
3869 FHD F08
Notes: (8) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively
performing a polling operation.
(9) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform
to either the CE or WE controlled write cycle timing.
14
X28VC256
DATA Polling Timing Diagram(10)
A
A
A
N
ADDRESS
CE
N
N
WE
t
t
OES
OEH
OE
t
DW
=X
D
=X
D
=X
D
I/O
7
IN
OUT
OUT
t
WC
3869 FHD F09
Toggle Bit Timing Diagram(10)
CE
WE
t
t
OES
OEH
OE
t
DW
HIGH Z
I/O
6
*
*
t
WC
* I/O beginning and ending state will vary, depending upon actual t
WC
6
3869 FHD F10
Note: (10) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
15
X28VC256
PACKAGING INFORMATION
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.460 (37.08)
1.400 (35.56)
0.550 (13.97)
0.510 (12.95)
PIN 1 INDEX
PIN 1
0.085 (2.16)
0.040 (1.02)
1.300 (33.02)
REF.
0.160 (4.06)
0.125 (3.17)
SEATING
PLANE
0.030 (0.76)
0.015 (0.38)
0.150 (3.81)
0.125 (3.17)
0.110 (2.79)
0.090 (2.29)
0.062 (1.57)
0.050 (1.27)
0.020 (0.51)
0.016 (0.41)
0.610 (15.49)
0.590 (14.99)
0°
15°
TYP. 0.010 (0.25)
3926 FHD F04
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
16
X28VC256
PACKAGING INFORMATION
28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
1.490 (37.85) MAX.
0.610 (15.49)
0.500 (12.70)
PIN 1
0.005 (0.127) MIN.
0.100 (2.54) MAX.
SEATING
PLANE
0.232 (5.90) MAX.
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
0.150 (3.81) MIN.
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.038 (0.97)
0.023 (0.58)
0.014 (0.36)
TYP. 0.100 (2.54)
TYP. 0.055 (1.40)
TYP. 0.018 (0.46)
0.620 (15.75)
0.590 (14.99)
TYP. 0.614 (15.60)
0°
0.015 (0.38)
0.008 (0.20)
15°
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F08
17
X28VC256
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.420 (10.67)
0.050 (1.27) TYP.
0.021 (0.53)
0.013 (0.33)
TYP. 0.017 (0.43)
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.045 (1.14) x 45°
0.015 (0.38)
0.095 (2.41)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
0.060 (1.52)
0.140 (3.56)
0.453 (11.51)
0.100 (2.45)
TYP. 0.136 (3.45)
0.447 (11.35)
TYP. 0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
REF.
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
3926 FHD F13
3926 Fhd F13
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
18
X28VC256
PACKAGING INFORMATION
28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.2980 (7.5692) 0.4160 (10.5664)
0.2920 (7.4168) 0.3980 (10.1092)
0.0192 (0.4877)
0.0138 (0.3505)
0.7080 (17.9832)
0.7020 (17.8308)
0.1040 (2.6416)
0.0940 (2.3876)
BASE PLANE
SEATING PLANE
0.0110 (0.2794)
0.050 (1.270)
BSC
0.0040 (0.1016)
0.0160 (0.4064)
0.0100 (0.2540)
X 45°
0.0125 (0.3175)
0.0090 (0.2311)
0° – 8°
0.0350 (0.8890)
0.0160 (0.4064)
3926 FHD F17
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3. BACK EJECTOR PIN MARKED “KOREA”
4. CONTROLLING DIMENSION: INCHES (MM)
19
X28VC256
PACKAGING INFORMATION
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
0.300 (7.62)
BSC
0.150 (3.81) BSC
0.020 (0.51) x 45° REF.
0.015 (0.38)
0.003 (0.08)
0.095 (2.41)
0.075 (1.91)
PIN 1
0.022 (0.56)
DIA.
0.006 (0.15)
0.055 (1.39)
0.200 (5.08)
BSC
0.045 (1.14)
TYP. (4) PLCS.
0.015 (0.38)
MIN.
0.028 (0.71)
0.040 (1.02) x 45° REF.
0.022 (0.56)
(32) PLCS.
TYP. (3) PLCS.
0.050 (1.27) BSC
0.458 (11.63)
0.088 (2.24)
0.050 (1.27)
0.442 (11.22)
0.120 (3.05)
0.458 (11.63)
––
0.060 (1.52)
0.558 (14.17)
––
0.560 (14.22)
0.540 (13.71)
0.400 (10.16)
BSC
PIN 1 INDEX CORNER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
3926 FHD F14
20
X28VC256
PACKAGING INFORMATION
28-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K
12
11
9
13
10
8
15
14
17
16
20
22
24
27
18
19
21
23
25
26
A
A
0.008 (0.20)
0.050 (1.27)
7
6
5
2
28
1
NOTE: LEADS 4,12,18 & 26
4
3
0.080 (2.03)
0.070 (1.78)
TYP. 0.100 (2.54)
ALL LEADS
4 CORNERS
0.080 (2.03)
0.070 (1.78)
0.110 (2.79)
0.080 (2.03)
0.072 (1.83)
0.061 (1.55)
PIN 1 INDEX
0.020 (0.51)
0.016 (0.41)
0.660 (16.76)
0.640 (16.26)
A
A
0.185 (4.70)
0.175 (4.44)
0.561 (14.25)
0.541 (13.75)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F15
21
X28VC256
PACKAGING INFORMATION
28-LEAD CERAMIC FLAT PACK TYPE F
0.019 (0.48)
0.015 (0.38)
PIN 1 INDEX
1
28
0.050 (1.27) BSC
0.740 (18.80)
MAX.
0.045 (1.14) MAX.
0.440 (11.18)
MAX.
0.130 (3.30)
0.090 (2.29)
0.006 (0.15)
0.003 (0.08)
0.370 (9.40)
0.250 (6.35)
0.045 (1.14)
0.025 (0.66)
TYP. 0.300 2 PLCS.
0.180 (4.57)
MIN.
0.030 (0.76)
MIN.
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F16
22
X28VC256
PACKAGING INFORMATION
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T
SEE NOTE 2
12.50 (0.492)
12.30 (0.484)
PIN #1 IDENT.
O 0.76 (0.03)
0.50 (0.0197) BSC
SEE NOTE 2
8.02 (0.315)
7.98 (0.314)
0.26 (0.010)
0.14 (0.006)
1.18 (0.046)
1.02 (0.040)
0.17 (0.007)
0.03 (0.001)
SEATING
PLANE
0.58 (0.023)
0.42 (0.017)
14.15 (0.557)
13.83 (0.544)
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
(0.012 ± 0.002)
SOLDER PADS
TYPICAL
32 PLACES
15 EQ. SPC. 0.50 ± 0.04
0.0197 ± 0.016 = 7.50 ± 0.06
(0.295 ± 0.0024) OVERALL
TOL. NON-CUMULATIVE
0.17 (0.007)
0.03 (0.001)
0.50 ± 0.04
(0.0197 ± 0.0016)
1.30 ± 0.05
(0.051 ± 0.002)
FOOTPRINT
NOTE:
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
3926 ILL F38.1
23
X28VC256
ORDERING INFORMATION
X28VC256
X
X
-X
Access Time
–45 = 45ns
–55 = 55ns
–70 = 70ns
–90 = 90ns
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
P = 28-Lead Plastic DIP
D = 28-Lead Cerdip
J = 32-Lead PLCC
S = 28-Lead Plastic SOIC
E = 32-Pad LCC
K = 28-Lead Pin Grid Array
F = 28-Lead Flat Pack
T = 32-Lead TSOP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
24
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