X3101_技术文档

APPLICATION NOTE

A V A I L A B L E

3 or 4 Cell Li-Ion BATTERY PACKS

Preliminary

Preliminary Information

4 cell / 3 cell

X3100/X3101

3 or 4 Cell Li-Ion Battery Protection and Monitor IC

FEATURE

BENEFIT

• Software Selectable Protection Levels and

Variable Protect Detection/Release Times

• Integrated FET Drive Circuitry

• Cell Voltage and Current Monitoring

• 0.5% Accurate Voltage Regulator

• Integrated 4kbit EEPROM

• Flexible Power Management with 1µA Sleep

Mode

• Cell Balancing Control

• Optimize protection for chosen cells to allow

maximum use of pack capacity.

• Reduce component count and cost

• Simplify implementation of gas gauge

• Accurate voltage and current measurements

• Record battery history to optimize gas gauge,

track pack failures and monitor system use

• Reduce power to extend battery life

• Increase battery capacity and improve cycle life

battery life

DESCRIPTION

Using an internal analog multiplexer, the X3100 or

X3101 allow battery parameters such as cell voltage

and current (using a sense resistor) to be monitored

externally by a separate microcontroller with A/D

converter. Software on this microcontroller implements

gas gauge and cell balancing functionality in software.

The X3100 is a protection and monitor IC for use in

battery packs consisting of 4 series Lithium-Ion

battery cells. The X3101 is designed to work in 3 cell

applications. Both devices provide internal over-

charge, over-discharge, and over-current protection

circuitry, internal EEPROM memory, an internal

voltage regulator, and internal drive circuitry for

external FET devices that control cell charge,

discharge, and cell voltage balancing.

The X3100 and X3101 contain a current sense

ampliﬁer. Selectable gains of 10, 25, 80 and 160 allow

an external 10 bit A/D converter to achieve better

resolution than a more expensive 14 bit converter.

Over-charge, over-discharge, and over-current

thresholds reside in an internal EEPROM memory

register and are selected independently via software

using a 3MHz SPI serial interface. Detection and time-

out delays can also be individually varied using

external capacitors.

An internal 4kbit EEPROM memory featuring

IDLock^™, allows the designer to partition and “lock in”

written battery cell/pack data.

The X3100 and X3101 are each housed in a 28 Pin

TSSOP package.

FUNCTIONAL DIAGRAM

RGC RGO

VCC RGP

UVP/OCP OVP/LMON

AS0

AS1

AS2

FET Control

Circuitry

5VDC

Regulator

VCELL1

Analog

MUX

CB1

AO

VCELL2

CB2

Over-charge

Protection

Sample Rate

Timer

Internal Voltage Regulator

Power On reset &

Over-discharge

Protection

Sense

Status Register

S0

4 kbit

EEPROM

VCELL3

CB3

Circuits

SCK

CS

SI

SPI

I/F

Protection Circuit

Timing Control

& Conﬁguration

Conﬁguration

Register

Control

Register

Over-current

Protection &

Current Sense

VCELL4/VSS

CB4

VSS

VCS1 VCS2

OVT UVT OCT

Characteristics subject to change without notice. 1 of 40

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X3100/X3101 – Preliminary Information

PRINCIPLES OF OPERATION

PIN NAMES

The X3100 and X3101 provide two distinct levels of

functionality and battery cell protection:

Pin Symbol

Description

1

2

3

4

5

6

VCELL1 Battery cell 1 voltage input

CB1 Cell balancing FET control output 1

VCELL2 Battery cell 2 voltage

First, in Normal mode, the device periodically checks

each cell for an over-charge and over-discharge state,

while continuously watching for a pack over-current

condition. A protection mode violation results from an

over-charge, over-discharge, or over-current state. The

thresholds for these states are selected by the user

through software. When one of these conditions occur, a

Discharge FET or a Charge FET or both FETs are

turned off to protect the battery pack. In an over-

discharge condition, the X3100 and X3101 devices go

into a low power sleep mode to conserve battery power.

During sleep, the voltage regulator turns off, removing

power from the microcontroller to further reduce pack

current.

CB2

Cell balancing FET control output 2

VCELL3 Battery cell 3 voltage

CB3

Cell balancing FET control output 3

VCELL4/ Battery cell 4 voltage (X3100)

7

VSS

CB4

VSS

Ground (X3101)

8

Cell balancing FET control output 4

Ground

9

10

11

12

13

14

15

16

17

18

19

20

21

22

VCS1 Current sense voltage pin 1

VCS2 Current sense voltage pin 2

OVT

UVT

OCT

AO

Over-charge detect/release time input

Over-discharge detect/release time input

Over-current detect/release time input

Analog multiplexer output

Analog output select pin 0

Analog output select pin 1

Analog output select pin 2

Serial data input

Second, in Monitor mode, a microcontroller with A/D

converter measures battery cell voltage and pack current

via pin AO and the X3100 or X3101 on-board MUX. The

user can thus implement protection, charge/discharge,

cell balancing or gas gauge software algorithms to suit

the speciﬁc application and characteristics of the cells

used. While monitoring these voltages, all protection

circuits are on continuously.

AS0

AS1

AS2

SI

In a typical application, the microcontroller is also

programmed to provide an SMBus interface along with

the Smart Battery System interface protocols. These

additions allow an X3100 or X3101 based module to

adhere to the latest industry battery pack standards.

SO

Serial data output

SCK

CS

Serial data clock input

Chip select input pin

OVP/

Over-charge Voltage Protection output/

23

24

LMON Load Monitor output

PIN CONFIGURATION

UVP/

OCP

Over-discharge protection output/

28 LeadTSSOP

Over-current protection output

Voltage regulator output pin

Voltage regulator control pin

Voltage regulator protection pin

Power supply

VCC

VCELL1

CB1

1

2

3

4

28

27

26

25

26

27

28

RGO

RGC

RGP

VCC

RGP

VCELL2

RGC

CB2

RGO

VCELL3

UVP/OCP

OVP/LMON

CS

5

24

23

22

21

20

19

CB3

6

X3100/

X3101

VCELL4/VSS*

PIN DESCRIPTIONS

7

CB4

VSS

SCK

SO

8

Battery Cell Voltage (VCELL1-VCELL4):

9

These pins are used to monitor the voltage of each

battery cell internally. The voltage of an individual cell

can also be monitored externally at pin AO.

VCS1

VCS2

SI

10

11

AS2

AS1

18

17

16

OVT

UVT

OCT

12

13

AS0

AO

The X3100 monitors 4 battery cells.The X3101 monitors

3 battery cells. For the X3101 device connect the

VCELL4/VSS pin to ground.

15

14

*For X3101, Connect to ground.

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X3100/X3101 – Preliminary Information

Cell Voltage Balancing Control (CB1-CB4):

Analog Output Select (AS0–AS2):

These outputs are used to switch external FETs in order

to perform cell voltage balancing control. This function

can be used to adjust individual cell voltages (e.g.

during cell charging). CB1–CB4 can be driven high

(Vcc) or low (Vss) to switch external FETs ON/OFF. When

using the X3101, the CB4 pin can be left unconnected,

or the FET control can be used for other purposes.

These pins select which voltage is to be multiplexed to

the output AO (see section “Sleep Control (SLP)” on

page 10 and section “Current Monitor Function” on

page 20)

Serial Input (SI):

SI is the serial data input pin. All opcodes, byte

addresses, and data to be written to the device are input

on this pin.

Current Sense Inputs (VCS1–VCS2):

A sense resistor (R

) is connected between VCS1

SENSE

and VCS2 (Figure 1). R

has a resistance in the

Serial Output (SO):

SENSE

order of 20mΩ to 100mΩ, and is used to monitor current

ﬂowing through the battery terminals, and protect

against over-current conditions.The voltage at each end

SO is a push/pull serial data output pin. During a read

cycle, data is shifted out on this pin. Data is clocked out

by the falling edge of the serial clock. While CS is HIGH,

SO will be in a High Impedance state.

of R

can also be monitored at pin AO.

SENSE

Note: SI and SO may be tied together to form one line

(SI/SO). In this case, all serial data communication with

the X3100 or X3101 is undertaken over one I/O line.

This is permitted ONLY if no simultaneous read/write

operations occur.

Over-charge Voltage detect Time control (OVT):

This pin is used to control the delay time (T

)

OV

associated with the detection of an over-charge

condition (see section “Over-charge Protection” on page

13).

Serial Clock (SCK):

Over-discharge detect/release time control (UVT):

The Serial Clock controls the serial bus timing for data

input and output. Opcodes, addresses, or data present

on the SI pin are latched on the rising edge of the clock

input, while data on the SO pin change after the falling

edge of the clock input.

This pin is used to control the delay times associated

with the detection (T ) and release (T

) of an over-

UV

UVR

discharge (under-voltage) condition (see section “Over-

discharge Protection” on page 15).

Over-current detect/release time control (OCT):

Chip Select (CS):

This pin is used to control the delay times associated

When CS is HIGH, the device is deselected and the SO

output pin is at high impedance. CS LOW enables the

SPI serial bus.

with the detection (T ) and release (T

current condition (see section “Over-Current Protection”

on page 18).

) of an over-

OC

OCR

Over-charge Voltage Protection/Load Monitor

(OVP/LMON):

Analog Output (AO):

The analog output pin is used to externally monitor

various battery parameter voltages. The voltages which

can be monitored at AO (see section “Analog

Multiplexer Selection” on page 20) are:

This one pin performs two functions depending upon

the present mode of operation of the X3100 or X3101.

—Over-charge Voltage Protection (OVP)

This pin controls the switching of the battery pack charge

FET. This power FET is a P-channel device. As such,

– Individual cell voltages

.

– Voltage across the current sense resistor (R

)

cell charge is possible when OVP/LMON=V , and cell

SENSE

SS

This voltage is ampliﬁed with a gain set by the user in

the control register (see section “Current Monitor

Function” on page 20.)

charge is prohibited when OVP/LMON=V . In this

CC

conﬁguration the X3100 and X3101 turn off the charge

voltage when the cells reach the over-charge limit. This

prevents damage to the battery cells due to the

application of charging voltage for an extended period of

time (see section “Over-charge Protection” on page 13).

The analog select pins pins AS0–AS2 select the desired

voltage to be monitored on the AO pin.

Characteristics subject to change without notice. 3 of 40

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X3100/X3101 – Preliminary Information

—Load Monitor (LMON)

powered by the Li-Ion battery cells in normal operating

conditions, and allow the device to be powered by an

external source (such as a charger) via pin P+ when the

battery cells are being charged. These diodes should

have sufﬁcient current and voltage ratings to handle both

cases of battery cell charge and discharge.

In Over-current Protection mode, a small test current

(7.5µA typ.) is passed out of this pin to sense the load

resistance. The measured load resistance determines

whether or not the X3100 or X3101 returns from an

over-current protection mode (see section “Over-Current

Protection” on page 18).

The operation of the voltage regulator is described in

section “Voltage Regulator” on page 21. This regulator

provides a 5VDC 0.5ꢀ output. The capacitor (C1)

connected from RGO to ground provides some noise

ﬁltering on the RGO output. The recommended value is

Over-discharge (Under Voltage) Protection/

Over-current Protection (UVP/OCP):

Pin UVP/OCP controls the battery cell discharge via an

external power FET. This P-channel FET allows cell

discharge when UVP/OCP=Vss, and prevents cell

discharge when UVP/OCP=Vcc. The X3100 and X3101

turn the external power FET off when the X3100 or

X3101 detects either:

0.1µF or less. The value chosen must allow V

to

RGO

decay to 0.1V in 170ms or less when the X3100 or

X3101 enter the sleep mode. If the decay is slower than

this, a resistor (R1) can be placed in parallel with the

capacitor.

—Over-discharge Protection (UVP)

During an initial turn-on period (T

+ T ), V

has

PUR

OC

RGO

In this case, pin 24 is referred to as “Over-discharge

(Under-Voltage) protection (UVP)” (see section “Over-

discharge Protection” on page 15). UVP/OCP turns off

the FET to prevent damage to the battery cells by being

discharged to excessively low voltages.

a stable, regulated output in the range of 5VDC 10ꢀ

(see Figure 2). The selection of the microcontroller

should take this into consideration. At the end of this turn

on period, the X3100 and X3101 “self-tunes” the output

of the voltage regulator to 5V+/-0.5ꢀ. As such, V

RGO

can be used as a reference voltage for the A/D converter

in the microcontroller. Repeated power up operations,

—Over-current protection (OCP)

In this case, pin 24 is referred to as “Over-current

protection (OCP)” (see section “Over-Current Protection”

on page 18). UVP/OCP turns off the FET to prevent

damage to the battery pack caused by excessive current

drain (e.g. as in the case of a surge current resulting

from a stalled disk drive).

consistently re-apply the same “tuned” value for V

.

RGO

Figure 1 shows a battery pack temperature sensor

implemented as a simple resistive voltage divider,

utilizing a thermistor (R ) and resistor (R ’). The voltage

T

V can be fed to the A/D input of a microcontroller and

T

used to measure and monitor the temperature of the

TYPICAL APPLICATION CIRCUIT

battery cells. R ’ should be chosen with consideration of

T

the dynamic resistance range of R as well as the input

The X3100 and X3101 have been designed to operate

correctly when used as connected in the Typical

Application Circuit (see Figure 1 on page 5).

T

voltage range of the microcontroller A/D input. An output

of the microcontroller can be used to turn on the

thermistor divider to allow periodic turn-on of the sensor.

This reduces power consumption since the resistor

string is not always drawing current.

The power MOSFET’s Q1 and Q2 are referred to as the

“Discharge FET” and “Charge FET,” respectively. Since

these FETs are p-channel devices, they will be ON when

Diode D3 is included to facilitate load monitoring in an

Over-current protection mode (see section “Over-

Current Protection” on page 18), while preventing the

ﬂow of current into pin OVP/LMON during normal

operation. The N-Channel transistor turns off this

function during the sleep mode.

the gates are at V , and OFF when the gates are at

SS

V

. As their names imply, the discharge FET is used to

CC

control cell discharge, while the charge FET is used to

control cell charge. Diode D1 allows the battery cells to

receive charge even if the Discharge FET is OFF, while

diode D2 allows the cells to discharge even if the charge

FET is OFF. D1 and D2 are integral to the Power FETs. It

should be noted that the cells can neither charge nor

discharge if both the charge FET and discharge FET are

OFF.

Resistor R

is connected across the gate and drain of

PU

the charge FET (Q2). The discharge FET Q1 is turned

off by the X3100 or X3101, and hence the voltage at pin

OVP/LMON will be (at maximum) equal to the voltage of

the battery terminal, minus one forward biased diode

Power to the X3100 or X3101 is applied to pin VCC via

diodes D6 and D7. These diodes allow the device to be

voltage drop (V –V ). Since the drain of Q2 is

P+ D7

connected to a higher potential (V ) a pull-up resistor

P+

Characteristics subject to change without notice. 4 of 40

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X3100/X3101 – Preliminary Information

Figure 1. Typical Application Circuit

Characteristics subject to change without notice. 5 of 40

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X3100/X3101 – Preliminary Information

(R ) in the order of 1MΩ should be used to ensure that

discharge cycles, and minimum/maximum conditions.

Battery pack manufacturing data as well as serial

number information can also be stored in the EEPROM

array. An SPI serial bus provides the communication link

to the EEPROM.

PU

the charge FET is completely turned OFF when OVP/

LMON=V

.

CC

The capacitors on the V

to V

inputs are used

CELL1

CELL4

in a ﬁrst order low pass ﬁlter conﬁguration, at the battery

cell voltage monitoring inputs (VCELL1–VCELL4) of the

X3100 or X3101. This ﬁlter is used to block any

unwanted interference signals from being inadvertently

injected into the monitor inputs. These interference

signals may result from:

A current sense resistor (R

) is used to measure

SENSE

and monitor the current ﬂowing into/out of the battery

terminals, and is used to protect the pack from over-

current conditions (see section “Over-Current

Protection” on page 18). R

is also used to

SENSE

externally monitor current via a microcontroller (see

section “Current Monitor Function” on page 20).

– Transients created at battery contacts when the bat-

tery pack is being connected/disconnected from the

charger or the host.

FETs Q4 and Q5 may be required on general purpose

I/Os of the microcontroller that connect outside of the

package. In some cases, without FETs, pull-up resistors

– Electrostatic discharge (ESD) from something/some-

one touching the battery contacts.

external to the pack force a voltage on the V pin of the

CC

– Unﬁltered noise that exists in the host device.

microcontroller during a pack sleep condition. This

voltage can affect the proper tuned voltage of the

X3100/X3101 regulator. These FETs should be turned-

on by the microcontroller. (See Figure 1.)

– RF signals which are induced into the battery pack

from the surrounding environment.

Such interference can cause the X3100 or X3101 to

operate in an unpredictable manner, or in extreme

cases, damage the device. As a guide, the capacitor

should be in the order of 0.01µF and the resistor, should

be in the order of 10KΩ. The capacitors should be of the

ceramic type. In order to minimize interference, PCB

tracks should be made as short and as wide as possible

to reduce their impedance. The battery cells should also

be placed as close to the X3100 or X3101 monitor inputs

as possible.

POWER ON SEQUENCE

Initial connection of the Li-Ion cells in the battery pack

will not normally power up the battery pack. Instead, the

X3100 or X3101 enters and remains in the SLEEP

mode. To exit the SLEEP mode, after the initial power up

sequence, or following any other SLEEP MODE, a

minimum of 16V (X3100 V

applied to the VCC pin, as would be the case during a

battery charge condition. (See Figure 2.)

) or 12V (X3101 V

) is

SLR

Resistors R

and the associated n-channel MOSFET’s

CB

When V

is applied to VCC, the analog select pins

SLR

(Q –Q ) are used for battery cell voltage balancing. The

6

9

(AS2-AS0) and the SPI communication pins (CS, CLK,

SI, SO) must be low, so the X3100 and X3101 power up

correctly into the normal operating mode. This can be

done by using a power-on reset circuit.

X3100 and X3101 provide internal drive circuitry which

allows the user to switch FETs Q –Q ON or OFF via

the microcontroller and SPI port (see section “Cell

Voltage Balance Control (CBC1-CBC4)” on page 11).

When any of the these FETs are switched ON, a

6

9

When entering the normal operating mode, either from

initial power up or following the SLEEP MODE, all bits in

the control register are zero. With UVPC and OVPC bits

at zero, the charge and discharge FETs are off. The

microcontroller must turn these on to activate the pack.

The microcontroller would typically check the voltage

and current levels prior to turning on the FETs via the

SPI port. The software should prevent turning on the

FETs throughout an initial measurement/calibration

current, limited by resistor R , ﬂows across the

CB

particular battery cell. In doing so, the user can control

the voltage across each individual battery cell. This is

important when using Li-Ion battery cells since

imbalances in cell voltages can, in time, greatly reduce

the usable capacity of the battery pack. Cell voltage

balancing may be implemented in various ways, but is

usually performed towards the end of cell charging

(“Top-of-charge method”). Values for R

according to the speciﬁc application.

will vary

period. The duration of this period is T +200ms or

CB

OV

T

+200ms, whichever is longer.

UV

The internal 4kbit EEPROM memory can be used to

store the cell characteristics for implementing such

functions as gas gauging, battery pack history, charge/

Characteristics subject to change without notice. 6 of 40

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X3100/X3101 – Preliminary Information

Figure 2. Power Up Timing (Initial Power Up or after Sleep Mode)

T

PUR

V

SLR

VCC

0V

5V 10ꢀ (Stable and Repeatable)

Tuned to 5V 0.5ꢀ

V

RGO

5V

V

RGO

0V

2ms (Typ.)

1

Voltage Regulator Output Status

(Internal Signal)

VRGS

0

T

OC

1

1 = X3100/1 in Over-Current Protection Mode

0 = X3100/1 NOT in Over-Current Protection Mode

Over-current Detection Status

(Internal Signal)

OCDS

1

1 = X3100/1 in Over-Current Protection Mode OR VRGO Not Yet Tuned

0 = X3100/1 NOT in Over-Current Protection Mode AND VRGO Tuned

Status Register Bit 0

VRGS+OCDS

0

T

+200ms

OV

1

Status Register Bit 2

0

(SWCEN=0) CCES+OVDS

1 = V

0 = V

< V OR X3100/1 in Over-charge Protection Mode

CE

CELL

> V OR X3100/1 NOT in Over-charge Protection Mode

CE

1

Status Register Bit 2

0

(SWCEN=1)

OVDS

1 = X3100/1 in Over-charge Protection Mode

0 = X3100/1 NOT in Over-charge Protection Mode

AS2_AS0

SPI PORT

T

+200ms OR T +200ms (whichever is longer)

UV

OV

Charge, Discharge FETs can be

turned on here.

Any Read or Write Operation, except

turn-on of FETs can start here.

Characteristics subject to change without notice. 7 of 40

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X3100/X3101 – Preliminary Information

CONFIGURATION REGISTER

Over-discharge Settings

VUV1 and VUV0 control the cell over-discharge (under

voltage threshold) level. See section “Over-discharge

Protection” on page 15.

The X3100 and X3101 can be conﬁgured for speciﬁc

user requirements using the Conﬁguration Register.

Table 1. Configuration Register Functionality

Table 5. Over-discharge Threshold Selection.

Configuration

Register Bits

VUV1 VUV0

Bit(s)

Name

Function

Operation

0-5

–

(don’t care)

X3100

X3101

=2.25V

(X3101 default)

Switch Cell Charge Enable

threshold function ON/OFF

V

6

7

SWCEN

CELLN

UV

0

V

=1.95V

UV

Set the number of Li-Ion battery

cells used (3 or 4)

0

1

0

V

=2.05V

=2.15V

=2.25V

V

=2.35V

=2.45V

UV

Select Cell Charge Enable

threshold

8-9

VCE1-VCE0

1

V

=2.55V

UV

(X3100 default)

10-11 VOC1-VOC0 Select over-current threshold

Select over-discharge (under

12-13 VUV1-VUV0

Over-current Settings

voltage) threshold

VOC1 and VOC0 control the pack over-current level.

See section “Over-Current Protection” on page 18.

Select over-charge voltage

14-15 VOV1-VOV0

threshold

Table 6. Over-Current Threshold Voltage Selection.

Configuration Register Bits

Table 2. Configuration Register—Upper Byte

15

14

13

12

11

10

9

8

VOC1

VOC0

Operation

VOV1 VOV0 VUV1 VUV0 VOC1 VOC0 VCE1 VCE0

X3100 Default = 30H; X3101 Default = 00H.

0

1

0

1

0

1

V

=0.075V (Default)

OC

V

=0.100V

=0.125V

=0.150V

OC

Table 3. Configuration Register—Lower Byte

7

6

5

4

3

2

1

0

CELLN SWCEN

x

Cell Charge Enable Settings

X3100 Default = C0H; X3101 Default = 40H.

VCE1, VCE0 and SWCEN control the pack charge

enable function. SWCEN enables or disables a circuit

that prevents charging if the cells are at too low a

voltage. VCE1 and VCE0 select the voltage that is

recognized as too low. See section “Sleep Mode” on

page 15.

Over-charge Voltage Settings

VOV1 and VOV0 control the cell over-charge level. See

section “Over-charge Protection” on page 13.

Table 4. Over-charge Voltage Threshold Selection

Table 7. Cell Charge Enable Function

Configuration Register

Bits

Configuration

Register Bit

VOV1

VOV0

Operation

= 4.20V (Default)

= 4.25V

SWCEN

Operation

0

1

0

1

0

1

V

OV

0

1

Charge enable function: ON

Charge enable function: OFF

= 4.30V

= 4.35V

Characteristics subject to change without notice. 8 of 40

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X3100/X3101 – Preliminary Information

Table 8. Cell Charging Threshold Voltage Selection.

Configuration Register Bits

Figure 3. Power up of Configuration Register

Configuration Register (SRAM)

Upper Byte

Lower Byte

VCE1

VCE0

Operation

= 0.5V

0

1

0

1

0

1

V

CE

Recall

= 0.80V

= 1.10V

= 1.40V

Shadow EEPROM

The conﬁguration register is designed for unlimited write

operations to SRAM, and a minimum of 1,000,000 store

operations to the EEPROM. Data retention is speciﬁed

to be greater than 100 years.

Cell Number Selection

The X3100 is designed to operate with four (4) Li-Ion

battery cells. The X3101 is designed to operate with

three (3) Li-Ion battery cells. The CELLN bit of the

conﬁguration register (Table 9) sets the number of cells

recognized. For the X3101, the value for CELLN should

always be zero.

It should be noted that the bits of the shadow EEPROM

are for the dedicated use of the conﬁguration register,

and are NOT part of the general purpose 4kbit

EEPROM array.

The WCFIG command writes to the conﬁguration

register, see Table 30 and section “X3100/X3101 SPI

Serial Communication” on page 22.

Table 9. Selection of Number of Battery Cells¹

Configuration

Register Bit

After writing to this register using a WCFIG instruction,

data will be stored only in the SRAM of the conﬁguration

register. In order to store data in shadow EEPROM, a

WREN instruction, followed by a EEWRITE to any

address of the 4kbit EEPROM memory array must

occur, see Figure 4. This sequence initiates an internal

nonvolatile write cycle which permits data to be stored

in the shadow EEPROM cells. It must be noted that

even though a EEWRITE is made to the general

purpose 4kbit EEPROM array, the value and address to

which it is written, is unimportant. If this procedure is not

followed, the conﬁguration register will power up to the

last previously stored values following a power down

sequence.

CELLN

Operation

1

0

4 Li-Ion battery cells (X3100 default)

3 Li-Ion battery cells (X3100 or X3101)

The conﬁguration register consists of 16 bits of

NOVRAM memory (Table 2, Table 3). This memory

features a high-speed static RAM (SRAM) overlaid bit-

for-bit with non-volatile “Shadow” EEPROM. An

automatic array recall operation reloads the contents of

the shadow EEPROM into the SRAM conﬁguration

register upon power-up (Figure 3).

1. In the case that the X3100 or X3101 is configured for use with

only three Li-Ion battery cells (i.e. CELLN=0), then VCELL4 (pin

7) MUST be tied to Vss (pin 9) to ensure correct operation.

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X3100/X3101 – Preliminary Information

Figure 4. Writing to Configuration Register

Since the control register is volatile, data will be lost

following a power down and power up sequence. The

default value of the control register on initial power up

or when exiting the SLEEP MODE is 00h (for both

upper and lower bytes respectively). The functions that

can be manipulated by the Control Register are shown

in Table 12.

Power Up

Data Recalled

from Shadow

EEPROM to SRAM

Conﬁguration Register

(SRAM=Old Value)

Table 12. Control Register Functionality

WCFIG (New Value)

Bit(s) Name

Function

Conﬁguration Register

(Sram=New Value)

0-4

5,6

7

–

(don’t care)

0, 0

SLP

Reserved—write 0 to these locations.

Select sleep mode.

Store

(New Value)

in Shadow

EEPROM

CSG1,

CSG0

NO

YES

8,9

Select current sense voltage gain

10

11

12

13

14

15

OVPC OVP control: switch pin OVP = V /V

CC SS

WREN

UVPC UVP control: switch pin UVP = V /V

CC SS

Write

Enable

Power Down

Power Up

CBC1 CB1 control: switch pin CB1 = V /V

CC SS

CBC2 CB2 control: switch pin CB2 = V /V

CC SS

Data Recalled

from Shadow

EEWRITE

CBC3 CB3 control: switch pin CB3 = V /V

CC SS

Write to

4kbit EEPROM

EEPROM to SRAM

CBC4 CB4 control: switch pin CB4 = V /V

CC SS

Conﬁguration Register

(SRAM=old value)

Sleep Control (SLP)

Setting the SLP bit to ‘1’ forces the X3100 or X3101 into

Power Down

Power Up

the sleep mode, if V

Mode” on page 15.

< V . See section “Sleep

CC

SLP

Data Recalled

from Shadow

EEPROM to SRAM

Table 13. Sleep Mode Selection

Conﬁguration Register

(SRAM=New Value)

Control Register Bits

SLP

Operation

CONTROL REGISTER

0

1

Normal operation mode

The Control Register is realized as two bytes of volatile

RAM (Table 10, Table 11). This register is written using

the WCNTR instruction, see Table 30 and section “X3100/

X3101 SPI Serial Communication” on page 22.

Device enters Sleep mode

Table 10. Control Register—Upper Byte

15

14

13

12

11

10

9

8

CBC4 CBC3 CBC2 CBC1 UVPC OVPC CSG1 CSG0

Table 11. Control Register—Lower Byte

7

6

5

4

3

2

1

0

SLP

0

x

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X3100/X3101 – Preliminary Information

Current Sense Gain (CSG1, CSG0)

Table 16. CB1—CB4 Control

These bits set the gain of the current sense ampliﬁer.

These are x10, x25, x80 and x160. For more detail, see

section “Current Monitor Function” on page 20.

Control Register Bits

CBC4 CBC3 CBC2 CBC1

Operation

Set CB1=V (ON)

x

1

0

x

1

0

x

1

0

x

1

0

x

CC

Table 14. Current Sense Gain Control

Control Register Bits

Set CB1=V (OFF)

SS

Set CB2=V (ON)

CC

Set CB2=V (OFF)

SS

CSG1

CSG0

Operation

Set CB3=V (ON)

CC

0

1

0

1

0

1

Set current sense gain=x10

Set current sense gain=x25

Set current sense gain=x80

Set current sense gain=x160

Set CB3=V (OFF)

SS

Set CB4=V (ON)

CC

Set CB4=V (OFF)

SS

CB1–CB4 can be controlled by using the WCNTR In-

struction to set bits CBC1–CBC4 in the control register

(Table 16).

Charge/Discharge Control (OVPC, UVPC)

The OVPC and UVPC bits allow control of cell charge

and discharge externally, via the SPI port. These bits

control the OVP/LMON and UVP/OCP pins, which in turn

control the external power FETs.

STATUS REGISTER

The status of the X3100 or X3101 can be veriﬁed by

using the RDSTAT command to read the contents of the

Status Register (Table 17).

Using P-channel power FETs ensures that the FET is

on when the pin voltage is low (Vss), and off when the

pin voltage is high (Vcc).

OVP/LMON and UVP/OCP can be controlled by using

the WCNTR Instruction to set bits OVPC and UVPC in

the Control register (See page 10).

Table 17. Status Register.

7

6

5

4

3

2

1

0

CCES+

OVDS

VRGS+

OCDS

0

UVDS

Table 15. UVP/OVP Control

Control Register Bits

The function of each bit in the status register is shown

in Table 18.

OVPC

UVPC

Operation

Pin OVP=V (FET ON)

1

0

x

1

0

SS

Bit 0 of the status register (VRGS+OCDS) actually

indicates the status of two conditions of the X3100 or

X3101. Voltage Regulator Status (VRGS) is an

internally generated signal which indicates that the

output of the Voltage Regulator (VRGO) has reached an

Pin OVP=V (FET OFF)

CC

Pin UVP=V (FET ON)

SS

Pin UVP=V (FET OFF)

CC

output of 5VDC

0.5ꢀ. In this case, the voltage

It is possible to set/change the values of OVPC and

UVPC during a protection mode. A change in the state

of the pins OVP/LMON and UVP/OCP, however, will not

take place until the device has returned from the

protection mode.

regulator is said to be “tuned”. Before the signal VRGS

goes low (i.e. before the voltage regulator is tuned), the

voltage at the output of the regulator is nominally 5VDC

10ꢀ (See section “Voltage Regulator” on page 21.)

Over-current Detection Status (OCDS) is another

internally generated signal which indicates whether or

not the X3100 or X3101 is in over-current protection

mode.

Cell Voltage Balance Control (CBC1-CBC4)

This function can be used to adjust individual battery

cell voltage during charging. Pins CB1–CB4 are used to

control external power switching devices. Cell voltage

balancing is achieved via the SPI port.

Signals VRGS and OCDS are logically OR’ed together

(VRGS+OCDS) and written to bit 0 of the status register

(See Table 18, Table 17 and Figure 2).

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X3100/X3101 – Preliminary Information

Bit 1 of the status register simply indicates whether or

not the X3100 or X3101 is in over-discharge protection

mode.

or not the X3100 or X3101 is in over-charge protection

mode.

When the cell charge enable function is switched ON

(conﬁguration bit SWCEN=0), the signals CCES and

OVDS are logically OR’ed (CCES+OVDS) and written to

bit 2 of the status register. If the cell charge enable

function is switched OFF (conﬁguration bit SWCEN=1),

then bit 2 of the status register effectively only represents

information about the over-charge status (OVDS) of the

X3100 or X3101 (See Table 18, Table 17 and Figure 2).

Bit 2 of the status register (CCES+OVDS) indicates the

status of two conditions of the X3100 or X3101. Cell

Charge Enable Status (CCES) is an internally generated

signal which indicates the status of any cell voltage

(V

) with respect to the Cell Charge Enable Voltage

CELL

(V ). Over-charge Voltage Detection Status (OVDS) is

CE

an internally generated signal which indicates whether

Table 18. Status Register Functionality.

Bit(s)

Name

Description

Case

Status

Interpretation

not yet tuned (V =5V 10ꢀ) OR

X3100/X3101 in over-current protection mode.

Voltage regulator

status

V

RGO

1

0

VRGS+OCDS

+

-

V

tuned (V =5V 0.5ꢀ) AND

RGO

Over-current

detection status

0

X3100/X3101 NOT in over-current protection mode.

1

0

X3100/X3101 in over-discharge protection mode

Over-discharge

detection status

1

UVDS

-

X3100/X3101 NOT in over-discharge protection mode

V

< V OR

CE

CELL

1

0

X3100/X3101 in over-charge protection mode

Cell charge

enable status

SWCEN =0^†

V

> V AND

CELL

CE

2

CCES+OVDS

+

X3100/X3101 NOT in over-charge protection mode

X3100/X3101 in over-charge protection mode

X3100/X3101 NOT in over-charge protection mode

Not used (always return zero)

Over-charge

1

0

detection status

SWCEN=1^†

-

3–7

-

†

Notes: This bit is set in the conﬁguration register.

X3100/X3101 INTERNAL PROTECTION FUNCTIONS

stages or when cells with slightly different

characteristics are used in an existing design.

The X3100 and the X3101 provide periodic monitoring

(see section “Periodic Protection Monitoring” on page

12) for over-charge and over-discharge states and

continuous monitoring for an over-current state. It has

automatic shutdown when a protection mode is

encountered, as well as automatic return after the

device is released from a protection mode. When

sampling voltages through the analog port (Monitor

Mode), over-charge and over-discharge protection

monitoring is also performed on a continuous basis.

Delay times for the detection of, and release from

protection modes (T , T /T

, and T /T

OV

UV UVR

OC OCR

respectively) can be individually varied by setting the

values of external capacitors connected to pins OVT,

UVT, OCT.

Periodic Protection Monitoring

In normal operation, the analog select pins are set such

that AS2=L, AS1=L, AS0=L. In this mode the X3100 and

X3101 conserve power by sampling the cells for over or

over-discharge conditions.

Voltage thresholds for each of these protection modes

(V , V , and V respectively) can be individually

OV

UV

OC

selected via software and stored in an internal non-

volatile register. This feature allows the user to avoid the

restrictions of mask programmed voltage thresholds, and

is especially useful during prototype/evaluation design

In this state over-charge and over-discharge protection

circuitry are usually off, but are periodically switched on

by the internal Protection Sample Rate Timer (PSRT). The

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X3100/X3101 – Preliminary Information

over-charge and over-discharge protection circuitry is on

for approximately 2ms in each 125ms period. Over-

current monitoring is continuous. In monitor mode (see

page 20) over-charge and over-discharge monitoring is

also continuous.

A typical delay time is shown in Table 10. The delay T

OV

that results from a particular capacitance C , can be

OV

approximated by the following linear equation:

T

(s) ≈ 10 x C (µF).

OV

Table 19. Typical over-charge detection time

Over-charge Protection

Symbol

C

Delay

The X3100 and X3101 monitor the voltage on each

OV

battery cell (V

time exceeding T , then the Charge FET will be

). If for any cell, V

> V

for a

T

0.1µF

1.0s (Typ)

CELL

OV

switched OFF (OVP/LMON=V ). The device has now

CC

The device further continues to monitor the battery cell

voltages, and is released from over-charge protection

entered Over-charge protection mode (Figure 5). The

status of the discharge FET (via pin UVP) will remain

unaffected.

mode when V

< V

, for all cells. When the X3100

CELL

OVR

or X3101 is released from over-charge protection

mode, the charge FET is automatically switched ON

While in over-charge protection mode, it is possible to

change the state of the OVPC bit in the control register

such that OVP/LMON=Vss (Charge FET=ON).

Although the OVPC bit in the control register can be

changed, the change will not be seen at pin OVP until

the X3100 or X3101 returns from over-charge

protection mode.

(OVP/LMON=V ). When the device returns from over-

SS

charge protection mode, the status of the discharge

FET (pin UVP/OCP) remains unaffected.

The value of V

can be selected from the values

OV

shown in Table 4 by setting bits VOV1, VOV0.These bits

are set by using the WCFIG instruction to write to the

conﬁguration register.

The over-charge detection delay T , is varied using a

OV

capacitor (C ) connected between pin OVT and GND.

OV

Figure 5. Over-charge Protection Mode—Event Diagram

Normal Operation Mode

Over-charge

Normal Operation Mode

Protection

Mode

V

OV

V

OVR

V

CELL

T

OV

V

CC

OVP/LMON

Event

V

SS

3

2

0

1

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Table 20. Over-charge Protection Mode—Event Diagram Description

Event

Event Description

—Discharge FET is ON (UVP/OCP=V ).

SS

—Charge FET is ON (OVP/LMON=V ), and hence battery cells are permitted to receive charge.

SS

[0,1)

—All cell voltages (V

-V

) are below the over-charge voltage threshold (V ).

CELL CELL4 OV

—The device is in normal operation mode (i.e. not in a protection mode).

—The voltage of one or more of the battery cells (V ), exceeds V

—The internal over-charge detection delay timer begins counting down.

.

OV

CELL

[1]

—The device is still in normal operation mode

The internal over-charge detection delay timer continues counting for T seconds.

OV

(1,2)

The internal over-charge detection delay timer times out

AND

still exceeds V

OV.

V

CELL

[2]

—Therefore, the internal over-charge sense circuitry switches the charge FET OFF (OVP/LMON=Vcc).

—The device has now entered over-charge protection mode.

While in over-charge protection mode:

—The battery cells are permitted to discharge via the discharge FET, and diode D across the charge FET

2

—The X3100 or X3101 monitors the voltages V

-V

to determine whether or not they have all fallen

(2,3)

[3]

CELL1 CELL4

below the “Return from over-charge threshold” (V

—(It is possible to change the status of UVP/OCP or OVP/LMON using the control register)

).

OVR

—All cell voltages fall below V —The device is now in normal operation mode.

OVR

—The X3100/X3101 automatically switches charge FET=ON (OVP/LMON=Vss)

—The status of the discharge FET remains unaffected.

—Charging of the battery cells can now resume.

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Over-discharge Protection

A sleep mode can be induced by the user, by setting

the SLP bit in the control register (Table 13) using the

WCNTR Instruction.

If V

< V , for a time exceeding T , the cells are

UV UV

CELL

said to be in a over-discharge state (Figure 6). In this

instance, the X3100 and X3101 automatically switch

the discharge FET OFF (UVP/OCP=Vcc), and then

enter sleep mode.

In sleep mode, power to all internal circuitry is switched

off, minimizing the current drawn by the device to 1µA

(max). In this state, the discharge FET and the charge

FET are switched OFF (OVP/LMON=V

and UVP/

CC

The over-discharge (under-voltage) value, V , can be

UV

OCP=V ), and the 5VDC regulated output (V

) is

CC

RGO

selected from the values shown in Table 5 by setting

bits VUV1, VUV0 in the conﬁguration register. These

bits are set using the WCFIG command. Once in the

sleep mode, the following steps must occur before the

X3100 or X3101 allows the battery cells to discharge:

0V. Control of UVP/OCP and OVP/LMON via bits UVPC

and OVPC in the control register is also prohibited.

The device returns from sleep mode when V

≥ V

.

CC

SLR

(e.g. when the battery terminals are connected to a

battery charger). In this case, the X3100 or the X3101

restores the 5VDC regulated output (section “Voltage

Regulator” on page 21), and communication via the SPI

port resumes.

– The X3100 and X3101 must wake from sleep mode

(see section “Voltage Regulator” on page 21).

– The charge FET must be switched ON by the micro-

controller (OVP/LMON=V ), via the control register

SS

If the Cell Charge Enable function is enabled when V

(see section “Control Register Functionality” on page

10).

CC

rises above V

, the X3100 and X3101 internally

SLR

veriﬁes that the individual battery cell voltages (V

are larger than the cell charge enable voltage (V

before allowing the FETs to be turned on. The value

)

CELL

– All battery cells must satisfy the condition: V

>

CELL

CE

V

for a time exceeding T

.

UVR

of V is selected by using the WCFIG command to set

bits VCE1–VCE0 in the conﬁguration register.

– The discharge FET must be switched ON by the micro-

CE

controller (UVP/OCP=V ), via the control register

SS

(see section “Control Register Functionality” on page

10)

Only if the condition “V

the state of charge and discharge FETs be changed

via the control register. Otherwise, if V < V for

any battery cell then both the Charge FET and the

discharge FET are OFF (OVP/LMON=Vcc and UVP/

> V ” is satisﬁed can

CE

CELL

The times T /T

are varied using a capacitor (C

)

CELL

CE

UV UVR

UV

connected between pin UVT and GND (Table 13). The

delay T that results from a particular capacitance C

,

UV

OCP=V ). Thus both charge and discharge of the

can be approximated by the following linear equation:

CC

battery cells via terminals P+ / P- is prohibited¹.

T

(s) ≈ 10 x C (µF)

UV

The cell charging threshold function can be switched

ON or OFF by the user, by setting bit SWCEN in the

conﬁguration register (Table 7) using the WCFIG

command. In the case that this cell charge enable

T

(ms) ≈ 70 x C (µF)

UV

UVR

Table 21. Typical Over-discharge Delay Times

function is switched OFF, then V

0V.

is effectively set to

Symbol

Description

C

Delay

CE

UV

Over-discharge

detection delay

T

0.1µF

1.0s (Typ)

UV

Neither the X3100 nor the X3101 enter sleep mode

(automatically or manually, by setting the SLP bit) if V

Over-discharge

release time

CC

T

7ms (Typ)

UVR

≥ V

. This is to ensure that the device does not go

SLR

into a sleep mode while the battery cells are at a high

voltage (e.g. during cell charging).

Sleep Mode

The X3100 or X3101 can enter sleep mode in two

ways:

i) The device enters the over-discharge protection mode.

ii) The user sends the device into sleep mode using the

control register.

1. In this case, charging of the battery may resume ONLY if the cell

charge enable function is switched OFF by setting bit SWCEN =

1 in the configuration register (See Above, “Configuration

Register Functionality” on page 8).

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Figure 6. Over-discharge Protection Mode—Event Diagram

V

SLR

VCC

Cell Charge Prohibited if SWCEN=0

AND V < V

CELL

CE

VCELL

0.7V

V

UVR

V

UV

T

UVR

V

CE

T

UV

V

CC

Note 3

Over-discharge Protection Mode

UVP/OCP

V

SS

The Longer of TOV+200ms OR TUV+200ms

V

CC

Note 1, 2

V

SS

OVP/LMON

RGO

5V

0V

Sleep Mode

Event

2

5

3

4

1

0

Note 1: If SWEN=0 and V

< V , then OVP/LMON stays high and charging is prohibited.

CE

CELL

Note 2: OVP/LMON stays high until the microcontroller writes a “1” to the OVPC bit in the control register.This sets the signal low, which turns on the

charge FET. It cannot be turned on prior to this time.

Note 3: UVP/OCP stays high until the microcontroller writes a “1” to the UVPC bit in the control register.This sets the signal low, which turns on the

discharge FET.The FET cannot be turned on prior to this time.

Table 22. Over-discharge Protection Mode—Event Diagram Description

Event

Event Description

—Charge FET is ON (OVP/LMON=V

—Discharge FET is ON (UVP/OCP=V ), and hence battery cells are permitted to discharge.

)

SS

[0,1)

—All cell voltages (VCELL -VCELL ) are above the Over-discharge threshold voltage (V ).

1

4

UV

—The device is in normal operation mode (i.e. not in a protection mode).

—The voltage of one or more of the battery cells (V ), falls below V

.

UV

CELL

[1]

—The internal over-discharge detection delay timer begins counting down.

—The device is still in normal operation mode

The internal over-discharge detection delay timer continues counting for T seconds.

UV

(1,2)

—The internal over-discharge detection delay timer times out, AND V

is still below V

UV.

CELL

—The internal over-discharge sense circuitry switches the discharge FET OFF (UVP/OCP=Vcc).

[2]

—The charge FET is switched OFF (OVP/LMON=V ).

CC

—The device has now entered over-discharge protection mode.

—At the same time, the device enters sleep mode (See section “Voltage Regulator” on page 21).

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Table 22. Over-discharge Protection Mode—Event Diagram Description (Continued)

Event

Event Description

While device is in sleep (in over-discharge protection) mode:

—The power to ALL internal circuits is switched OFF limiting power consumption to less than 1µA.

—The output of the 5VDC voltage regulator (RGO) is 0V.

(2,3)

—Access to the X3100/X3101 via the SPI port is NOT possible.

Return from sleep mode (but still in over-discharge protection mode):

—Vcc rises above the “Return from Sleep mode threshold Voltage” (V

)—This would normally occur in the

SLR

case that the battery pack was connected to a charger. The X3100/X3101 is now powered via P+/P-, and

not the battery pack cells.

—Power is returned to ALL internal circuitry

[3]

—5VDC output is returned to the regulator output (RGO).

—Access is enabled to the X3100/X3101 via the SPI port.

—The status of the discharge FET remains OFF (It is possible to change the status of UVPC in the control reg-

ister, although it will have no effect at this time).

—The X3100/X3101 initiates a reset operation that takes the longer of

T

+200ms or T +200ms to complete. Do not write to the FET control bits

OV

UV

If the cell charge enable func-

tion is switched ON

during this time.

—The charge FET is switched On (OVP/LMON=Vss) by the microcontroller by

writing a “1” to the OVPC bit in the control register.

—The battery cells now receive charge via the charge FET and diode D1 across

the discharge FET (which is OFF).

AND V

> V

CELL

CE

OR

Charge enable function is

switched OFF

(3,4)

—The X3100/X3101 monitors the V

voltage to determine whether or not it

CELL

has risen above V

.

UVR

—Charge/discharge of the battery cells via P+ is no longer permitted (Charge

FET and discharge FET are held OFF).

—(Charging may re-commence only when the Cell Charge Enable function is

switched OFF - See Sections: “Configuration Register” page 4, and “Sleep

mode” page 17.)

If the cell charge enable func-

tion is switched ON

AND

V

< V

CELL

CE

—The voltage of all of the battery cells (V

—The internal Over-discharge release timer begins counting down.

—The X3100/X3101 is still in over-discharge protection mode.

), have risen above V

.

CELL

UVR

[4]

—The internal over-discharge release timer continues counting for t

—The X3100/X3101 should be in monitor mode (AS2:AS0 not all low) for recovery time based on t

wise recovery is based on two successive samples about 120ms apart.

seconds.

UVR

(4,5)

. Other-

UVR

—The internal over-discharge release timer times out, AND V

is still above V

UVR.

CELL

—The device returns from over-discharge protection mode, and is now in normal operation mode.

—The Charger voltage can now drop below VSLR and the X3100/X3101 will not go back to sleep.

—The discharge FET is can now be switched ON (UVP/OCP=V ) by the microcontroller by writing a “1” to

SS

[5]

the UVPC bit of the control register.

—The status of the charge FET remains unaffected (ON)

—The battery cells continue to receive charge via the charge FET and discharge FET (both ON).

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X3100/X3101 – Preliminary Information

Over-Current Protection

If the load resistance > 150kΩ (I

=0µA) for a time

LMON

exceeding T

, then the X3100 or X3101 is released

OCR

In addition to monitoring the battery cell voltages, the

from over-current protection mode. The discharge FET

is then automatically switched ON (UVP/OCP=Vss) by

the X3100 or X3101, unless the status of UVP/OCP has

been changed in control register (by manipulating bit

UVPC) during the over-current protection mode.

X3100 and X3101 continually monitor the voltage VCS

21

(VCS –VCS ) across the current sense resistor

2

1

(R

). If VCS > V

for a time exceeding T

,

SENSE

21

OC

then the device enters over-current protection mode

(Figure 7). In this mode, the X3100 and X3101

automatically switch the discharge FET OFF (UVP/

OCP=Vcc) and hence prevent current from ﬂowing

through the terminals P+ and P-.

T

/T

are varied using a capacitor (C ) connected

OC OCR OC

between pin OCT and VSS. A list of typical delay times

is shown in Table 23. Note that the value C

larger than 1nF.

should be

OC

Figure 7. Over-Current Protection

The delay T

and T

that results from a particular

OC

OCR

capacitance C

equations:

can be approximated by the following

OC

P+

I

LMON

Q2

D1

T

(ms) ≈ 10,000 x C (µF)

OC

V

RGO

T

(ms) ≈ 10,000 x C (µF)

OC

OCR

Q10

Load

OVP/LMON

Table 23. Typical Over-Current Delay Times

X3100/X3101

Symbol

Description

Over-current

detection delay

C

Delay

OC

FET Control

Circuitry

T

0.001µF

10ms (Typ)

OC

Over-current

release time

T

10ms (Typ)

OCR

VSS

VCS1

VCS2

P-

The value of V

can be selected from the values

OC

R

SENSE

shown in Table 6, by setting bits VOC1, VOC0 in the

conﬁguration register using the WCFIG command.

The 5VDC voltage regulator output (V

active during an over-current protection mode.

) is always

RGO

Note: If the Charge FET is turned off, due to an

overcharge condition or by direct command from the

microcontroller, the cells are not in an undervoltage

condition and the pack has a load, then excessive

current may ﬂow through Q10 and diode D1. To

eliminate this effect, the gate of Q10 can be turned off by

the microcontroller through an unused X3101 cell

balance output, or directly from a microcontroller port

Once the device enters over-current protection mode,

the X3100 and X3101 begin a load monitor state. In the

load monitor state, a small current (I

=7.5µA typ.) is

LMON

passed out of pin OVP/LMON in order to determine the

load resistance. The load resistance is the impedance

seen looking out of pin OVP/LMON, between terminal

P+ and pin VSS (See Figure 7.)

instead of connecting to V

.

RGO

Characteristics subject to change without notice. 18 of 40

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X3100/X3101 – Preliminary Information

Figure 8. Over-Current Protection Mode—Event Diagram

Over-Current Protection Mode

Normal Operation Mode

B+

P+

P+ = (RLOAD+RSENSE) x ILMON

V

OC

Voc

VCS

V

2

SS

T

OCR

T

OC

V

CC

UVP/OCP

Event

SS

4

0

3

1

2

Table 24. Over-Current Protection Mode—Event Diagram Description

Event

Event Description

—Discharge FET is ON (OCP=Vss). Battery cells are permitted to discharge.

[0,1)

—VCS (VCS –VCS ) is less than the over-current threshold voltage (V ).

21

2

1

OC

—The device is in normal operation mode (i.e. not in a protection mode).

—Excessive current flows through the battery terminals P+, dropping the voltage. (See Figure 8.).

—The positive battery terminal voltage (P+) falls, and VCS exceeds V

21

—The internal over-current detection delay timer begins counting down.

.

OC

[1]

—The device is still in Normal Operation Mode

The internal Over-current detection delay timer continues counting for T

OC

seconds.

(1,2)

—The internal over-current detection delay timer times out, AND VCS is still above V

21

OC.

—The internal over-current sense circuitry switches the discharge FET OFF (UVP/OCP=Vcc).

—The device now begins a load monitor state by passing a small test current (I =7.5µA) out of pin

LMON

OVP/LMON. This senses if an over-current condition (i.e. if the load resistance < 150kΩ) still exists

across P+/P-.

[2]

—The device has now entered over-current protection mode.

—It is possible to change the status of UVPC and OVPC in the control register, although the status of pins

UVP/OCP and OVP/LMON will not change until the device has returned from over-current protection

mode.

—The X3100/X3101 now continuously monitors the load resistance to detect whether or not an over-

current condition is still present across the battery terminals P+/P-.

(2,3)

Characteristics subject to change without notice. 19 of 40

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X3100/X3101 – Preliminary Information

Table 24. Over-Current Protection Mode—Event Diagram Description (Continued)

Event

[3]

Event Description

—The device detects the load resistance has risen above 250kΩ.

—Voltages P+ and VCS return to their normal levels.

21

—The test current from pin OVP/LMON is stopped (I

=0µA)

LMON

—The device has now returned from the load monitor state

—The internal over-current release time timer begins counting down.

—Device is still in over-current protection mode.

The internal over-current release timer continues counting for T

seconds.

(3,4)

[4]

OCR

—The internal over-current release timer times out, and VCS is still below V

21

OC.

—The device returns from over-current protection mode, and is now in normal operation mode.

—The discharge FET is automatically switched ON (UVP/OCP=Vss)—unless the status of UVPC has

been changed in the control register during the over-current protection mode.

—The status of the charge FET remains unaffected.

—Discharge of the battery cells is once again possible.

MONITOR MODE

Since the value of the sense resistor (R

) is small

SENSE

(typically in the order of tens of mΩ), and since the

Analog Multiplexer Selection

resolution of various A/D converters may vary, the

voltage across R

internally with a gain of between 10 and 160, and output

to pin AO (Figure 9).

(VCS and VCS ) is ampliﬁed

SENSE

1 2

The X3100 and X3101 can be used to externally monitor

individual battery cell voltages, and battery current.

Each quantity can be monitored at the analog output pin

(AO), and is selected using the analog select (AS0–AS2)

pins (Table 25). Also, see Figure 9.

Figure 9. X3100/X3101 Monitor Circuit

Table 25. AO Selection Map

Cell 1 Voltage

AS2 AS1 AS0

AO output

Voltage

Cell 2 Voltage

Level

(1)

L

H

L

V

SS

Cell 3 Voltage

Shifters

AS0

AS1

AS2

Cell 4 Voltage

VCELL –VCELL (VCELL

)

1

2

12

23

34

L

H

L

VCELL –VCELL (VCELL

2 3

AO

L

H

L

VCELL –VCELL (VCELL

3 4

2.5V

OP1

+

R2

H

VCELL –Vss (VCELL )

4

(2)

L

H

L

VCS –VCS (VCS )

12

-

1

2

R2

(2)

R1

H

VCS2–VCS (VCS )

1 21

S0

R1

H

V

SS

SCL

CS

SI

Conﬁg

Register

Gain

Setting

SPI

I/F

Notes: (1) This is the normal state of the X3100 or X3101. While in

this state Over-charge and Over-discharge Protection

conditions are periodically monitored (See “Periodic Pro-

tection Monitoring” on page 12.)

CSG1CSG0

(2) VCS , VCS are read at AO with respect to a DC bias

Cross-Bar

Switch

1

2

voltage of 2.5V (See section “Current Monitor Function”

Over-Current

Protection

on page 20).

X3100/X3101

Current Monitor Function

The voltages monitored at pins VCS and VCS can be

VCS

2

1

2

P-

used to calculate current ﬂowing through the battery

terminals, using an off-board microcontroller with an A/D.

The internal gain of the X3100 or X3101 current sense

voltage ampliﬁer can be selected by using the WCNTR

R

SENSE

Instruction to set bits CSG1 and CSG0 in the control

register (Table 14). The CSG1 and CSG0 bits select one

Characteristics subject to change without notice. 20 of 40

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X3100/X3101 – Preliminary Information

of four input resistors to Op Amp OP1. The feedback

resistors remain constant. This ratio of input to feedback

resistors determines the gain. Putting external resistors

in series with the inputs reduces the gain of the ampliﬁer.

2.5V (i.e. the threshold voltage for the FET), Q2 switches

ON, shorting VCC to the base of Q1. Since the base

voltage of Q1 is now higher than the emitter voltage, Q1

switches OFF, and hence the supply current goes to zero.

VCS1 and VCS2 are read at AO with respect to a DC

bias voltage of 2.5V. Therefore, the voltage range of

Typical values for R

In order to protect the voltage regulator circuitry from

and I

are shown in Table 27.

LMT

VCS

and VCS

changes depending upon the

damage in case of a short-circuit, R

always be used.

≥ 10Ω should

12

21

LMT

direction of current ﬂow (i.e. battery cells are in Charge

or Discharge—Table 21).

Table 27. Typical Values for R

and I

LMT

Table 26. AO Voltage Range for VCS₁₂and VCS₂₁

R

Voltage Regulator Current Limit (I

)

LMT

AO

Cell State

Charge

AO Voltage Range

2.5V ≤ AO ≤ 5.0V

0V ≤ AO ≤ 2.5V

2.5V ≤ AO ≤ 5.0V

10Ω

25Ω

50Ω

250mA 50ꢀ (Typical)

VCS

12

100mA 50ꢀ (Typical)

VCS

Discharge

Charge

12

50mA 50ꢀ (Typical)

21

When choosing the value of R

, the drive limitations

VCS

Discharge

LMT

of the PNP transistor used should also be taken into

consideration. The transistor should have a gain of at

least 100 to support an output current of 250mA.

By calculating the difference of VCS and VCS the

12

21

offset voltage of the internal op-amp circuitry is

cancelled. This allows for the accurate calculation of

current ﬂow into and out of the battery cells.

Figure 10. Voltage Regulator Operation

Pack current is calculated using the following formula:

VCC

Un-Regulated

To Internal Voltage

Voltage

(VCS₁₂– VCS₂₁

)

Regulating Circuitry

Input

Pack Current = ---------------------------------------------------------------------------------------------------------

(2)(gain setting)(current sense resistor)

R

LMT

X3100/X3101

RGP

RGC

Tuning

VOLTAGE REGULATOR

Q2

I

LMT

The X3100 and X3101 are able to supply peripheral

devices with a regulated 5VDC 0.5ꢀ output at pin

RGO. The voltage regulator should be configured

externally as shown in Figure 10.

5VDC

Precision

+

Voltage

_

Q1

Reference

OP1

The non-inverting input of OP1 is fed with a high

precision 5VDC supply. The voltage at the output of the

Regulated

5VDC Output

voltage regulator (V

) is compared to this 5V

RGO

reference via the inverting input of OP1. The output of

OP1 in turn drives the regulator pnp transistor (Q1). The

negative feedback at the regulator output maintains the

voltage at 5VDC 0.5ꢀ (including ripple) despite

changes in load, and differences in regulator transistors.

V

0.1

µF

RGO

4KBIT EEPROM MEMORY

The X3100 and X3101 contain a CMOS 4k-bit serial

EEPROM, internally organized as 512 x 8 bits. This

memory is accessible via the SPI port, and features the

IDLock function.

When power is applied to pin VCC of the X3100 or

X3101, V

is regulated to 5VDC 10ꢀ for a nominal

RGO

time of T +2ms. During this time period, V

is

OC

RGO

“tuned” to attain a ﬁnal value of 5VDC 0.5ꢀ (Figure 2).

The 4kbit EEPROM array can be accessed by the SPI

port at any time, even during a protection mode, except

during sleep mode. After power is applied to VCC of the

X3100 or X3101, EEREAD and EEWRITE Instructions

The maximum current that can ﬂow from the voltage

regulator (I

) is controlled by the current limiting

LMT

resistor (R

) connected between RGP and VCC. When

LMT

the voltage across VCC and RGP reaches a nominal

Characteristics subject to change without notice. 21 of 40

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X3100/X3101 – Preliminary Information

can be executed only after times t

(power up to read

and must be written as zeroes. Bringing CS HIGH after

the two byte IDLock instruction initiates a nonvolatile write

to the status register. Writing more than one byte to the

status register will overwrite the previously written

IDLock byte.

PUR

time) and t

(power up to write time) respectively.

PUW

IDLock is a programmable locking mechanism which

allows the user to lock data in different portions of the

EEPROM memory space, ranging from as little as one

page to as much as 1/2 of the total array. This is useful

for storing information such as battery pack serial

number, manufacturing codes, battery cell chemistry

data, or cell characteristics.

Once an IDLock instruction has been completed, that

IDLock setup is held in a nonvolatile IDLock Register

(Table 29) until the next IDLock instruction is issued. The

sections of the memory array that are IDLocked can be

read but not written until IDLock is removed or changed.

EEPROM Write Enable Latch

Table 29. IDLock Register

The X3100 and X3101 contain an EEPROM “Write

Enable” latch. This latch must be SET before a write to

EEPROM operation is initiated. The WREN instruction

will set the latch and the WRDI instruction will reset the

latch (Figure 11). This latch is automatically reset upon a

power-up condition and after the completion of a byte or

page write cycle.

7

6

5

4

3

2

1

0

IDL2 IDL1

IDL0

Note: Bits [7:3] speciﬁed to be “0’s”

X3100/X3101 SPI SERIAL COMMUNICATION

The X3100 and X3101 are designed to interface directly

with the synchronous Serial Peripheral Interface (SPI) of

many popular microcontroller families. This interface

uses four signals, CS, SCK, SI and SO. The signal CS

when low, enables communications with the device. The

SI pin carries the input signal and SO provides the

output signal. SCK clocks data in or out. The X3100 and

X3101 operate in SPI mode 0 which requires SCK to be

normally low when not transferring data. It also speciﬁes

that the rising edge of SCK clocks data into the device,

while the falling edge of SCK clocks data out.

IDLock Memory

Xicor’s IDLock memory provides a ﬂexible mechanism to

store and lock battery cell/pack information. There are

seven distinct IDLock memory areas within the array

which vary in size from one page to as much as half of

the entire array.

Prior to any attempt to perform an IDLock operation, the

WREN instruction must ﬁrst be issued. This instruction

sets the “Write Enable” latch and allows the part to

respond to an IDLock sequence. The EEPROM memory

may then be IDLocked by writing the SET IDL instruction

(Table 30 and Figure 19), followed by the IDLock

protection byte.

This SPI port is used to set the various internal registers,

write to the EEPROM array, and select various device

functions.

The X3100 and X3101 contain an 8-bit instruction

register. It is accessed by clocking data into the SI input.

CS must be LOW during the entire operation. Table 30

contains a list of the instructions and their opcodes. All

instructions, addresses and data are transferred MSB

ﬁrst.

Table 28. IDLock Partition Byte Definition

IDLock Protection

Bytes

EEPROM Memory Address

IDLocked

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

0000 0101

0000 0110

0000 0111

None

000h–07Fh

080h–0FFh

100h–17Fh

180h–1FFh

000h–0FFh

000h–00Fh

1F0h–1FFh

Data input is sampled on the ﬁrst rising edge of SCK

after CS goes LOW. SCK is static, allowing the user to

stop the clock, and then start it again to resume

operations where left off.

The IDLock protection byte contains the IDLock bits

IDL2-IDL0, which deﬁnes the particular partition to be

locked (Table 28). The rest of the bits [7:3] are unused

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X3100/X3101 – Preliminary Information

Table 30. X3100/X3101 Instruction Set

Instruction

Name

Instruction

Format*

Description

WREN

WRDI

0000 0110

0000 0100

0000 0010

0000 0101

0000 0011

Set the write enable latch (write enable operation)—Figure 11

Reset the write enable latch (write disable operation)—Figure 11

Write command followed by address/data (4kbit EEPROM)—Figure 12, Figure 13

Reads IDLock settings & status of EEPROM EEWRITE instruction—Figure 14

Read operation followed by address (for 4kbit EEPROM)—Figure 15

EEWRITE

EEREAD STAT

EEREAD

Write to configuration register followed by two bytes of data—Figure 4, Figure 16.

Data stored in SRAM only and will power-up to previous settings—Figure 3

WCFIG

0000 1001

WCNTR

RDSTAT

SET IDL

0000 1010

0000 1011

0000 0001

Write to control register, followed by two bytes of data—Figure 17

Read contents of status register—Figure 18

Set EEPROM ID lock partition followed by partition byte—Figure 19

*Instructions have the MSB in leftmost position and are transferred MSB first.

Write Enable/Write Disable (WREN/WRDI)

operation to proceed. The WRDI command resets the

internal latch if the system decides to abort a write

operation. See Figure 11.

Any write to a nonvolatile array or register, requires the

WREN command be sent prior to the write command.

This command sets an internal latch allowing the write

Figure 11. EEPROM Write Enable Latch (WREN/WRDI) Operation Sequence

CS

0

1

2

3

4

5

6

7

WREN

SCK

Instruction

(1 Byte)

SI

High Impedance

WRDI

SO

Characteristics subject to change without notice. 23 of 40

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X3100/X3101 – Preliminary Information

EEPROM Write Sequence (EEWRITE)

to be written is clocked in. If it is brought HIGH at any

other time, the write operation will not be completed.

Refer to Figure 12 and Figure 13 for detailed illustration

of the write sequences and time frames in which CS

going HIGH are valid.

Prior to any attempt to write data into the EEPROM of

the X3100 or X3101, the “Write Enable” latch must ﬁrst

be set by issuing the WREN instruction (See Table 30

and Figure 11). CS is ﬁrst taken LOW. Then the WREN

instruction is clocked into the X3100 or X3101. After all

eight bits of the instruction are transmitted, CS must

then be taken HIGH. If the user continues the write

operation without taking CS HIGH after issuing the

WREN instruction, the write operation will be ignored.

EEPROM Read Status Operation (EEREAD STAT)

If there is not a nonvolatile write in progress, the

EEREAD STAT instruction returns the IDLock byte from

the IDLock register which contains the IDLock bits IDL2-

IDL0 (Table 29). The IDLock bits deﬁne the IDLock

condition (Table 28). The other bits are reserved and will

return‘0’when read.

To write data to the EEPROM memory array, the user

issues the EEWRITE instruction, followed by the 16 bit

address and the data to be written. Only the last 9 bits of

the address are used and bits [15:9] are speciﬁed to be

zeroes. This is minimally a thirty-two clock operation. CS

must go LOW and remain LOW for the duration of the

operation. The host may continue to write up to 16 bytes

of data to the X3100 or X3101. The only restriction is the

16 bytes must reside on the same page. If the address

counter reaches the end of the page and the clock

continues, the counter will “roll over” to the ﬁrst address

of the page and overwrite any data that may have been

previously written.

If a nonvolatile write to the EEPROM (i.e. EEWRITE

instruction) is in progress, the EEREAD STAT returns a

HIGH on SO. When the nonvolatile write cycle in the

EEPROM is completed, the status register data is read

out.

Clocking SCK is valid during a nonvolatile write in

progress, but is not necessary. If the SCK line is clocked,

the pointer to the status register is also clocked, even

though the SO pin shows the status of the nonvolatile

write operation (See Figure 14).

For a byte or page write operation to be completed, CS

can only be brought HIGH after bit 0 of the last data byte

Figure 12. EEPROM Byte Write (EEWRITE) Operation Sequence

CS

20 21 22 23 24 25 26 27 28 29 30 31

0

1

2

3

4

5

6

7

8

9

SCK

SI

EEWRITE Instruction

(1 Byte)

Byte Address (2 Byte)

15 14

Data Byte

3

2

1

0

7

6

5

4

3

2

1

0

High Impedance

SO

Characteristics subject to change without notice. 24 of 40

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X3100/X3101 – Preliminary Information

Figure 13. EEPROM Page Write (EEWRITE) Operation Sequence

CS

20 21 22 23 24 25 26 27 28 29 30 31

0

1

2

3

4

5

6

7

8

9

10

SCK

SI

EEWRITE

Instruction

Byte Address

(2 Byte)

Data Byte 1

15 14 13

3

2

1

0

7

6

5

4

3

2

1

0

CS

SCK

SI

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Data Byte 2

Data Byte 3

Data Byte 16

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

6

5

4

3

2

1

0

Figure 14. EEPROM Read Status (EEREAD STAT) Operation Sequence

CS

0

1

2

3

4

5

6

7

...

SCK

SI

EEREAD STAT

Instruction

Nonvolatile EEWRITE in Progress

I

D

L

2

D

L

1

D

L

0

SO

SO High During

Nonvolatile

EEWRITE Cycle

SO=Status Reg Bit

When No Nonvolatile

EEWRITE Cycle

Characteristics subject to change without notice. 25 of 40

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EEPROM Read Sequence (EEREAD)

address can be read sequentially by continuing to provide

clock pulses.The address is automatically incremented to

the next higher address after each byte of data is shifted

out. When the highest address is reached (01FFh), the

address counter rolls over to address 0000h, allowing

the read cycle to be continued indeﬁnitely. The read

operation is terminated by taking CS HIGH. Refer to the

EEPROM Read (EEREAD) operation sequence

illustrated in Figure 15.

When reading from the X3100 or X3101 EEPROM

memory, CS is ﬁrst pulled LOW to select the device. The 8-

bit EEREAD instruction is transmitted to the X3100 or

X3101, followed by the 16-bit address, of which the last

9 bits are used (bits [15:9] speciﬁed to be zeroes). After

the EEREAD opcode and address are sent, the data

stored in the memory at the selected address is shifted

out on the SO line.The data stored in memory at the next

Figure 15. EEPROM (EEREAD) Read Operation Sequence

CS

20 21 22 23 24 25 26 27 28 29 30 31

0

1

2

3

4

5

6

7

8

9

SCK

SI

EEREAD Instruction

(1 Byte)

Byte Address (2 Byte)

Data Out

3

2

1

0

15 14

High Impedance

7

6

5

4

3

2

1

0

SO

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X3100/X3101 – Preliminary Information

Write Configuration Register (WCFIG)

Write Control Register (WCNTRL)

The Write Conﬁguration Register (WCFIG) instruction

updates the static part of the Conﬁguration Register.

These new values take effect immediately, for example

writing a new Over-discharge voltage limit. However, to

make these changes permanent, so they remain if the

cell voltages are removed, an EEWRITE operation to

the EEPROM array is required following the WCFIG

command.This command is shown in Figure 16.

The Write Control Register (WCNTRL) instruction

updates the contents of the volatile Control Register.

This command sets the status of the FET control pins,

the cell balancing outputs, the current sense gain and

external entry to the sleep mode. Since this instruction

controls a volatile register, no other commands are

required and there is no delay time needed after the

instruction, before subsequent commands. The

operation of the WCNTRL command is shown in

Figure 17.

Figure 16. Write Configuration Register (WCFIG) Operation Sequence

CS

20 21 22 23

0

1

2

3

4

5

6

7

8

9

SCK

SI

Configuration

Register Data

WCFIG Instruction

(1 BYTE)

3

2

1

0

15 14

(2 BYTE)

High Impedance

SO

Figure 17. Write Control Register (WCNTR) Operation Sequence

CS

18 19 20 21 22 23

0

1

2

3

4

5

6

7

8

9

SCK

SI

Control

Register Data

WCNTR Instruction

(1 Byte)

1

0

5

4

3

2

15 14

(2 Byte)

High Impedance

SO

Control

Bits

Old Control Bits

New Control Bits

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X3100/X3101 – Preliminary Information

Read Status Register (RDSTAT)

Set ID Lock (SET IDL)

The Read Status Register (RDSTAT) command returns

the status of the X3100 or X3101. The Status Register

contains three bits that indicate whether the voltage

regulator is stabilized, and if there are any protection

failure conditions. The operation of the RDSTAT

instruction is shown in Figure 18.

The contents of the EEPROM memory array in the

X3100 or X3101 can be locked in one of eight

conﬁgurations using the SET ID lock command. When a

section of the EEPROM array is locked, the contents

cannot be changed, even when a valid write operation

attempts a write to that area. The SET IDL command

operation is shown in Figure 19.

Figure 18. Read Status Register (RDSTAT) Operation Sequence

CS

9

10 11 12 13 14 15

0

1

2

3

4

5

6

7

8

SCK

SI

RDSTAT

Instruction

(1 Byte)

High Impedance

2

1

0

SO

Status Register Output

Figure 19. EEPROM IDLock (SET IDL) Operation Sequence

CS

10 11 12 13 14 15

9

0

1

2

3

4

5

6

7

8

SCK

IDLock

Byte

Set IDL

Instruction

I

D

L

2

D

L

1

D

L

0

SI

High Impedance

SO

Characteristics subject to change without notice. 28 of 40

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X3100/X3101 – Preliminary Information

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min.

-55

Max.

125

85

Unit

°C

mA

°C

V

Storage temperature

Operating temperature

DC output current

-40

5

Lead temperature (soldering 10 seconds)

Power supply voltage

300

VCC

V

-0.5

V

+27.0

SS

VCELL

Cell voltage

-0.5

6.75

V + 0.5

RGO

V

Terminal voltage (Pins: SCK, SI, SO, CS, AS0, AS1, AS2, VCS1,

VCS2, OVT, UVT, OCT, AO)

V

-0.5

V

TERM1

SS

V

Terminal voltage (VCELL1)

V

-0.5

V

+ 1.0

+ 0.5

V

TERM2

SS

CC

Terminal voltage (all other pins)

TERM3

SS

CC

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is

a stress rating only; the functional operation of the device (at these or any other conditions above those indicated in

the operational sections of this speciﬁcation) is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Supply Voltage

Limits

Commercial

-20°C

+70°C

X3100/X3101

6V to 24V

D.C. OPERATING CHARACTERISTICS

(Over the recommended operating conditions, unless otherwise speciﬁed.)

Limits

Symbol

Parameter

Min.

Max.

10

Units

µA

Test Conditions

Input leakage current (SCK, SI, CS,

ASO, AS1, AS2)

I

LI

I

Output leakage current (SO)

10

µA

LO

Input LOW voltage

(SCK, SI, CS, AS0, AS1, AS2)

(1)

V

- 0.3

V

x 0.3

V

IL

RGO

Input HIGH voltage

(SCK, SI, CS, AS0, AS1, AS2)

(1)

V

x 0.7 V

- 0.8

+ 0.3

V

IH

RGO

VOL1

VOH1

Output LOW voltage (SO)

Output HIGH voltage (SO)

0.4

V

I

= 1.0mA

= -0.4mA

OL

V

RGO

OH

Output LOW voltage

(UVP/OCP, OVP/LMON, CB1-CB4)

VOL2

VOH2

VOL3

VOH3

0.4

V

I

= 100uA

= -20uA

OL

Output HIGH voltage

(UVP/OCP, OVP/LMON, CB1-CB4)

V

-0.4

I

CC

OH

= 2mA, RGP = V

,

OL

CC

Output LOW voltage (RGC)

Output HIGH voltage (RGC)

RGO = 5V

I

= -20µA, RGP = V - 4V,

OH

CC

V

-4.0

CC

RGO = 5V

Note: (1) V min. and V max. are for reference only and are not 100ꢀ tested.

IL

IH

Characteristics subject to change without notice. 29 of 40

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X3100/X3101 – Preliminary Information

OPERATING CHARACTERISTICS X3100 (Over the recommended operating conditions unless otherwise specified)

Description

Sym

Condition

On power up or at wake-up

After self-tuning

Min

Typ⁽²⁾

Max

Unit

4.5

5.5

V

4.98

4.95

4.90

4.99

5.00

5.02

5.00

(@10mA V

current; 25^oC)

current; 0 - 50^oC)⁽⁵⁾

current)⁽⁵⁾

RGO

5V regulated voltage

V

RGO After self-tuning

(@10mA V

RGO

After self-tuning

V

(@50mA V

RGO

5VDC voltage regulator current

limit

(3)

I

R

=10Ω

250

mA

LMT

V

supply current (1)

supply current (2)

Icc1 Normal operation

85

250

2.5

µA

CC

Icc2 during nonvolatile EEPROM write

1.3

mA

CC

During EEPROM read

SCK=3.3MHz

V

supply current (3)

supply current (4)

supply current (5)

Icc3

0.9

1.2

1

mA

µA

CC

Icc4 Sleep mode

Monitor mode

Icc5

365

600

AN2, AN1, AN0 not equal to 0.

V

= 4.20V (VOV1, VOV0 = 0,0)

4.10

4.15

4.275

4.25

OV

V

0^oC to 50^oC

V

= 4.25V (VOV1, VOV0 = 0,1)

0^oC to 50^oC

4.15

4.20

4.325

4.30

OV

Cell over-charge protection mode

voltage threshold

(Default in Boldface)

(4)

V

OV

V

= 4.30V (VOV1, VOV0 = 1,0)

0^oC to 50^oC

4.2

4.25

4.375

4.35

OV

4.25

4.30

4.425

4.40

= 4.35V (VOV1, VOV0 = 1,1)

0^oC to 50^oC

Cell over-charge protection mode

release voltage threshold

(Default in Boldface)

V

0.25

-

V

0.20

-

V

0.15

-

OV

V

OVR

(5)

Cell over-charge detection time

T

C

=0.1uF

0.5

1

1.5

s

OV

UV

V

= 1.95V (VUV1, VUV0 = 0,0)

= 2.05V (VUV1, VUV0 = 0,1)

= 2.15V (VUV1, VUV0 = 1,0)

= 2.25V (VUV1, VUV0 = 1,1)

1.85

1.95

2.05

2.15

2.05

2.15

2.25

2.35

V

Cell over-discharge protection

mode (SLEEP) threshold.

(Default in Boldface)

(4)

V

UV

Cell over-discharge protection

mode release threshold

(Default in Boldface)

V

0.65

+

V

0.7

+

V

0.75

+

UV

V

UVR

C

=0.1µF⁽⁵⁾

=200pF

0.5

1

2

1.5

3

s

ms

UV

Cell over-discharge detection time

T

UV

C

=0.1µF⁽⁵⁾

=200pF

3.5

80

7

100

10.5

120

ms

µs

UV

Cell over-discharge release time

T

UVR

Characteristics subject to change without notice. 30 of 40

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X3100/X3101 – Preliminary Information

Description

Sym

Condition

Min

Typ⁽²⁾

Max

Unit

V

= 0.075V (VOC1, VOC0 = 0,0)

0.050

0.060

0.100

0.090

OC

0^oC to 50^oC

V

= 0.100V (VOC1, VOC0 = 0,1)

0^oC to 50^oC

0.075

0.085

0.125

0.115

Over-current mode detection

voltage

(Default in Boldface)

(4)

V

OC

= 0.125V (VOC1, VOC0 = 1,0)

0^oC to 50^oC

0.100

0.110

0.150

0.140

= 0.150V (VOC1, VOC0 = 1,1)

0^oC to 50^oC

0.125

0.135

0.175

0.165

C

=0.001µF⁽⁵⁾

=200pF

=0.001µF⁽⁵⁾

=200pF

5

1

10

2

15

3

OC

Over-current mode detection time

Over-current mode release time

T

ms

OC

C

5

1

10

2

15

3

OC

T

OCR

Load resistance over-current mode

release condition

Releases when OVP/LMON pin >

2.5V

200

250

kΩ

Cell charge threshold voltage

V

=1.4V (Default)⁽⁵⁾

1.30

1.40

1.50

15.5

V

CE

X3100 wake-up voltage

(For Vcc above this voltage, the device

wakes up)

V

See Wake-up test circuit

See Sleep test circuit

12.5

11.5

V

SLR

X3100 sleep voltage

(For Vcc above this voltage, the device

cannot go to sleep)

V

14.5

SLP

Notes: (2) Typical at 25°C.

(3) See Figure 10 on page 21.

(4) The default setting is set at the time of shipping, but may be changed by the user via changes in the conﬁguration register.

(5) For reference only, this parameter is not 100ꢀ tested.

Wake-up test circuit (X3100)

Vcc

Sleep test circuit (X3100)

Vcc

Vcc RGP

VCELL1

VCELL2

VCELL3

VCELL4

VCELL1

RGC

RGO

RGC

RGO

1V

VCELL2

V

RGO

1V

VCELL3

VCELL4

1V

Vss

Increase Vcc until V

turns on

Decrease Vcc until V

turns off

RGO

Characteristics subject to change without notice. 31 of 40

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X3100/X3101 – Preliminary Information

OPERATING CHARACTERISTICS X3101 (Over the recommended operating conditions unless otherwise specified)

Description

Sym

Condition

On power up or at wake-up

After self-tuning

Min

Typ⁽²⁾

Max

Unit

4.5

5.5

V

4.98

4.95

4.90

4.99

5.00

5.02

5.00

(@10mA V

current; 25^oC)

current; 0 - 50^oC)⁽⁵⁾

current)⁽⁵⁾

RGO

5V regulated voltage

V

RGO After self-tuning

(@10mA V

RGO

After self-tuning

V

(@50mA V

RGO

(3)

5VDC voltage regulator current limit I

R

=10Ω

250

85

mA

µA

LMT

V

supply current (1)

supply current (2)

Icc1 Normal operation

250

2.5

CC

Icc2 during nonvolatile EEPROM write

1.3

mA

CC

During EEPROM read

SCK=3.3MHz

V

supply current (3)

supply current (4)

supply current (5)

Icc3

0.9

1.2

1

mA

µA

CC

Icc4 Sleep mode

Monitor mode

Icc5

365

600

AN2, AN1, AN0 not equal to 0.

V

= 4.20V (VOV1, VOV0 = 0,0)

4.10

4.15

4.275

4.25

OV

V

0^oC to 50^oC

V

= 4.25V (VOV1, VOV0 = 0,1)

0^oC to 50^oC

4.15

4.20

4.325

4.30

OV

Cell over-charge protection mode

voltage threshold

(Default in Boldface)

(4)

V

OV

V

= 4.30V (VOV1, VOV0 = 1,0)

0^oC to 50^oC

4.2

4.25

4.375

4.35

OV

4.25

4.30

4.425

4.40

V

= 4.35V (VOV1, VOV0 = 1,1)

0^oC to 50^oC

Cell over-charge protection mode

release voltage threshold

(Default in Boldface)

V

0.25

-

V

0.20

-

V

0.15

-

OV

V

OVR

(5)

Cell over-charge detection time

T

C

=0.1uF

0.5

1

1.5

s

OV

UV

V

= 2.25V (VUV1, VUV0 = 0,0)

= 2.35V (VUV1, VUV0 = 0,1)

= 2.45V (VUV1, VUV0 = 1,0)

= 2.55V (VUV1, VUV0 = 1,1)

2.15

2.25

2.35

2.45

2.35

2.45

2.55

2.65

V

Cell over-discharge protection

mode (SLEEP) threshold.

(Default in Boldface)

(4)

V

UV

Cell over-discharge protection

mode release threshold

(Default in Boldface)

V

0.65

+

V

0.7

+

V

0.75

+

UV

V

UVR

C

=0.1µF⁽⁵⁾

=200pF

0.5

1

2

1.5

3

s

ms

UV

Cell over-discharge detection time

T

UV

C

=0.1µF⁽⁵⁾

=200pF

3.5

80

7

100

10.5

120

ms

µs

UV

Cell over-discharge release time

T

UVR

Characteristics subject to change without notice. 32 of 40

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X3100/X3101 – Preliminary Information

Description

Sym

Condition

Min

Typ⁽²⁾

Max

Unit

V

= 0.075V (VOC1, VOC0 = 0,0)

0.050

0.060

0.100

0.090

OC

0^oC to 50^oC

V

= 0.100V (VOC1, VOC0 = 0,1)

0^oC to 50^oC

0.075

0.085

0.125

0.115

Over-current mode detection

voltage

(Default in Boldface)

(4)

V

OC

= 0.125V (VOC1, VOC0 = 1,0)

0^oC to 50^oC

0.100

0.110

0.150

0.140

= 0.150V (VOC1, VOC0 = 1,1)

0^oC to 50^oC

0.125

0.135

0.175

0.165

C

=0.001µF⁽⁵⁾

=200pF

=0.001µF⁽⁵⁾

=200pF

5

1

10

2

15

3

OC

Over-current mode detection time

Over-current mode release time

T

ms

OC

C

5

1

10

2

15

3

OC

T

OCR

Load resistance over-current mode

release condition

Releases when OVP/LMON pin >

2.5V

200

250

kΩ

Cell charge threshold voltage

V

=1.4V (Default)⁽⁵⁾

1.30

1.50

12.5

V

CE

X3100 wake-up voltage

(For Vcc above this voltage, the device

wakes up)

V

See Wake-up test circuit

See Sleep test circuit

10.5

9.5

V

SLR

X3100 sleep voltage

(For Vcc above this voltage, the device

cannot go to sleep)

V

11.5

SLP

Notes: (2) Typical at 25°C.

(3) See Figure 10 on page 21.

(4) The default setting is set at the time of shipping, but may be changed by the user via changes in the conﬁguration register.

(5) For reference only, this parameter is not 100ꢀ tested.

Wake-up test circuit (X3101)

Vcc

Sleep test circuit (X3101)

Vcc

Vcc RGP

VCELL1

VCELL2

VCELL3

VCELL4

VCELL1

VCELL2

VCELL3

VCELL4

RGC

RGO

RGC

RGO

1V

V

RGO

Vss

Decrease Vcc until V

turns off

RGO

Increase Vcc until V

turns on

RGO

Characteristics subject to change without notice. 33 of 40

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X3100/X3101 – Preliminary Information

POWER-UP TIMING

Symbol

Parameter

Min.

Max.

(6)

t

Power-up to SPI read operation (RDSTAT, EEREAD STAT)

Power-up to SPI write operation (WREN, WRDI, EEWRITE, WCFIG, SET IDL, WCNTR)

T

+2ms

PUR

OC

(6)

t

+2ms

PUW1

T

+200ms

or

OV

(6)

Power-up to SPI write operation (WCNTR - bits 10 and 11)

PUW2

T

+200ms⁽⁷⁾

UV

Notes: (6) t

, t

and t

are the delays required from the time V

PUW2 CC

is stable until a read or write can be initiated. These parameters

PUR PUW1

are not 100ꢀ tested.

(7) Whichever is longer.

CAPACITANCE T =+25°C, f= 1 MHz, V

=5V

A

RGO

Symbol

Parameter

Output capacitance (SO)

Input capacitance (SCK, SI, CS)

Max.

Units

pF

Conditions

=0V

(8)

C

8

6

V

OUT

(8)

C

pF

V =0V

IN

Notes: (8) This parameter is not 100ꢀ tested.

Equivalent A.C. Load Circuit

5V

A.C. TEST CONDITIONS

Input pulse levels

0.5 – 4.5V

10ns

Input rise and fall times

Input and output timing level

2061Ω

2.5V

SO

30pF

3025Ω

Characteristics subject to change without notice. 34 of 40

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X3100/X3101 – Preliminary Information

A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)

SERIAL INPUT TIMING

Symbol

Parameter

Clock frequency

Voltage

Min.

0

Max.

Units

MHz

ns

f

3.3

SCK

t

Cycle time

300

150

130

20

CYC

t

CS lead time

ns

LEAD

t

CS lag time

ns

LAG

t

Clock HIGH time

Clock LOW time

Data setup time

Data hold time

Data in rise time

Data in fall time

CS deselect time

Write cycle time

ns

WH

t

ns

WL

t

ns

SU

t

20

ns

H

(9)

t

2

µs

RI

(9)

µs

FI

t

100

ns

CS

(10)

t

5

ms

WC

Notes: (9) This parameter is not 100ꢀ tested

(10)t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile

WC

write cycle.

Serial Input Timing

t

CS

SCK

SI

t

LEAD

LAG

t

FI

H

SU

RI

MSB IN

LSB IN

SO

Characteristics subject to change without notice. 35 of 40

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X3100/X3101 – Preliminary Information

Serial Output Timing

Symbol

Parameter

Clock Frequency

Voltage

Min.

Max.

3.3

Units

MHz

ns

f

0

SCK

t

Output Disable Time

Output Valid from Clock LOW

Output Hold Time

150

130

DIS

t

ns

V

t

0

ns

HO

(11)

t

Output Rise Time

50

ns

RO

(11)

t

Output Fall Time

ns

FO

Notes: (11)This parameter is not 100ꢀ tested.

Serial Output Timing

CS

t

CYC

WH

LAG

SCK

t

WL

t

DIS

HO

V

SO

SI

MSB Out

MSB–1 Out

LSB Out

ADDR

LSB In

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

Characteristics subject to change without notice. 36 of 40

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X3100/X3101 – Preliminary Information

Analog Output Response Time

Symbol

Parameter

Min.

Typ.

Max.

1.0

Units

ms

t

AO Output Stabilization Time (Voltage Source Change)

AO Output Stabilization Time (Current Sense Gain Change)

VSC

t

1.0

ms

CSGO

Control Outputs Response Time (UVP/OCP, OVP/MON, CB4,

CB3, CB2, CB1, RGC)

t

-1.0

µs

CO

ANALOG OUTPUT RESPONSE TIME

Change in Voltage Source

AS2:AS0

AO

t

VSC

Change in Current Sense Gain Amplification and Control Bits

C S

SCK

DI

0

OVPC

Bit10

CSG1 CSG0 SLP

Bit9 Bit8 Bit7

x

Control Reg

Bit6

Bit5

AO

Old Gain

Current Sense

Gain Change

New Gain

t

CSGO

UVP/OCP

OVP/LMON

CB4:CB1

RGC

On

Control

Outputs

Off

t

CO

Characteristics subject to change without notice. 37 of 40

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X3100/X3101 – Preliminary Information

TYPICAL OPERATING CHARACTERISTICS

Normal Operating Current

Monitor Mode Current

450

400

350

300

150

125

100

75

50

-20

25

80

-20

25

80

Temperature

X3100 Over Discharge Trip Voltage (Typical)

X3100/X3101 Over Charge Trip Voltage (Typical)

2.30

4.40

4.35

4.30

4.25

4.20

4.15

2.25

2.20

2.15

2.10

2.05

2.00

1.95

-25

25

75

-25

25

75

Temperature (Deg C)

4.2V Setting

4.3V Setting

4.25V Setting

4.35V Setting

1.95V Setting

2.15V Setting

2.05V Setting

2.25V Setting

X3101 Over Discharge Trip Voltage (Typical)

Voltage Regulator Output (Typical)

Vcc = 10.8V to 16V R_lim= 15 Ohm (I_lim= 200mA)

2.60

2.55

2.50

2.45

2.40

2.35

2.30

2.25

5.020

5.000

4.980

4.960

4.940

4.920

4.900

4.880

-25

25

75

Temperature (Deg C)

1

10

50

100

2.25V Setting

2.45V Setting

2.35V Setting

2.55V Setting

Load (mA)

-25 degC

25 degC

75 degC

Voltage Regulator Output (Typical)

Vcc = 10.8V to 16V R_lim= 15 Ohm (I_lim= 200mA)

5.020

5.000

4.980

4.960

4.940

4.920

4.900

4.880

-25

25

75

Temperature

1mA Load

10mA Load

50mA Load

100 mA Load

For typical performance of current and voltage monitoring circuits, please refer to Application Note AN142 and AN143

Characteristics subject to change without notice. 38 of 40

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X3100/X3101 – Preliminary Information

28-Lead Plastic, TSSOP, Package Code V28

.026 (.65) BSC

.169 (4.3)

.177 (4.5)

.252 (6.4) BSC

.377 (9.60)

.385 (9.80)

.047 (1.20)

.0075 (.19)

.0118 (.30)

.002 (.06)

.005 (.15)

.010 (.25)

Gage Plane

(7.72)

(4.16)

0° – 8°

Seating Plane

.020 (.50)

.030 (.75)

(1.78)

(0.42)

Detail A (20X)

(0.65)

All Measurements are Typical

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

Characteristics subject to change without notice. 39 of 40

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X3100/X3101 – Preliminary Information

ORDERING INFORMATION

X3100 P

X3101

T

–

V

VCC Limits

Blank=6V to 24V

Device

Temperature Range

Blank=Commercial= -20°C to +70°C

Package

V28 = 28-Lead TSSOP

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemniﬁcation provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,

statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes

no warranty of merchantability or ﬁtness for any purpose. Xicor, Inc. reserves the right to discontinue production and change speciﬁcations and prices at any time and

without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All

others belong to their respective owners.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;

4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137;

5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and

correction, redundancy and back-up features to prevent such an occurence.

Xicor’s products are not authorized for use in critical components in life support devices or systems.

1.

Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signiﬁcant injury to the user.

2.

A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

Characteristics subject to change without notice. 40 of 40

REV 1.1.8 12/10/02

www.xicor.com


型号：	X3101
厂家：	XICOR INC.
描述：	3 or 4 Cell Li-Ion Battery Protection and Monitor IC 3或4节锂离子电池保护和监控器IC 电池监控
文件：	总40页 (文件大小：248K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X3101 [XICOR]

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