X40235S16I-BT1 [XICOR]
Power Supply Support Circuit, Adjustable, 3 Channel, PDSO16, 0.300 INCH, PLASTIC, SOIC-16;
| 型号： | X40235S16I-BT1 |
| 厂家： | 
XICOR INC. |
| 描述： | Power Supply Support Circuit, Adjustable, 3 Channel, PDSO16, 0.300 INCH, PLASTIC, SOIC-16 光电二极管 |
| 文件： | 总39页 (文件大小：599K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X4023x
Integrated System Management IC
Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP
FEATURES
DESCRIPTION
• Triple Voltage Monitors
The X4023x family of Integrated System Management
ICs combine CPU Supervisor functions (V Power On
—User Programmable Threshold Voltage
—Power On Reset (POR) Circuitry
—Software Selectable Reset timeout
—Manual Reset Input
• 2-Wire industry standard Serial Interface
• 2 kbit EEPROM with Write Protect & Block LockTM
• Digitally Controlled Potentiometers (DCP)
CC
Reset (POR) circuitry, two additional programmable volt-
age monitor inputs with software and hardware indica-
tors), integrated EEPROM with Block LockTM protection
and one or two Xicor Digitally Controlled Potentiometers
(XDCP). All functions of the X4023x are accessed by an
industry standard 2-Wire serial interface.
X4023X Family Selector Guide
X= 256 tap 100 tap 64 Tap
APPLICATIONS
The DCP of the X4023x may be utilized to software con-
trol analog voltages for:
1
3
5
7
9
1
1
1
– LCD contrast, LCD purity, or Backlight control.
– Power Supply settings such as PWM frequency, Voltage
Trimming or Margining (temperature offset control).
– Reference voltage setting (e.g. DDR-SDRAM SSTL-2)
1
1
1
1
The 2 kbit integrated EEPROM may be used to store ID,
manufacturer data, maintenance data and module defini-
tion data.
—Total Resistance
256 Tap = 100 kΩ, 100 Tap or 64 Tap = 10 kΩ
—Nonvolatile wiper position
—Write Protect Function
• Single Supply Operation
—2.7 V to 5.5 V
The programmable POR circuit insures V
is stable
CC
before RESET is removed and protects against brown-
outs and power failures. The programmable voltage mon-
itors have on-chip independent reference alarm levels.
With separate outputs, the voltage monitors can be used
for power on sequencing.
• 16 Pin SOIC (300) package
—SOIC
BLOCK DIAGRAM
8
R
R
H
WIPER
COUNTER
REGISTER
WP
256 Tap DCP
PROTECT LOGIC
W
CR
REGISTER
8 - BIT
NONVOLATILE
MEMORY
DATA
REGISTER
4
SDA
SCL
COMMAND
DECODE &
CONTROL
LOGIC
R
R
H
WIPER
Optional
2 kbit
EEPROM
ARRAY
COUNTER
REGISTER
W
64 or 100 Tap DCP
THRESHOLD
RESET LOGIC
8 - BIT
NONVOLATILE
MEMORY
Manual Reset (MR)
V3MON
2
V3FAIL
V2FAIL
RESET
-
+
VTRIP
3
-
+
V2MON
VTRIP
VTRIP
2
POWER ON /
V
CC
+
–
LOW VOLTAGE
RESET
GENERATION
V
SS
1
©2000 Xicor Inc., Patents Pending (VTRIP
are user programmable)
1,2,3
Characteristics subject to change without notice. 1 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
PIN CONFIGURATION
SINGLE XDCP
X40233
X40231
X40235
16 Pin SOIC
16 Pin SOIC
16 Pin SOIC
V
V
V
CC
NC
NC
CC
NC
16
1
CC
R
R
16
1
16
1
H2
RESET
RESET
RESET
NC
15
14
13
15
14
13
2
3
W2
15
14
13
2
3
2
3
V3MON
V3FAIL
MR
V3MON
V3FAIL
MR
V3MON
V3FAIL
MR
V2FAIL
V2MON
NC
V2FAIL
V2MON
V2FAIL
V2MON
NC
4
5
6
4
5
6
4
5
6
R
12
11
10
9
12
11
10
9
12
11
10
9
W0
WP
SCL
SDA
WP
SCL
SDA
WP
SCL
SDA
R
R
NC
H1
H0
7
8
7
8
7
8
R
NC
NC
W1
VSS
VSS
VSS
DUAL XDCP
X40237
X40239
16 Pin SOIC
16 Pin SOIC
V
V
CC
R
CC
R
16
1
16
1
H2
H2
RESET
RESET
R
R
W2
W2
15
14
13
15
14
13
2
3
2
3
V3MON
V3FAIL
MR
V3MON
V3FAIL
MR
V2FAIL
V2MON
V2FAIL
V2MON
NC
4
5
6
4
5
6
R
12
11
10
9
12
11
10
9
W0
WP
SCL
SDA
WP
SCL
SDA
R
R
R
H0
H1
7
8
7
8
NC
W1
VSS
VSS
Characteristics subject to change without notice. 2 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
X40231 PIN ASSIGNMENT
SOIC
Name
NC
Function
1
2
No Connect
NC
No Connect
V3MON Voltage Monitor Input.
V3MON i s the input to a non-inverting voltage comparator circuit. When the V3MON input is higher
than the V threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V
when not used.
3
4
V3MON
V3FAIL
TRIP3
SS
V3MON RESET Output.
This open drain output makes a transition to a HIGH level when V3MON is greater than V
goes LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin
requires the use of an external “pull-up” resistor.
and
TRIP3
Manual Reset.
MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the
5
6
MR
WP
RESET pin (V RESET Output pin). RESET will remain HIGH for time t
to it’s normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR
Register. The MR pin requires the use of an external “pull-down” resistor.
after MR has returned
CC
PURST
Write Protect Control Pin.
WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled,
and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write”
(volatile or nonvolatile) operations can be performed in the device (including the wiper position of any
of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down”
resistor, thus if left floating the write protection feature is disabled.
Serial Clock.
7
8
SCL
SDA
This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data.
SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The
SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor.
9
VSS
NC
Ground.
10
11
No Connect
R
Connection to end of resistor array for (the 64 Tap) DCP.
H0
R
12
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP.
W0
V2MON Voltage Monitor Input.
V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater
13
V2MON
V2FAIL
than the V
when not used.
threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V
TRIP2
SS
V2MON RESET Output.
This open drain output makes a transition to a HIGH level when V2MON is greater than V
, and
TRIP2
14
goes LOW when V2MON is less than V
. There is no power up reset delay circuitry on this pin.The
TRIP2
V2FAIL pin requires the use of an external “pull-up” resistor.
V
RESET Output.
CC
This is an active HIGH, open drain output which becomes active whenever V falls below V
.
CC
TRIP1
RESET becomes active on power up and remains active for a time t
after the power supply
PURST
15
16
RESET
stabilizes (t
can be changed by varying the PUP0 and PUP1 bits of the internal control register).
PURST
The RESET pin requires the use of an external “pull-up” resistor.The RESET pin can be forced active
(HIGH) using the manual reset (MR) input pin.
V
Supply Voltage.
CC
Characteristics subject to change without notice. 3 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
X40233 PIN ASSIGNMENT
SOIC
Name
NC
Function
1
2
No Connect
NC
No Connect
V3MON Voltage Monitor Input.
V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher
than the V threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V
when not used.
3
4
V3MON
V3FAIL
TRIP3
SS
V3MON RESET Output.
This open drain output makes a transition to a HIGH level when V3MON is greater than V
goes LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin
requires the use of an external “pull-up” resistor.
and
TRIP3
Manual Reset.
MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the
5
6
MR
RESET pin (V RESET Output pin). RESET will remain HIGH for time t
to it’s normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR
Register. The MR pin requires the use of an external “pull-down” resistor.
after MR has returned
CC
PURST
Write Protect Control Pin.
WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled,
and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write”
(volatile or nonvolatile) operations can be performed in the device (including the wiper position of any
of the integrated Digitally Controlled Potentiometers (DCPs).The WP pin uses an internal “pull-down”
resistor, thus if left floating the write protection feature is disabled.
WP
Serial Clock.
7
8
SCL
This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data.
SDA
VSS
SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The
SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor.
9
Ground.
R
10
11
12
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP.
Connection to end of resistor array for (the 100 Tap) DCP.
No Connect
W1
R
H1
NC
V2MON Voltage Monitor Input.
V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater
13
14
V2MON
than the V
when not used.
threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V
TRIP2
SS
V2MON RESET Output.
This open drain output makes a transition to a HIGH level when V2MON is greater than V
, and
TRIP2
V2FAIL
RESET
goes LOW when V2MON is less than V
. There is no power up reset delay circuitry on this pin.
TRIP2
The V2FAIL pin requires the use of an external “pull-up” resistor.
V
RESET Output.
CC
This is an active HIGH, open drain output which becomes active whenever V falls below V
.
CC
TRIP1
RESET becomes active on power up and remains active for a time t
after the power supply
PURST
15
16
stabilizes (t
can be changed by varying the PUP0 and PUP1 bits of the internal control register).
PURST
The RESET pin requires the use of an external “pull-up” resistor.The RESET pin can be forced active
(HIGH) using the manual reset (MR) input pin.
V
Supply Voltage.
CC
Characteristics subject to change without notice. 4 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
X40235 PIN ASSIGNMENT
SOIC
Name
Function
R
1
2
Connection to end of resistor array for (the 256 Tap) DCP.
H2
R
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP.
W2
V3MON Voltage Monitor Input.
V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher
3
4
V3MON
V3FAIL
than the V
when not used.
threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V
TRIP3
SS
V3MON RESET Output.
This open drain output makes a transition to a HIGH level when V3MON is greater than V
goes LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin
requires the use of an external “pull-up” resistor.
and
TRIP3
Manual Reset.
MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the
5
6
MR
WP
RESET pin (V RESET Output pin). RESET will remain HIGH for time t
to it’s normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR
Register. The MR pin requires the use of an external “pull-down” resistor.
after MR has returned
CC
PURST
Write Protect Control Pin.
WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled,
and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write”
(volatile or nonvolatile) operations can be performed in the device (including the wiper position of any
of the integrated Digitally Controlled Potentiometers (DCPs).The WP pin uses an internal “pull-down”
resistor, thus if left floating the write protection feature is disabled.
Serial Clock.
7
8
SCL
SDA
This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data.
SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The
SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor.
9
VSS
NC
NC
NC
Ground.
10
11
12
No Connect
No Connect
No Connect
V2MON Voltage Monitor Input.
V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater
13
14
V2MON
V2FAIL
than the V
when not used.
threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V
TRIP2
SS
V2MON RESET Output.
This open drain output makes a transition to a HIGH level when V2MON is greater than V
, and
TRIP2
goes LOW when V2MON is less than V
. There is no power up reset delay circuitry on this pin.
TRIP2
The V2FAIL pin requires the use of an external “pull-up” resistor.
V
RESET Output.
CC
This is an active HIGH, open drain output which becomes active whenever V falls below V
.
CC
TRIP1
RESET becomes active on power up and remains active for a time t
after the power supply
PURST
15
16
RESET
stabilizes (t
can be changed by varying the PUP0 and PUP1 bits of the internal control register).
PURST
The RESET pin requires the use of an external “pull-up” resistor.The RESET pin can be forced active
(HIGH) using the manual reset (MR) input pin.
V
Supply Voltage.
CC
Characteristics subject to change without notice. 5 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
X40237 PIN ASSIGNMENT
SOIC
Name
Function
R
1
2
Connection to end of resistor array for (the 256 Tap) DCP2.
H2
R
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP2.
W2
V3MON Voltage Monitor Input.
V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher
3
4
V3MON
V3FAIL
than the V
when not used.
threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V
TRIP3
SS
V3MON RESET Output.
This open drain output makes a transition to a HIGH level when V3MON is greater than V
goes LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin
requires the use of an external “pull-up” resistor.
and
TRIP3
Manual Reset. MR is a TTL level compatible input.
Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET pin (V RESET Output pin).
CC
5
6
MR
WP
RESET will remain HIGH for time t
time can be selected using bits PUP1 and PUP0 in the CR Register. The MR pin requires the use of
an external “pull-down” resistor.
after MR has returned to it’s normally LOW state. The reset
PURST
Write Protect Control Pin.
WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled,
and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write”
(volatile or nonvolatile) operations can be performed in the device (including the wiper position of any
of the integrated Digitally Controlled Potentiometers (DCPs).The WP pin uses an internal “pull-down”
resistor, thus if left floating the write protection feature is disabled.
Serial Clock.
7
8
SCL
SDA
This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data.
SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The
SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor.
9
VSS
NC
Ground.
10
11
No Connect
R
Connection to end of resistor array for (the 64 Tap) DCP0.
H0
R
12
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP0.
W0
V2MON Voltage Monitor Input.
V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater
13
V2MON
V2FAIL
than the V
when not used.
threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V
TRIP2
SS
V2MON RESET Output.
This open drain output makes a transition to a HIGH level when V2MON is greater than V
, and
TRIP2
14
goes LOW when V2MON is less than V
. There is no power up reset delay circuitry on this pin.
TRIP2
The V2FAIL pin requires the use of an external “pull-up” resistor.
V
RESET Output.
CC
This is an active HIGH, open drain output which becomes active whenever V falls below V
.
CC
TRIP1
RESET becomes active on power up and remains active for a time t
after the power supply
PURST
15
16
RESET
stabilizes (t
can be changed by varying the PUP0 and PUP1 bits of the internal control register).
PURST
The RESET pin requires the use of an external “pull-up” resistor.The RESET pin can be forced active
(HIGH) using the manual reset (MR) input pin.
V
Supply Voltage.
CC
Characteristics subject to change without notice. 6 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
X40239 PIN ASSIGNMENT
SOIC
Name
Function
R
1
2
Connection to end of resistor array for (the 256 Tap) DCP2.
H2
R
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP2.
W2
V3MON Voltage Monitor Input.
V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher
3
4
V3MON
V3FAIL
than the V
when not used.
threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V
TRIP3
SS
V3MON RESET Output.
This open drain output makes a transition to a HIGH level when V3MON is greater than V
and
TRIP3
goes LOW when V3MON is less than V
. There is no delay circuitry on this pin. The V3FAIL pin
TRIP3
requires the use of an external “pull-up” resistor.
Manual Reset. MR is a TTL level compatible input.
Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET pin (V RESET Output pin).
CC
5
6
MR
RESET will remain HIGH for time t
time can be selected using bits PUP1 and PUP0 in the CR Register. The MR pin requires the use of
an external “pull-down” resistor.
after MR has returned to it’s normally LOW state.The reset
PURST
Write Protect Control Pin.
WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled,
and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write”
(volatile or nonvolatile) operations can be performed in the device (including the wiper position of any
of the integrated Digitally Controlled Potentiometers (DCPs).The WP pin uses an internal “pull-down”
resistor, thus if left floating the write protection feature is disabled.
WP
Serial Clock.
7
8
SCL
This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data.
SDA
VSS
SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The
SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor.
9
Ground.
R
10
11
12
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP1
Connection to end of resistor array for (the 100 Tap) DCP1.
No Connect
W1
R
H1
NC
V2MON Voltage Monitor Input.
V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater
13
14
V2MON
than the V
when not used.
threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V
TRIP2
SS
V2MON RESET Output.
This open drain output makes a transition to a HIGH level when V2MON is greater than V
, and
TRIP2
V2FAIL
RESET
goes LOW when V2MON is less than V
. There is no power up reset delay circuitry on this pin.
TRIP2
The V2FAIL pin requires the use of an external “pull-up” resistor.
V
RESET Output.
CC
This is an active HIGH, open drain output which becomes active whenever V falls below V
.
CC
TRIP1
RESET becomes active on power up and remains active for a time t
after the power supply
PURST
15
16
stabilizes (t
can be changed by varying the PUP0 and PUP1 bits of the internal control register).
PURST
The RESET pin requires the use of an external “pull-up” resistor.The RESET pin can be forced active
(HIGH) using the manual reset (MR) input pin.
V
Supply Voltage.
CC
Characteristics subject to change without notice. 7 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 1. Valid Data Changes on the SDA Bus
DETAILED DEVICE DESCRIPTION
Xicor’s unique circuits allow for all internal trip voltages
to be individually programmed with high accuracy,
either by Xicor at final test or by the user during their
The X4023x combines One or Two Xicor Digitally Con-
trolled Potentiometer (XDCP) devices, V
power on
CC
production process. Some distributors offer V
TRIP
reset control, V
low voltage reset control, two sup-
CC
reprogramming as a value added service. This gives
the designer great flexibility in changing system param-
eters, either at the time of manufacture, or in the field.
plementary voltage monitors with independent outputs,
and integrated EEPROM with Block Lock™ protection,
in one package. The integrated functionality of the
X4023x lowers system cost, increases reliability, and
reduces board space requirements.
The memory portion of the device is a CMOS serial
EEPROM array with Xicor’s Block LockTM protection.
This memory may be used to store module manufac-
turing data, serial numbers, or various other system
parameters. The EEPROM array is internally organized
as x 8, and utilizes Xicor’s proprietary Direct WriteTM
cells providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
DCPs allow for the “set-and-forget” adjustment during
production test or in-system updating via the industry
standard 2-wire interface.
Applying voltage to V
activates the Power On Reset
CC
circuit which sets the RESET output HIGH, until the
supply voltage stabilizes for a period of time (50-300
msec selectable via software). The RESET output then
goes LOW. The Low Voltage Reset circuit sets the
The device features a 2-Wire interface.
PRINCIPLES OF OPERATION
SERIAL INTERFACE
RESET output HIGH when V
falls below the mini-
CC
mum V
trip point. RESET remains HIGH until V
CC
CC
returns to proper operating level and stabilizes for a
period of time (t . A Manual Reset (MR) input
PURST)
Serial Interface Conventions
allows the user to externally activate the RESET out-
put.
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data trans-
fers, and provides the clock for both transmit and
receive operations. The X4023x operates as a slave in
all applications.
Two supplementary Voltage Monitor circuits, V2MON
and V3MON, continuously compare their inputs to indi-
vidual trip voltages (independent on-chip voltage refer-
ences factory set and user programmable). When an
input voltage exceeds it’s associated trip level, the cor-
responding output (V3FAIL, V2FAIL) goes HIGH. When
the input voltage becomes lower than it’s associated
trip level, the corresponding output is driven LOW. A
corresponding binary representation of the two monitor
circuit outputs (V2FAIL and V3FAIL) are also stored in
latched, volatile (CR) register bits. The status of these
two monitor outputs can be read out via the 2-wire
serial port. The bits will remain SET, even after the
alarm condition is removed, allowing advanced recov-
ery algorithms to be implemented.
Serial Clock and Data
Data states on the SDA line can change only while
SCL is LOW (see Figure 1). SDA state changes while
SCL is HIGH are reserved for indicating START and
STOP conditions. See Figure 1. On power up of the
X4023x, the SDA pin is in the input mode.
Characteristics subject to change without notice. 8 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
SCL
SDA
Start
Stop
Figure 2. Valid Start and Stop Conditions
cycle, the receiver will pull the SDA line LOW to
ACKNOWLEDGE that it received the eight bits of data.
Refer to Figure 3
Serial Start Condition
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not
respond to any command until this condition has been
met. See Figure 2.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte.
If a write operation is selected, the device will respond
with an ACKNOWLEDGE after the receipt of each sub-
sequent eight bit word.
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. The STOP condition is also used to
place the device into the Standby power mode after a
read sequence. A STOP condition can only be issued
after the transmitting device has released the bus. See
Figure 2.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data.The device will ter-
minate further data transmissions if an ACKNOWL-
EDGE is not detected. The master must then issue a
STOP condition to place the device into a known state.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The trans-
mitting device, either master or slave, will release the
bus after transmitting eight bits. During the ninth clock
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the
X4023x can be split up into three main parts:
SCL from
Master
1
8
9
Data Output from
Transmitter
Data Output
from Receiver
Start
Acknowledge
Figure 3. Acknowledge Response From Receiver
Characteristics subject to change without notice. 9 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
—One or Two Digitally Controlled Potentiometers (DCPs)
—EEPROM array
SA7 SA6
SA3 SA2
SA5 SA4
SA1
SA0
R/W
1 0 1 0
—Control and Status (CR) Register
Depending upon the operation to be performed on
each of these individual parts, a 1, 2 or 3 Byte protocol
is used. All operations however must begin with the
Slave Address Byte being issued on the SDA pin. The
Slave address selects the part of the X4023x to be
addressed, and specifies if a Read or Write operation is
to be performed.
READ /
WRITE
INTERNAL
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESS
Internally Addressed
Device
Internal Address
(SA3 - SA1)
000
010
111
EEPROM Array
CR Register
DCP
It should be noted that in order to perform a write oper-
ation to either a DCP or the EEPROM array, the Write
Enable Latch (WEL) bit must first be set (See “BL1,
BL0: Block Lock protection bits - (Nonvolatile)” on
page 18.)
Bit SA0
Operation
WRITE
0
1
Slave Address Byte
READ
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4). This byte con-
sists of three parts:
Figure 4. Slave Address Format
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X4023x.
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte.
The Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is
still busy with the high voltage cycle then no
ACKNOWLEDGE will be returned. If the device has
completed the write operation, an ACKNOWLEDGE
will be returned and the host can then proceed with a
read or write operation. (Refer to Figure 5)
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 000 internally selects
the EEPROM array, while setting these bits to 111
selects the DCP structures in the X4023x.The CR Reg-
ister may be selected using the Internal Device Address
010.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4)
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
The X4023x includes one or two independent resistor
arrays. For the 64, 100 or 256 tap XDCPs, these arrays
respectively contain 63, 99 discrete resistive segments
that are connected in series. (the 256 tap resistor
achieves an equivalent end to end resistance.) The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer. At one end of
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the EEPROM array, the Non Volatile Memory of a DCP
(NVM), or the CR Register) has been correctly issued
(including the final STOP condition), the X4023x ini-
tiates an internal high voltage write cycle. This cycle
typically requires 5 ms. During this time, no further
Read or Write commands can be issued to the device.
Write Acknowledge Polling is used to determine when
this high voltage write cycle has been completed.
the resistor array the terminal connects to the R pin
Hx
(x = 0,1,2).The other end of the resistor array is con-
nected to V inside the package.
SS
Characteristics subject to change without notice. 10 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
At both ends of each array and between each resistor
segment there is a CMOS switch connected between
Byte load completed
by issuing STOP.
Enter ACK Polling
the resistor array and the wiper (R ) output. Within
x
w
each individual array, only one switch may be turned on
at any one time. These switches are controlled by the
Wiper Counter Register (WCR) (See Figure 6). The
WCR is a volatile register.
Issue START
On power up of the X4023x, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below
shows the Initial Values of the DCP WCR’s before the
contents of the NVM is loaded into the WCR.
Issue Slave Address
Byte (Read or Write)
Issue STOP
NO
ACK
returned?
DCP
R (64 TAP)
Initial Values Before Recall
V (TAP = 63)
0
H
YES
R (100 TAP)
V (TAP = 0)
L
1
High Voltage Cycle
complete. Continue
command sequence?
NO
R (256 TAP)
V (TAP = 255)
H
2
Issue STOP
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
before break” sequence is used internally for the FET
switches when the wiper is moved from one tap posi-
tion to another.
YES
Continue normal
Read or Write
command sequence
Hot Pluggability
Figure 7 shows a typical waveform that the X4023x
might experience in a Hot Pluggable situation. On
PROCEED
power up, V applied to the X4023x may exhibit some
amount of ringing, before it settles to the required
value.
CC
Figure 5.
Acknowledge Polling Sequence
The device is designed such that the wiper terminal
(R ) is recalled to the correct position (as per the last
stored in the DCP NVM), when the voltage applied to
Wx
R
N
Hx
V
exceeds V
for a time exceeding t
(the
CC
PURST
TRIP1
Power On Reset time, set in the CR Register - See
“CONTROL AND STATUS REGISTER” on page 18.).
WIPER
COUNTER
REGISTER
(WCR)
Therefore, if t
is defined as the time taken for V
CC
trans
to settle above V
(Figure 7): then the desired
TRIP1
wiper terminal position is recalled by (a maximum)
is
“WIPER”
FET
SWITCHES
RESISTOR
ARRAY
DECODER
time: t
+ t
. It should be noted that t
PURST trans
trans
determined by system hot plug conditions.
2
NON
VOLATILE
MEMORY
1
0
DCP Operations
In total there are three operations that can be per-
formed on any internal DCP structure:
(NVM)
R
Wx
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
Figure 6. DCP Internal Structure
Characteristics subject to change without notice. 11 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
V
CC
V
V
CC (Max.)
TRIP1
t
TRANS
t
PURST
t
0
Maximum Wiper Recall time
Figure 7. DCP Power up
A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
I7
I6
0
I5
0
I4
0
I3
0
I2
0
I1
P1
I0
P0
WT
position” setting is recalled into the WCR after V
of
CC
the X4023x is powered down and then powered back
up.
WRITE TYPE
DCP SELECT
A volatile write operation to a DCP however, changes
the “wiper position” by writing new data to the associ-
ated WCR only. The contents of the associated NVM
WT†
Description
Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
0
register remains unchanged. Therefore, when V
to
CC
the device is powered down then back up, the “wiper
position” reverts to that last position written to the DCP
using a nonvolatile write operation.
Select a Nonvolatile Write operation to be per-
formed on the DCP pointed to by bits P1 and P0
1
†
This bit has no effect when a Read operation is being performed.
Both volatile and nonvolatile write operations are exe-
cuted using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a
Data Byte (See Figure 9)
Figure 8. Instruction Byte Format
case, the two Least Significant Bit’s (I1 - I0) of the
Instruction Byte are used to select the particular DCP
(0 - 2). In the case of a Write to any of the DCPs (i.e.
the LSB of the Slave Address is 0), the Most Significant
Bit of the Instruction Byte (I7), determines the Write
Type (WT) performed.
A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consist-
ing of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again
(Refer to Figure 10).
If WT is “1”, then a Nonvolatile Write to the DCP occurs.
In this case, the “wiper position” of the DCP is changed
by simultaneously writing new data to the associated
WCR and NVM. Therefore, the new “wiper position”
Instruction Byte
While the Slave Address Byte is used to select the
DCP devices, an Instruction Byte is used to determine
which DCP is being addressed.
setting is recalled into the WCR after V
of the
CC
X4023x has been powered down then powered back
up
The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device Address
bits of the Slave Address are set to 1010111. In this
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of
Characteristics subject to change without notice. 12 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
the associated NVM register remains unchanged.
P1- P0
DCPx
x=0
# Taps
64
Max. Data Byte
Therefore, when V
to the device is powered down
CC
0
0
1
1
0
1
0
1
3Fh
Refer to Appendix 1
FFh
then back up, the “wiper position” reverts to that last
written to the DCP using a nonvolatile write operation.
x=1
100
x=2
256
DCP Write Operation
Reserved
A write to DCPx (x=0,1,2) can be performed using the
three byte command sequence shown in Figure 9.
Using a Data Byte larger than the values specified
above results in the “wiper terminal” being set to the
highest tap position. The “wiper position” does NOT
roll-over to the lowest tap position.
In order to perform a write operation on a particular
DCP, the Write Enable Latch (WEL) bit of the CR Reg-
ister must first be set (See “BL1, BL0: Block Lock pro-
tection bits - (Nonvolatile)” on page 18.)
For DCP0 (64 Tap) and DCP2 (256 Tap), the Data Byte
maps one to one to the “wiper position” of the DCP
“wiper terminal”. Therefore, the Data Byte 00001111
The Slave Address Byte 10101110 specifies that a
Write to a DCP is to be conducted. An ACKNOWL-
EDGE is returned by the X4023x after the Slave
Address, if it has been received correctly.
(15 ) corresponds to setting the “wiper terminal” to
10
tap position 15. Similarly, the Data Byte 00011100
(28 ) corresponds to setting the “wiper terminal” to
10
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to
be written, while the WT bit determines if the Write is to
be volatile or nonvolatile. If the Instruction Byte format
is valid, another ACKNOWLEDGE is then returned by
the X4023x.
tap position 28. The mapping of the Data Byte to “wiper
position” data for DCP1 (100 Tap), is shown in
“APPENDIX 1” . An example of a simple C language
function which “translates” between the tap position
(decimal) and the Data Byte (binary) for DCP1, is given
in “APPENDIX 2” .
Following the Instruction Byte, a Data Byte is issued to
the X4023x over SDA. The Data Byte contents is
latched into the WCR of the DCP on the first rising
edge of the clock signal, after the LSB of the Data Byte
(D0) has been issued on SDA (See Figure 34).
It should be noted that all writes to any DCP of the
X4023x are random in nature. Therefore, the Data Byte
of consecutive write operations to any DCP can differ
by an arbitrary number of bits. Also, setting the bits
P1=1, P0=1 is a reserved sequence, and will result in
no ACKNOWLEDGE after sending an Instruction Byte
on SDA.
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON)
of the DCP. The maximum value for the Data Byte
depends upon which DCP is being addressed (see fol-
lowing table).
The factory default setting of all “wiper position” set-
tings is with 00h stored in the NVM of the DCPs. This
corresponds to having the “wiper terminal” R
WX
(x=0,1,2) at the “lowest” tap position, Therefore, the
resistance between R and R is a minimum (essen-
WX
LX
tially only the Wiper Resistance, R ).
W
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
A
C
K
S
T
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
Figure 9. DCP Write Command Sequence
Characteristics subject to change without notice. 13 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
WRITE Operation
READ Operation
Data Byte
S
t
S
t
Signals from
the Master
Instruction
Byte
Slave
Address
S
t
o
p
Slave
Address
a
r
a
r
t
t
SDA Bus
P
0
P
1
W
T
1 0 1 0 1 1 1 0
0 0 0 0 0
1 0 1 0 1 1 1 1
A
C
K
A
C
K
A
C
K
DCPx
x = 0
Signals from
the Slave
- -
-
x = 1
x = 2
“Dummy” write
LSB
MSB
“-” = DON’T CARE
Figure 10. DCP Read Sequence
Following this ACKNOWLEDGE, the master immedi-
ately issues another START condition and a valid Slave
address byte with the R/W bit set to 1. Then the
X4023x issues an ACKNOWLEDGE followed by Data
Byte, and finally, the master issues a STOP condition.
The Data Byte read in this operation, corresponds to
the “wiper position” (value of the WCR) of the DCP
pointed to by bits P1 and P0.
DCP Read Operation
A read of DCPx (x=0,1,2) can be performed using the
three byte random read command sequence shown in
Figure 10.
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a
“dummy” write” is to be conducted. This “dummy” write
operation sets which DCP is to be read (in the preced-
ing Read operation). An ACKNOWLEDGE is returned
by the X4023x after the Slave Address if received cor-
rectly. Next, an Instruction Byte is issued on SDA. Bits
P1-P0 of the Instruction Byte determine which DCP
“wiper position” is to be read. In this case, the state of
the WT bit is “don’t care”. If the Instruction Byte format
is valid, then another ACKNOWLEDGE is returned by
the X4023x.
It should be noted that when reading out the data byte
for DCP0 (64 Tap), the upper two most significant bits
are “unknown” bits. For DCP1 (100 Tap), the upper
most significant bit is an “unknown”. For DCP2 (256
Tap) however, all bits of the data byte are relevant (See
Figure 10).
WRITE Operation
S
t
Signals from
the Master
S
Address
Byte
Slave
Address
Data
Byte
t
a
r
o
p
t
SDA Bus
0 1
0 0
0
1
0 0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Internal
Device
Address
Figure 11. EEPROM Byte Write Sequence
Characteristics subject to change without notice. 14 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
S
t
(2 < n < 16)
Signals from
the Master
S
t
o
p
a
r
Address
Byte
Slave
Address
Data
(1)
Data
(n)
t
SDA Bus
1 0 1 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 12. EEPROM Page Write Operation
2 kbit EEPROM ARRAY
Block Lock protection bits - (Nonvolatile)” on page 18.),
suppresses the ACKNOWLEDGE bit after the Address
Byte.
Operations on the 2 kbit EEPROM Array, consist of
either 1, 2 or 3 byte command sequences. All opera-
tions on the EEPROM must begin with the Device Type
Identifier of the Slave Address set to 1010000. A Read
or Write to the EEPROM is selected by setting the LSB
of the Slave Address to the appropriate value R/W
(Read = “1”, Write=”0”).
EEPROM Page Write
In order to perform an EEPROM Page Write operation
to the EEPROM array, the Write Enable Latch (WEL)
bit of the CR Register must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 18.)
In some cases when performing a Read or Write to the
EEPROM, an Address Byte may also need to be speci-
fied. This Address Byte can contain the values 00h to
FFh.
The X4023x is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit an
unlimited number of 8-bit bytes. After the receipt of
each byte, the X4023x responds with an ACKNOWL-
EDGE, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page.
EEPROM Byte Write
In order to perform an EEPROM Byte Write operation
to the EEPROM array, the Write Enable Latch (WEL)
bit of the CR Register must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 18.)
For a write operation, the X4023x requires the Slave
Address Byte and an Address Byte. This gives the
master access to any one of the words in the array.
After receipt of the Address Byte, the X4023x responds
with an ACKNOWLEDGE, and awaits the next eight
bits of data. After receiving the 8 bits of the Data Byte,
it again responds with an ACKNOWLEDGE. The mas-
ter then terminates the transfer by generating a STOP
condition, at which time the X4023x begins the internal
write cycle to the nonvolatile memory (See Figure 11).
During this internal write cycle, the X4023x inputs are
disabled, so it does not respond to any requests from
the master. The SDA output is at high impedance. A
write to a region of EEPROM memory which has been
protected with the Block-Lock feature (See “BL1, BL0:
For example, if the master writes 12 bytes to the page
starting at location 11 (decimal), the first 5 bytes are
written to locations 11 through 15, while the last 7 bytes
are written to locations 0 through 6. Afterwards, the
address counter would point to location 7. If the master
supplies more than 16 bytes of data, then new data
overwrites the previous data, one byte at a time (See
Figure 13).
The master terminates the Data Byte loading by issu-
ing a STOP condition, which causes the X4023x to
begin the nonvolatile write cycle. As with the byte write
operation, all inputs are disabled until completion of the
internal write cycle. See Figure 12 for the address,
ACKNOWLEDGE, and data transfer sequence.
Characteristics subject to change without notice. 15 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
5 bytes
7 bytes
address
11
address
address
= 6
15
10
10
10
address pointer
ends here
Addr = 7
10
Figure 13. Example:Writing 12 bytes to a 16-byte page starting at location 11.
Signals from
the Master
S
t
S
t
o
p
Slave
Address
a
r
t
SDA Bus
1 0 1 0 0 0 0 1
A
C
K
Signals from
the Slave
Data
Figure 14. Current EEPROM Address Read Sequence
address n, the next read operation would access data
from address n+1. On power up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Stops and EEPROM Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and receiving the subsequent ACKNOWLEDGE signal.
If the master issues a STOP within a Data Byte, or
before the X4023x issues a corresponding ACKNOWL-
EDGE, the X4023x cancels the write operation. There-
fore, the contents of the EEPROM array does not
change.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an ACKNOWLEDGE
and then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an ACKNOWLEDGE during the ninth
clock and then issues a STOP condition (See Figure 14
for the address, ACKNOWLEDGE, and data transfer
sequence).
EEPROM Array Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current EEPROM Address
Read, Random EEPROM Read, and Sequential
EEPROM Read.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a STOP condi-
tion during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a STOP condition.
Another important point to note regarding the “Current
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access
to a DCP or the CR Register (i.e.: an operation using
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
Characteristics subject to change without notice. 16 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
READ Operation
WRITE Operation
Signals from
the Master
S
t
S
t
S
t
o
p
Slave
Address
Slave
Address
Address Byte
a
r
a
r
t
t
SDA Bus
1 0 1 0 0 0 0
0
1 0 1 0 0 0 0
1
A
C
K
A
C
K
A
C
K
Signalsfrom
the Slave
Data
“Dummy”Write
Figure 15. Random EEPROM Address Read Sequence
the Device Type Identifier 1010111 or 1010010). Imme-
diately after an operation to a DCP or CR Register is
performed, only a “Random EEPROM Read” is avail-
able. Immediately following a “Random EEPROM
Read” , a “Current EEPROM Address Read” or
“Sequential EEPROM Read” is once again available
(assuming that no access to a DCP or CR Register
occur in the interim).
After the X4023x acknowledges the receipt of the
Address Byte, the master immediately issues another
START condition and the Slave Address Byte with the
R/W bit set to one. This is followed by an ACKNOWL-
EDGE from the X4023x and then by the eight bit word.
The master terminates the read operation by not
responding with an ACKNOWLEDGE and instead issu-
ing a STOP condition (Refer to Figure 15).
A similar operation called “Set Current Address” also
exists. This operation is performed if a STOP is issued
instead of the second START shown in Figure 15. In
this case, the device sets the address pointer to that of
the Address Byte, and then goes into standby mode
after the STOP bit. All bus activity will be ignored until
another START is detected.
Random EEPROM Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the START condition and the Slave
Address Byte, receives an ACKNOWLEDGE, then
issues an Address Byte. This “dummy” Write operation
sets the address pointer to the address from which to
begin the random EEPROM read operation.
Slave
Address
Signals from
the Master
S
A
C
K
A
C
K
t
A
C
K
o
p
SDA Bus
0 0 0 1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
Figure 16. Sequential EEPROM Read Sequence
Characteristics subject to change without notice. 17 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
WEL:Write Enable Latch (Volatile)
CS3
BL0
CS7 CS6
CS4
BL1
CS5
CS2 CS1 CS0
The WEL bit controls the Write Enable status of the
entire X4023x device. This bit must first be enabled
before ANY write operation (to DCPs, EEPROM mem-
ory array, or the CR register). If the WEL bit is not first
enabled, then ANY proceeding (volatile or nonvolatile)
write operation to DCPs, EEPROM array, as well as the
CR register, is aborted and no ACKNOWLEDGE is
issued after a Data Byte.
PUP1
NV
V2FS V3FS
RWEL
WEL
PUP0
NV
NV
NV
Bit(s)
Description
Write Enable Latch bit
WEL
RWEL
Register Write Enable Latch bit
V2MON Output Flag Status
V3MON Output Flag Status
Sets the Block Lock partition
Sets the Power On Reset time
V2FS
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state. The WEL bit is enabled / set by
writing 00000010 to the CR register. Once enabled, the
WEL bit remains set to “1” until either it is reset to “0”
(by writing 00000000 to the CR register) or until the
X4023x powers down, and then up again.
V3FS
BL1 - BL0
PUP1 - PUP0
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
Figure 17. CR Register Format
Writes to the WEL bit do not cause an internal high
voltage write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition
is executed in the CR Write command sequence (See
Figure 18).
Sequential EEPROM Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an ACKNOWLEDGE,
indicating it requires additional data. The X4023x con-
tinues to output a Data Byte for each ACKNOWLEDGE
received. The master terminates the read operation by
not responding with an ACKNOWLEDGE and instead
issuing a STOP condition.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CR) Register Write Enable
status of the X4023x. Therefore, in order to write to any
of the bits of the CR Register (except WEL), the RWEL
bit must first be set to “1”. The RWEL bit is a volatile bit
that powers up in the disabled, LOW (“0”) state.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through the entire memory contents to be serially read
during one operation. At the end of the address space
the counter “rolls over” to address 00h and the device
continues to output data for each ACKNOWLEDGE
received (Refer to Figure 16).
It must be noted that the RWEL bit can only be set,
once the WEL bit has first been enabled (See "CR
Register Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of three cases:
—After a successful write operation to any bits of the CR
register has been completed (See Figure 18).
CONTROL AND STATUS REGISTER
—When the X4023x is powered down.
The Control and Status (CR) Register provides the
user with a mechanism for changing and reading the
status of various parameters of the X4023x (See Fig-
ure 17).
—When attempting to write to a Block Lock protected
region of the EEPROM memory (See "BL1, BL0: Block
Lock protection bits - (Nonvolatile)", below).
BL1, BL0: Block Lock protection bits - (Nonvolatile)
The CR register is a combination of both volatile and
nonvolatile bits. The nonvolatile bits of the CR register
The Block Lock protection bits (BL1 and BL0) are used
to:
retain their stored values even when V
is powered
CC
down, then powered back up. The volatile bits however,
will always power up to a known logic state “0” (irre-
spective of their value at power down).
—Inhibit a write operation from being performed to certain
addresses of the EEPROM memory array
—Inhibit a DCP write operation (changing the “wiper posi-
tion”).
A detailed description of the function of each of the CR
register bits follows:
Characteristics subject to change without notice. 18 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
SCL
SDA
CS0
CS2CS1
1
CS7 CS6
S
T
A
R
T
1
0
1
0
0
1
0
R/W A
1
1
1
1
1
1
1
A
C
K
CS5 CS4 CS3
A
C
K
S
T
O
P
C
K
SLAVE ADDRESS BYTE
ADDRESS BYTE
CR REGISTER DATA IN
Figure 18. CR Register Write Command Sequence
The region of EEPROM memory which is protected /
locked is determined by the combination of the BL1
and BL0 bits written to the CR register. It is possible to
lock the regions of EEPROM memory shown in the
table below:
ply voltage stabilizes above the V
threshold for a
TRIP1
period of time, t
(See Figure 30).
PURST
The Power On Reset bits, PUP1 and PUP0 of the CR
register determine the t delay time of the Power
PURST
On Reset circuitry (See "VOLTAGE MONITORING
FUNCTIONS"). These bits of the CR register are non-
volatile, and therefore power up to the last written state.
Protected Addresses
(Size)
Partition of array
locked
BL1 BL0
0
0
1
1
0
1
0
1
None (Default)
None (Default)
Upper 1/4
Upper 1/2
All
The nominal Power On Reset delay time can be
selected from the following table, by writing the appro-
priate bits to the CR register:
C0 - FF (64 bytes)
h
h
80 - FF (128 bytes)
h
h
00 - FF (256 bytes)
Power on Reset delay (t
)
h
h
PUP1
PUP0
PURESET
0
0
1
1
0
1
0
1
50ms
100ms (Default)
200ms
If the user attempts to perform a write operation on a
protected region of EEPROM memory, the operation is
aborted without changing any data in the array.
300ms
When the Block Lock bits of the CR register are set to
something other than BL1=0 and BL0=0, then the
“wiper position” of the DCPs cannot be changed - i.e.
DCP write operations cannot be conducted:
The default for these bits are PUP1 = 0, PUP0 = 1.
V2FS, V3FS:Voltage Monitor Status Bits (Volatile)
BL1 BL0
DCP Write Operation Permissible
Bits V2FS and V3FS of the CR register are latched, vol-
atile flag bits which indicate the status of the Voltage
Monitor reset output pins V2FAIL and V3FAIL.
0
0
1
1
0
1
0
1
YES (Default)
NO
NO
NO
At power up the VxFS (x=2,3) bits default to the value
“0”. These bits can be set to a “1” by writing the appro-
priate value to the CR register. To provide consistency
The factory default setting for these bits are BL1 = 0,
BL0 = 0.
between the VxFAIL and V
however, the status of
xFS
the V
bits can only be set to a “1” when the corre-
xFS
sponding VxFAIL output is HIGH.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X4023x is active (HIGH), then all nonvolatile write oper-
ations to both the EEPROM memory and DCPs are
inhibited, irrespective of the Block Lock bit settings
(See "WP:Write Protection Pin").
Once the VxFS bits have been set to “1”, they will be
reset to “0” if:
—The device is powered down, then back up,
—The corresponding V
output becomes LOW.
xFAIL
PUP1, PUP0: Power On Reset bits – (Nonvolatile)
Applying voltage to V
activates the Power On Reset
CC
circuit which holds RESET output HIGH, until the sup-
Characteristics subject to change without notice. 19 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
CR Register Write Operation
CR (Control) Register Read Operation
The CR register is accessed using the Slave Address
set to 1010010 (Refer to Figure 4). Following the Slave
Address Byte, access to the CR register requires an
Address Byte which must be set to FFh. Only one data
byte is allowed to be written for each CR register Write
operation. The user must issue a STOP, after sending
this byte to the register, to initiate the nonvolatile cycle
that stores the BP1, BP0, PUP1 and PUP0 bits. The
X4023x will not ACKNOWLEDGE any data bytes writ-
ten after the first byte is entered (Refer to Figure 18).
The contents of the CR Register can be read at any
time by performing a random read (See Figure 18).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each
register read operation. The X4023x resets itself after
the first byte is read. The master should supply a STOP
condition to be consistent with the bus protocol.
After setting the WEL and / or the RWEL bit(s) to a “1”,
a CR register read operation may o ur, without inter-
CC
rupting a proceeding CR register write operation.
Prior to writing to the CR register, the WEL and RWEL
bits must be set using a two step process, with the
whole sequence requiring 3 steps
DATA PROTECTION
There are a number of levels of data protection fea-
tures designed into the X4023x. Any write to the device
first requires setting of the WEL bit in the CR register. A
write to the CR register itself, further requires the set-
ting of the RWEL bit. Block Lock protection of the
device enables the user to inhibit writes to certain
regions of the EEPROM memory, as well as to all the
DCPs. One further level of data protection in the
X4023x, is incorporated in the form of the Write Protec-
tion pin.
—Write a 02H to the CR Register to set the Write Enable
Latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceded by a START
and ended with a STOP).
—Write a 06H to the CR Register to set the Register
Write Enable Latch (RWEL) AND the WEL bit. This is
also a volatile cycle. The zeros in the data byte are
required. (Operation preceded by a START and ended
with a STOP).
—Write a one byte value to the CR Register that has all
the bits set to the desired state. The CR register can be
represented as qxyst01r in binary, where xy are the
Voltage Monitor Output Status (V2FS and V3FS) bits, st
are the Block Lock Protection (BL1 and BL0) bits, and
WP:Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X4023x.
The table below (X4023x Write Permission Status)
summarizes the effect of the WP pin (and Block Lock),
on the write permission status of the device.
qr are the Power On Reset delay time (t
) control
PURST
bits (PUP1 - PUP0). This operation is proceeded by a
START and ended with a STOP bit. Since this is a non-
volatile write cycle, it will typically take 5ms to complete.
The RWEL bit is reset by this cycle and the sequence
must be repeated to change the nonvolatile bits again.
If bit 2 is set to ‘1’ in this third step (qxys t11r) then the
RWEL bit is set, but the V2FS, V3FS, PUP1, PUP0,
BL1 and BL0 bits remain unchanged. Writing a second
byte to the control register is not allowed. Doing so
aborts the write operation and the X4023x does not
return an ACKNOWLEDGE.
Additional Data Protection Features
In addition to the preceding features, the X4023x also
incorporates the following data protection functionality:
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvol-
atile write cycle.
VOLTAGE MONITORING FUNCTIONS
For example, a sequence of writes to the device CR
register consisting of [02H, 06H, 02H] will reset all of
the nonvolatile bits in the CR Register to “0”.
VCC Monitoring
The X4023x monitors the supply voltage and drives the
RESET output HIGH (using an external “pull up” resis-
It should be noted that a write to any nonvolatile bit of
CR register will be ignored if the Write Protect pin of the
X4023x is active (HIGH) (See "WP: Write Protection
Pin").
tor) if V
is lower than V
threshold. The RESET
CC
TRIP1
output will remain HIGH until V exceeds V
minimum time of t
pin is driven to a LOW state. See Figure 30.
for a
CC
TRIP1
. After this time, the RESET
PURST
Characteristics subject to change without notice. 20 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
For the Power On / Low Voltage Reset function of the
X4023x, the RESET output may be driven HIGH down
V
CC
V
TRIP1
to a V
of 1V (V
). See Figure 30. Another fea-
CC
RVALID
0 Volts
0 Volts
ture of the X4023x, is that the value of t
may be
PURST
selected in software via the CR register (See “PUP1,
PUP0: Power On Reset bits – (Nonvolatile)” on
page 19.).
MR
It is recommended to stop communication to the device
while RESET is HIGH. Also, setting the Manual Reset
(MR) pin HIGH overrides the Power On / Low Voltage
circuitry and forces the RESET output pin HIGH (See
"MR: Manual Reset").
RESET
0 Volts
t
PURST
Figure 19. Manual Reset Response
MR: Manual Reset
The RESET output can be forced HIGH externally
using the Manual Reset (MR) input. MR is a de-
bounced, TTL compatible input, and so it may be oper-
RESET remains HIGH for time t
after MR has
PURST
returned to its LOW state (See Figure 19). An external
“pull down” resistor is required to hold this pin (nor-
mally) LOW.
ated by connecting a push-button directly from V
the MR pin.
to
CC
READ Operation
WRITE Operation
Signals from the
Master
S
t
S
t
S
t
o
p
Slave
Address
Slave
Address
Address Byte
a
r
a
r
t
t
CS7
… CS0
SDA Bus
1 0 1 0 0 1 0
0
1 0 1 0 0 1 0
1
A
C
K
A
C
K
A
C
K
Signals from the
Slave
Data
“Dummy”Write
Figure 20. CR Register Read Command Sequence
X4023x Write Permission Status
BlockLock
Bits
Write to CR Register
Permitted
DCP Volatile Write
DCP Nonvolatile
Write Permitted
Write to EEPROM
Permitted
Nonvolatile
BL0 BL1 WP
Permitted
Volatile Bits
YES
Bits
x
1
0
x
1
0
1
x
0
1
x
0
1
1
1
0
0
0
NO
NO
NO
NO
NO
NO
YES
NO
NO
NO
NO
YES
NO
YES
NO
NO
YES
NO
Not in locked region
Not in locked region
Yes (All Array)
YES
YES
YES
YES
NO
YES
YES
YES
Characteristics subject to change without notice. 21 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
V2MON Monitoring
The X4023x asserts the V2FAIL output HIGH if the volt-
V
TRIPx
Vx
age V2MON exceeds the corresponding V
thresh-
TRIP2
0V
old (See Figure 21). The bit V2FS in the CR register is
then set to a “0” (assuming that it has been set to “1”
after system initialization).
VxFAIL
0V
The V2FAIL output may remain active HIGH with V
down to 1V. (See Figure 21)
CC
V
CC
V
TRIP1
V3MON Monitoring
The X4023x asserts the V3FAIL output HIGH if the volt-
age V3MON exceeds the corresponding V thresh-
0 Volts
(x = 2,3)
TRIP3
old (See Figure 21). The bit V3FS in the CR register is
then set to a “0” (assuming that it has been set to “1”
after system initialization).
Figure 21. Voltage Monitor Response
Setting a VTRIPx Voltage (x=1,2,3)
The V3FAIL output may remain active HIGH with V
CC
There are two procedures used to set the threshold
voltages (V ), depending if the threshold voltage to
down to 1V. V
Thresholds (x=1,2,3)
TRIPx
TRIPx
The X4023x is shipped with pre-programmed threshold
(V ) voltages. In applications where the required
be stored is higher or lower than the present value. For
example, if the present V is 2.9 V and the new
TRIPx
TRIPx
thresholds are different from the default values, or if a
higher precision / tolerance is required, the X4023x trip
points may be adjusted by the user, using the steps
detailed below.
V
is 3.2 V, the new voltage can be stored directly
TRIPx
into the V
cell. If however, the new setting is to be
TRIPx
lower than the present setting, then it is necessary to
“reset” the V voltage before setting the new value.
TRIPx
V
V
TRIPx
CC
V2MON,
V3MON
V
P
WP
0
1 2 3 4 5 6 7
0
1 2 3 4 5 6 7
0
1 2 3 4 5 6 7
SCL
00h
Data Byte †
SDA
†
01h† sets V
09h† sets V
0Dh† sets V
A0h
TRIP1
TRIP2
S
T
A
R
T
† All others Reserved.
TRIP3
Figure 22. Setting V
to a higher level (x=1,2,3).
TRIPx
Characteristics subject to change without notice. 22 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
LOW to complete the operation (See Figure 23). The
user does not have to set the WEL bit in the CR regis-
ter before performing this write sequence.
Setting a Higher VTRIPx Voltage (x=1,2,3)
To set a V
threshold to a new voltage which is
TRIPx
higher than the present threshold, the user must apply
the desired V threshold voltage to the correspond-
TRIPx
After being reset, the value of V
nal value of 1.7V.
becomes a nomi-
TRIPx
ing input pin (V , V2MON or V3MON). Then, a pro-
CC
gramming voltage (Vp) must be applied to the WP pin
before a START condition is set up on SDA. Next, issue
on the SDA pin the Slave Address A0h, followed by the
VTRIPx Accuracy (x=1,2,3).
The accuracy with which the V
thresholds are set,
TRIPx
Byte Address 01h for V
, 09h for V
, and 0Dh
TRIP1
TRIP2
can be controlled using the iterative process shown in
Figure 24.
for V
, and a 00h Data Byte in order to program
TRIP3
V
. The STOP bit following a valid write operation
TRIPx
initiates the programming sequence. Pin WP must then
be brought LOW to complete the operation (See Figure
23). The user does not have to set the WEL bit in the
CR register before performing this write sequence.
If the desired threshold is less that the present thresh-
old voltage, then it must first be “reset” (See "Resetting
the V
Voltage (x=1,2,3).").
TRIPx
The desired threshold voltage is then applied to the
Setting a Lower V
Voltage (x=1,2,3).
TRIPx
appropriate input pin (V , V2MON or V3MON) and
CC
the procedure described in Section “Setting a Higher
In order to set V
present value, then V
to a lower voltage than the
TRIPx
V
Voltage“ must be followed.
TRIPx
must first be “reset” accord-
TRIPx
ing to the procedure described below. Once V
has
TRIPx
Once the desired V
error between the desired and (new) actual set thresh-
old can be determined. This is achieved by applying
threshold has been set, the
TRIPx
been “reset”, then V
can be set to the desired volt-
TRIPx
age using the procedure described in “Setting a Higher
Voltage”.
V
TRIPx
V
to the device, and then applying a test voltage
CC
higher than the desired threshold voltage, to the input
pin of the voltage monitor circuit whose V was
Resetting the VTRIPx Voltage (x=1,2,3).
TRIPx
programmed. For example, if V
desired level of 3.0 V, then a test voltage of 3.4 V may
be applied to the voltage monitor input pin V2MON. In
was set to a
To reset a V
voltage, apply the programming volt-
TRIP2
TRIPx
age (Vp) to the WP pin before a START condition is set
up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
the case of setting of V
then only V
need be
TRIP1
CC
applied. In all cases, care should be taken not to
exceed the maximum input voltage limits.
V
, 0Bh for V
, and 0Fh for V
, followed
TRIP1
TRIP2
TRIP3
by 00h for the Data Byte in order to reset V
. The
TRIPx
STOP bit following a valid write operation initiates the
programming sequence. Pin WP must then be brought
V
P
WP
0
1
2
3
4
5
6
7
0
1 2 3 4 5 6 7
0
1 2 3 4 5 6 7
SCL
00h †
Data Byte
SDA
A0h†
03h† Resets VTRIP1
0Bh† Resets VTRIP2
0Fh† Resets VTRIP3
S
T
A
R
T
† All others Reserved.
Figure 23. Resetting the V
Level
TRIPx
Characteristics subject to change without notice. 23 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
After applying the test voltage to the voltage monitor
input pin, the test voltage can be decreased (either in
discrete steps, or continuously) until the output of the
voltage monitor circuit changes state. At this point, the
error between the actual / measured, and desired
threshold levels is calculated.
put level of pin V2FAIL from a LOW to a HIGH, when
V2MON reaches 3.09 V. From this, it can be calculated
that the programming error is 3.09 - 3.0 = 0.09 V.
If the error between the desired and measured V
is
TRIPx
less than the maximum desired error, then the program-
ming process may be terminated. If however, the error is
greater than the maximum desired error, then another
For example, the desired threshold for V
is set to
TRIP2
3.0 V, and a test voltage of 3.4 V was applied to the input
iteration of the V
programming sequence can be
TRIPx
pin V2MON (after applying power to V ).The input volt-
age is decreased, and found to trip the associated out-
performed (using the calculated error) in order to further
increase the accuracy of the threshold voltage.
CC
Note: X = 1,2,3.
V
Programming
TRIPx
Let: MDE = Maximum Desired Error
MDE+
NO
Desired V
present value?
<
TRIPx
Acceptable
Desired Value
Error Range
MDE–
YES
Execute
TRIPx
Sequence
Error = Actual – Desired
V
Reset
Set Vx = desired V
TRIPx
Execute
TRIPx
Sequence
New Vx applied =
New Vx applied =
Old Vx applied + | Error |
Set Higher V
Old Vx applied - | Error |
Execute
TRIPx
Sequence
Power Down
Reset V
Ramp up Vx
NO
Output
switches?
YES
Error < MDE–
TRIPx
TRIPx
Error >MDE+
Actual V
- Desired V
= Error
| Error | < | MDE |
DONE
Figure 24. V
Setting / Reset Sequence (x=1,2,3)
TRIPx
Characteristics subject to change without notice. 24 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
If the calculated error is greater than zero, then the
voltage equal to the last previously programmed volt-
age, minus the last previously calculated error. There-
V
must first be “reset”, and then programmed to
TRIPx
the a value equal to the previously set V
minus the
fore, we must apply V
= 2.91 V to pin V2MON and
TRIPx
TRIP2
calculated error. If it is the case that the error is less
than zero, then the V must be programmed to a
execute the programming sequence (See "Setting a
Higher V Voltage (x=1,2,3)").
TRIPx
TRIPx
value equal to the previously set V
lute value of the calculated error.
plus the abso-
TRIPx
Using this process, the desired accuracy for a particu-
lar V threshold may be attained using a succes-
TRIPx
Continuing the previous example, we see that the cal-
culated error was 0.09V. Since this is greater than zero,
sive number of iterations.
we must first “reset” the V
threshold, then apply a
TRIP2
Characteristics subject to change without notice. 25 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
ABSOLUTE MAXIMUM RATINGS
Parameter
Min.
–65
Max.
+135
+150
+15
Units
°C
°C
V
Temperature under Bias
Storage Temperature
–65
Voltage on WP pin (With respect to VSS)
Voltage on other pins (With respect to VSS)
–1.0
–1.0
+7
V
Voltage on R – Voltage on R (x=0,1,2. Referenced to V
Hx Lx
)
V
V
SS
CC
D.C. Output Current (SDA,RESETRESET,V2FAIL,V3FAIL)
0
5
300
7
mA
°C
V
Lead Temperature (Soldering, 10 seconds)
Supply Voltage Limits (Applied V voltage, referenced to V
CC
)
2.7
SS
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Units
Industrial
–40
+85
°C
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.This is a stress rating
only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 25. Equivalent A.C. Circuit
V
= 5V
CC
2300Ω
SDA
V2FAIL
V3FAIL
RESET
100pF
Figure 26. DCP SPICE Macromodel
R
TOTAL
R
R
Hx
Lx
C
L
C
H
10pF
R
W
C
10pF
W
25pF
(x=0,1,2)
R
Wx
Characteristics subject to change without notice. 26 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
TIMING DIAGRAMS
Figure 27. Bus Timing
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA IN
t
t
t
BUF
AA
DH
SDA OUT
Figure 28. WP Pin Timing
START
SCL
Clk 1
Clk 9
SDA IN
WP
t
t
HD:WP
SU:WP
Figure 29. Write Cycle Timing
SCL
8th bit of last byte
ACK
SDA
t
WC
Stop
Condition
Start
Condition
Characteristics subject to change without notice. 27 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
Figure 30. Power-Up and Power-Down Timing
t
t
F
R
V
CC
V
TRIP1
0 Volts
t
PURST
t
PURST
t
t
RPD
RPD
RESET
MR
0 Volts
0 Volts
Figure 31. Manual Reset Timing Diagram
MR
t
MRPW
0 Volts
t
PURST
t
MRD
RESET
0 Volts
V
CC
V
CC
V
TRIP1
Characteristics subject to change without notice. 28 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
Figure 32. V2MON, V3MON Timing Diagram
t
t
Rx
Fx
Vx
V
TRIPx
t
t
RPDx
RPDx
t
RPDx
0 Volts
t
RPDx
VxFAIL
0 Volts
V
CC
V
TRIP1
V
RVALID
0 Volts
Note : x = 2,3.
Characteristics subject to change without notice. 29 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
Figure 33. V
Programming Timing Diagram (x=1,2,3).
TRIPX
V
, V2MON, V3MON
CC
V
TRIPx
t
t
TSU
THD
V
P
WP
t
VPS
t
VPO
SCL
SDA
t
WC
00h
t
VPH
NOTE : V1/V must be greater than V2MON, V3MON when programming.
CC
Figure 34. DCP “Wiper Position”Timing
Rwx (x=0,1,2)
R
WX(n+1)
R
WX(n)
R
WX(n-1)
t
WR
Time
n = tap position
SCL
SDA
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A WT
0
0
0
0
0
P1 P0
A
C
K
A
S
T
C
K
C
K
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
Characteristics subject to change without notice. 30 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
D.C. OPERATING CHARACTERISTICS
Symbol
Parameter
Min Typ
Max
Unit
Test Conditions / Notes
Requires V > V or chip
will not operate.
CC
TRIP1
V
2.7
5.5
V
CC
Current into V
Pin (X4023x: Active)
CC
(1)
I
Read memory array (3)
f
= 400KHz
1
CC
SCL
0.4
1.5
mA
Write nonvolatile memory V
= 3.5V
CC
V
= V
SDA
CC
MR = VSS
WP = VSS or Open/Floating
= V (when no bus
Current into V
Pin (X4023x:Standby)
CC
With 2-Wire bus activity (3)
No 2-Wire bus activity
(2)
I
µA
2
CC
50.0
50.0
V
SCL
CC
V
= 3.5V
CC
activity else f
= 400kHz)
SCL
Input Leakage Current (SCL, SDA, MR)
Input Leakage Current (WP)
0.1
0.1
10
10
µA
µA
V
(4) = GND to V
IN
CC
.
I
I
LI
V
(5) = GND to V
Output Leakage Current (SDA, RESET,
V2FAIL, V3FAIL)
OUT
.
CC
10
µA
LO
X4023x is in Standby(2)
V
V
V
V
Programming Range
2.75
1.75
4.70
3.50
V
V
TRIP1PR
TRIP1
TRIPx
Programming Range (x=2,3)
PR
TRIPx
Factory shipped default option A
Factory shipped default option B
2.8 2.95
4.3 4.45
3.00
4.50
(6)
(6)
(6)
V
V
V
Pre - programmed V
Pre - programmed V
Pre - programmed V
threshold
threshold
threshold
V
V
V
TRIP1
TRIP2
TRIP3
TRIP1
TRIP2
TRIP3
Factory shipped default option A
Factory shipped default option B
2.05 2.20
2.8 2.95
2.25
3.00
Factory shipped default option A
Factory shipped default option B
1.60 1.75
1.60 1.75
1.80
1.80
V
, V2MON, V3MON to RESET,
CC
t
V2FAIL, V3FAIL propagation
delay (respectively)
20
µs
See (8)
RPDx
V2MON Input leakage current
V3MON Input leakage current
V
=V
=V
1
1
SDA SCL
CC
Others=GND or V
I
µA
V
Vx
(7)
CC
V
Input LOW Voltage (SCL, SDA, WP, MR)
-0.5
2.0
0.8
IL
V
(7)
CC
+0.5
V
Input HIGH Voltage (SCL,SDA, WP, MR)
V
IH
RESET, V2FAIL, V3FAIL, SDA Output
Low Voltage
V
0.4
V
I
= 2.0mA
OLx
SINK
Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the
Slave Address Byte are incorrect; 200nS after a STOP ending a read operation; or t after a STOP ending a write operation.
WC
Notes: 2. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; t
after a STOP that
WC
initiates a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave
Address Byte.
Notes: 3. Current through external pull up resistor not included.
Notes: 4.
Notes: 5.
V
= Voltage applied to input pin.
IN
V
= Voltage applied to output pin.
OUT
Notes: 6. See “ORDERING INFORMATION” on page 39.
Notes: 7. Min. and V Max. are for reference only and are not tested
V
IL
IH
Notes: 8. Equivalent input circuit for V
XMON
V
XMON
+
–
V
REF
Characteristics subject to change without notice. 31 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
A.C. CHARACTERISTICS (See Figure 27, Figure 28, Figure 29)
400kHz
Symbol
Parameter
Min
0
Max
Units
KHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
SCL Clock Frequency
400
SCL
(5)
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
50
IN
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.9
µs
µs
µs
µs
µs
µs
ns
AA
BUF
LOW
Clock HIGH Time
HIGH
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
DH
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
µs
µs
ns
Stop Condition Setup Time
Data Output Hold Time
0.6
50
(5)
R
20 +.1Cb(2)
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
300
300
ns
(5)
F
20 +.1Cb(2)
t
t
t
ns
0.6
0
µs
µs
pF
SU:WP
HD:WP
WP Hold Time
Cb
Capacitive load for each bus line
400
A.C.TEST CONDITIONS
Input Pulse Levels
0.1V
CC
to 0.9V
CC
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
10ns
0.5V
CC
See Figure 25
NONVOLATILE WRITE CYCLE TIMING
Symbol
(4)
Parameter
Nonvolatile Write Cycle Time
Min.
Typ.(1)
Max.
Units
t
5
10
ms
WC
CAPACITANCE (T = 25°C, F = 1.0 MHZ, V = 5V)
A
CC
Parameter
Symbol
Max
8
Units
Test Conditions
= 0V
(5)
V
C
C
Output Capacitance (SDA, RESET, V2FAIL, V3FAIL)
Input Capacitance (SCL, WP, MR)
pF
pF
OUT
OUT
(5)
IN
V
= 0V
6
IN
Notes: 1. Typical values are for T = 25°C and V = 5.0V
A
CC
Notes: 2. Cb = total capacitance of one bus line in pF.
Notes: 3. Over recommended operating conditions, unless otherwise specified
Notes: 4.
t
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write
WC
cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Notes: 5. This parameter is not 100% tested.
Characteristics subject to change without notice. 32 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
POTENTIOMETER CHARACTERISTICS
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions/Notes
In a ratiometric circuit, R
TOTAL
divides out of the equation and
accuracy is determined by
XDCP resolution.
R
End to End Resistance Tolerance
–20
+20
%
TOL
V
V
R Terminal Voltage (x=0,1,2)
H
VSS
VSS
V
V
CC
RHx
RLx
R Terminal internally tied to
L
gnd.
V
P
R Terminal Voltage (x=0,1,2)
L
VSS
10
5
mW
mW
R
R
V
= 10 KΩ (DCP0, DCP1)
= 100 KΩ (DCP2)
TOTAL
Power Rating(1)
R
TOTAL
= 5 V, V
= VSS (x=0,1,2),
= V
,
RHx
CC
CC
200
400
400
Ω
V
RLx
I
= 50 uA /500 uA (100/10 kΩ).
W
R
DCP Wiper Resistance
W
V
= 2.7 V, V
= V , V
RHx RLx
CC
CC
= VSS (x=0,1,2),
1200
4.4
Ω
I
= 27 uA /270 uA (100/10 kΩ).
W
I
Wiper Current
Noise
mA
W
mV /
R
R
= 10 kΩ (DCP0, DCP1)
TOTAL
√(Hz)
mV /
√(Hz)
= 100 kΩ (DCP2)
TOTAL
Absolute Linearity(2)
Relative Linearity(3)
-1
-1
+1
+1
R
R
R
R
– R
MI(4)
MI(4)
w(n)(actual)
w(n)(expected)
]
w(n)+MI
– [R
w(n+1)
300
300
ppm/°C
ppm/°C
= 10 kΩ (DCP0, DCP1)
= 100 kΩ (DCP2)
TOTAL
TOTAL
R
Temperature Coefficient
TOTAL
Ratiometric Temperature Coefficient
Potentiometer Capacitances
30
ppm/°C (Voltage divider configuration)
C /C /
10/10/
25
pF
H
L
See Figure 26.
C
W
t
Wiper Response time
200
µs
See Figure 34.
wr
Notes: 1. Power Rating between the wiper terminal R
WX(n)
and the end terminals R
V
- for ANY tap position n, (x=0,1,2).
SS
HX
Notes: 2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance
(expected)) = 1 Ml Maximum (x=0,1,2).
=
(R
(actual) –
wx(n)
R
wx(n)
Notes: 3. Relative Linearity is a measure of the error in step size between taps = R
– [R
+ Ml] = 0.2 Ml (x=0,1,2)
wx(n)
Wx(n+1)
Notes: 4. 1 Ml = Minimum Increment = R
TOT
/ (Number of taps in DCP - 1).
Notes: 5. Typical values are for T = 25°C and nominal supply voltage.
A
Notes: 6. This parameter is periodically sampled and not 100% tested.
Characteristics subject to change without notice. 33 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
V
(X=1,2,3) PROGRAMMING PARAMETERS (See Figure 33)
TRIPX
Parameter
Description
Program Enable Voltage Setup time
Program Enable Voltage Hold time
Setup time
Min
10
Typ
Max
Units
µs
t
V
V
V
V
V
VPS
TRIPx
TRIPx
TRIPx
TRIPx
TRIPx
t
10
µs
VPH
t
10
µs
TSU
t
Hold (stable) time
10
µs
THD
Program Enable Voltage Off time
(Between successive adjustments)
t
1
ms
VPO
t
V
Write Cycle time
5
10
15
ms
V
WC
TRIPx
V
P
Programming Voltage
Program Voltage accuracy
10
V
TRIPx
V
ta
-100
+100
+25
mV
mV
Programmed at 25°C.)
V
Program variation after programming (-40 - 85°C).
TRIP
V
tv
-25
+10
(Programmed at 25°C.)
Notes: 100% tested.
Characteristics subject to change without notice. 34 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
RESET,V2FAIL, V3FAIL OUTPUT TIMING. (See Figure 30, Figure 31, Figure 32)
Symbol
Description
Condition
Min.
25
Typ.
50
Max.
75
Units
ms
PUP1= 0, PUP0= 0
PUP1= 0, PUP0= 1
PUP1= 1, PUP0= 0
PUP1= 1, PUP0= 1
50
100
200
300
150
300
450
ms
t
Power On Reset delay time
PURST
100
150
ms
ms
MR to RESET propagation
delay
(31)(2)
MRD
See (1),(2),(4).
t
5
µs
t
MR pulse width
500
ns
MRDPW
V
, V2MON, V3MON to
CC
RESET, V2FAIL, V3FAIL
propagation
t
See (5)
20
µs
RPDx
delay (respectively)
V
Time
, V2MON, V3MON Fall
CC
t
t
20
20
1
mV/µs
mV/µs
V
Fx
V
, V2MON, V3MON Rise
CC
Time
Rx
V
for RESET, V2FAIL,
CC
V
V3FAIL Valid(3).
RVALID
Notes: 1. See Figure 31 for timing diagram.
Notes: 2. See Figure 25 for equivalent load.
Notes: 3. This parameter describes the lowest possible V
level for which the outputs RESET, V2FAIL, and V3FAIL will be correct with
CC
respect to their inputs (V , V2MON, V3MON).
CC
Notes: 4. From MR rising edge crossing V , to RESET rising edge crossing V
.
IH
OH
Notes: 5. Equivalent input circuit for V
XMON
V
XMON
+
–
OUTPUT
V
REF
t
= 20µs worst case
RPDX
Characteristics subject to change without notice. 35 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
APPENDIX 1
DCP1 (100 Tap) Tap position to Data Byte translation Table
Data Byte
Tap
Position
Decimal
Binary
0
1
0
1
0000 0000
0000 0001
.
.
.
.
.
.
23
24
25
26
23
24
56
55
0001 0111
0001 1000
0011 1000
0011 0111
.
.
.
.
.
.
48
49
50
51
33
32
64
65
0010 0001
0010 0000
0100 0000
0100 0001
.
.
.
.
.
.
73
74
75
76
87
88
0101 0111
0101 1000
0111 1000
0111 0111
120
119
.
.
.
.
.
.
98
99
97
96
0110 0001
0110 0000
Characteristics subject to change without notice. 36 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example.
unsigned DCP1_TAP_Position(int tap_pos)
{
int block;
int i;
int offset;
int wcr_val;
offset = 0;
block = tap_pos / 25;
if (block < 0) return ((unsigned)0);
else if (block <= 3)
{
switch(block)
{ case (0): return ((unsigned)tap_pos) ;
case (1):
{
wcr_val = 56;
offset = tap_pos - 25;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned) wcr_val);
}
case (2):
{
wcr_val = 64;
offset = tap_pos - 50;
for (i=0; i<= offset; i++) wcr_val++ ;
return ((unsigned) wcr_val);
}
case (3):
{
wcr_val = 120;
offset = tap_pos - 75;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned) wcr_val);
}
}
}
return((unsigned)01100000);
}
Characteristics subject to change without notice. 37 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
16-Lead Plastic, SOIC (300-mil body), Package Code S16
0.290 (7.37)
0.299 (7.60)
0.393 (10.00)
0.420 (10.65)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.403 (10.2 )
0.413 ( 10.5)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" Typical
X 45°
0° – 8°
0.050"
Typical
0.0075 (0.19)
0.010 (0.25)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" Typical
16 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 38 of 39
REV 1.0.7 2/11/04
www.xicor.com
X4023x
ORDERING INFORMATION
y
X4023x
-
P
T
Preset (Factory Shipped) V
Levels (x=1,2,3)
Threshold
TRIPx
Device
A = Optimized for 3.3 V system monitoring †
3.3 10%, 2.5 10%, 1.8 V +10%/–0%
B = Optimized for 5 V system monitoring †
5.0 10%, 3.3 10%, 1.8 V +10%/–0%
Temperature Range
x
1
3
5
7
9
DEVICE
X40231
X40233
X40235
X40237
X40239
I = Industrial –40°C to +85°C
Package
S16 = 16-Lead Widebody SOIC (300 mil)
†
For details of preset threshold values, See "D.C. OPERATING CHARACTERISTICS"
LIMITED WARRANTY
©Xicor, Inc. 2001 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS ANDTRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 39 of 39
REV 1.0.7 2/11/04
www.xicor.com
相关型号：
X40237S16I-B
Power Supply Support Circuit, Adjustable, 3 Channel, PDSO16, 0.300 INCH, PLASTIC, SOIC-16
XICOR
X40237S16I-BT1
Power Supply Support Circuit, Adjustable, 3 Channel, PDSO16, 0.300 INCH, PLASTIC, SOIC-16
XICOR
X40239S16I-AT1
Power Supply Support Circuit, Adjustable, 3 Channel, PDSO16, 0.300 INCH, PLASTIC, SOIC-16
XICOR
X403-250M
LVPECL Output Clock Oscillator, 250MHz Nom, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKAGE-6
CONNOR-WINFIE
X403-700M
LVPECL Output Clock Oscillator, 700MHz Nom, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKAGE-6
CONNOR-WINFIE
©2020 ICPDF网 联系我们和版权申明