X40421V14I-A [XICOR]
Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch; 双电压监控器，集成了CPU监控系统和电池开关
| 型号： | X40421V14I-A |
| 厂家： | 
XICOR INC. |
| 描述： | Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch |
| 文件： | 总25页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
New Features
• Monitor Voltages: 5V to 1.6V
• Memory Security
• Battery Switch Backup
• V
5mA to 50mA
OUT
Preliminary Datasheet
4kbit EEPROM
X40420/X40421
Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch
FEATURES
APPLICATIONS
• Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
• Communications Equipment
—Routers, Hubs, Switches
—Disk arrays
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Desktop Computers
—Network Servers
—V
Programmable down to 0.9V
TRIP2
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to V = 1V
CC
—Monitor two voltages or detect power fail
• Battery Switch Backup
• V
V
: 5mA to 50mA from V ; or 250µA from
OUT
BATT
CC
X40420/21
• Fault detection register
• Selectable power on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
• Debounced manual reset input
• Low power CMOS
Standard V
Level Standard V
Level Suffix
TRIP1
TRIP2
4.6V (+/-1%)
4.6V (+/-1%)
2.9V(+/-1.7%)
2.9V(+/-1.7%)
2.6V (+/-2%)
1.6V (+/-3%)
-A
-B
-C
See “Ordering Information” for more details
For Custom Settings, call Xicor.
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA typical battery current in backup mode
• 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0 or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
DESCRIPTION
The X40420/21 combines power-on reset control,
watchdog timer, supply voltage supervision, and sec-
ondary supervision, manual reset, and Block Lock™
protect serial EEPROM in one package. This combina-
tion lowers system cost, reduces board space require-
ments, and increases reliability.
Applying voltage to V
activates the power on reset
CC
circuit which holds RESET/RESET active for a period of
time.This allows the power supply and system oscillator
to stabilize before the processor can execute code.
—14-lead SOIC,TSSOP
BLOCK DIAGRAM
V
OUT
+
-
V2FAIL
WDO
V2MON
V
TRIP2
V2 Monitor
Logic
Watchdog
and
Reset Logic
Fault Detection
Register
Data
Register
SDA
V
OUT
Status
Register
WP
Command
Decode Test
& Control
EEPROM
Array
MR
RESET
X40420
Logic
SCL
Power on,
Manual Reset
Low Voltage
Reset
V
OUT
RESET
X40421
+
-
V
CC
V
TRIP1
Generation
(V1MON)
V
Monitor
CC
Logic
BATT-ON
LOWLINE
System
Battery
Switch
V
OUT
V
BATT
Characteristics subject to change without notice. 1 of 25
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X40420/X40421 – Preliminary
Low V
detection circuitry protects the user’s system
selected, the interval does not change, even after
cycling the power.
CC
from low voltage conditions, resetting the system when
falls below the minimum V point. RESET/
V
CC
TRIP1
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock protection. The
array is internally organized as x 8. The device features
an 2-wire interface and software protocol allowing
operation on a two-wire bus.
RESET is active until V
returns to proper operating
CC
level and stabilizes. A second voltage monitor circuit
tracks the unregulated supply to provide a power fail
warning or monitors different power supply voltage.
Three common low voltage combinations are available,
however, Xicor’s unique circuits allows the threshold for
either voltage monitor to be reprogrammed to meet
special needs or to fine-tune the threshold for applica-
tions requiring higher precision.
The device utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
Example Application
A manual reset input provides debounce circuitry for
minimum reset component count.
Unreg.
Supply
5V
REG
A battery switch circuit compares V
with V
input
CC
BATT
and connects V
to whichever is higher. This pro-
OUT
vides voltage to external SRAM or other circuits in the
event of main power failure. The X40420/21 can drive
BATT-ON
CC
Enable
SRAM
V
V
V
OUT
BATT
50mA from V
switches to V
to 250µA from V
. The device only
CC
BATT
Addr
+
X40420/21
V2MON
when V
drops below the low V
BATT
CC
CC
Addr
uC
voltage threshold and V
.
BATT
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
NMI
V2FAIL
V
CC
VDO
RESET
MR
IRQ
RESET
Manual
Reset
SCL SDA
I2C
PIN CONFIGURATION
X40421
14-Pin SOIC, TSSOP
X40420
14-Pin SOIC, TSSOP
V
V2FAIL
V2MON
LOWLINE
WDO
V
V2FAIL
V2MON
1
2
3
4
14
13
12
11
1
2
3
4
14
13
12
11
CC
CC
BATT-ON
BATT-ON
V
LOWLINE
WDO
V
OUT
OUT
V
V
BATT
BATT
MR
RESET
MR
RESET
WP
SCL
SDA
WP
SCL
SDA
5
6
7
10
9
8
5
6
7
10
9
8
V
V
SS
SS
PIN DESCRIPTION
Pin
Name
Function
1
V2FAIL
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V
and
TRIP2
goes HIGH when V2MON exceeds V
. There is no power up reset delay circuitry on this pin.
TRIP2
2
V2MON
V2 Voltage Monitor Input. When the V2MON input is less than the V
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
voltage, V2FAIL goes
TRIP2
monitor a second power supply with no external components. Connect V2MON to V or V
SS
CC
when not used.
3
LOWLINE Early Low V Detect. This open drain output signal goes LOW when V
< V
.
CC
> V
CC
TRIP1
When V
, this pin is pulled high with the use of an external pull up resistor.
CC
TRIP1
Characteristics subject to change without notice. 2 of 25
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X40420/X40421 – Preliminary
PIN DESCRIPTION (Continued)
Pin
Name
Function
4
WDO
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
5
6
MR
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-
main HIGH/LOW until the pin is released and for the t
thereafter. It has an internal pull up resistor.
PURST
RESET/
RESET
RESET Output. (X40421) This open drain pin is an active LOW output which goes LOW whenever
falls below V voltage or if manual reset is asserted. This output stays active for the pro-
V
CC
TRIP1
grammed time period (t
and for t
) on power up. It will also stay active until manual reset is released
PURST
thereafter.
PURST
RESET Output. (X40420) This pin is an active HIGH open drain output which goes HIGH when-
ever V falls below V voltage or if manual reset is asserted. This output stays active for the
CC
TRIP1
programmed time period (t
) on power up. It will also stay active until manual reset is released
PURST
and for t
thereafter.
PURST
7
8
V
SS
Ground
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This pin
requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
9
SCL
WP
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10
Write Protect. WP HIGH prevents writes to any location in the device (including all the registers).
It has an internal pull down resistor. (>10MΩ typical)
11
12
V
Battery Supply Voltage. This input provides a backup supply in the event of a failure of the
BATT
primary V voltage. The V
voltage typically provides the supply voltage necessary to
CC
BATT
maintain the contents of SRAM and also powers the internal logic to “stay awake.” If the battery is
not used, connect V to ground.
BATT
V
Output Voltage. (V)
OUT
V
= V if V > V
.
OUT
CC
CC
TRIP1
IF V < V
CC
TRIP1
then V
= V if V > V
+ 0.03V
OUT
CC
CC
BATT
else V
= V
(ie if V < V
– 0.03V)
OUT
BATT
CC
BATT
Note: There is hysteresis around V
switchover voltage. A capacitance of 0.1µF must be connected to V
± 0.03V point to avoid oscillation at or near the
BATT
to ensure stability.
OUT
13
14
BATT-ON Battery On. This CMOS output goes HIGH when the V
switches to V
and goes LOW
OUT
BATT
when V
switches to V . It is used to drive an external PNP pass transistor when V = V
OUT
CC CC OUT
and current requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when
the V supply is fully functional. In the event of a V failure, the battery voltage is applied to the
CC
OUT
CC
V
pin and the external transistor is turned off. In this “backup condition,” the battery only needs
to supply enough voltage and current to keep SRAM devices from losing their data–there is no
communication at this time.
V
Supply Voltage
CC
Characteristics subject to change without notice. 3 of 25
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X40420/X40421 – Preliminary
PRINCIPLES OF OPERATION
Power On Reset
Low Voltage V2 Monitoring
The X40420/21 also monitors a second voltage level
and asserts V2FAIL if the voltage falls below a preset
Applying power to the X40420/21 activates a Power On
Reset Circuit that pulls the RESET/RESET pins active.
This signal provides several benefits.
minimum V
. The V2FAIL signal is either ORed
TRIP2
with RESET to prevent the microprocessor from oper-
ating in a power fail or brownout condition or used to
interrupt the microprocessor with notification of an
impending power failure. The V2FAIL signal remains
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
active until the V
drops below 1V (V
falling). It
CC
CC
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
also remains active until V2MON returns and exceeds
V
.
TRIP2
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
V2MON voltage monitor is powered by V
If V
CC
OUT.
and V
go away, V2MON cannot be monitored.
BATT
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
Figure 2. Two Uses of Multiple Voltage Monitoring
When V
exceeds the device V
threshold value
V
CC
TRIP1
OUT
for t
(selectable) the circuit releases the RESET
PURST
X40420
(X40421) and RESET (X40420) pin allowing the system
to begin operation.
5V
Unreg.
Supply
V
CC
System
Reset
Reg
RESET
V2MON
V2FAIL
Figure 1. Connecting a Manual Reset Push-Button
R
X40420/21
R
System
Reset
RESET
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
MR
V
OUT
Manual
Reset
X40421
Unreg.
Supply
5V
Reg
V
CC
RESET
V2MON
System
Reset
Manual Reset
3V
Reg
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains LOW for
V2FAIL
Notice: No external components required to monitor two voltages.
tPURST or till the push-button is released and for t
PURST
thereafter. A weak pull up resistor is connected to the
MR pin.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
WDO signal to go active. A minimum sequence to
reset the watchdog timer requires four microprocessor
instructions namely, a Start, Clock Low, Clock High and
Stop. The state of two nonvolatile control bits in the
Status Register determine the watchdog timer period.
The microprocessor can change these watchdog bits
by writing to the X40420/21 control register.
Low Voltage V1 Monitoring
During operation, the X40420/21 monitors the V
CC
level and asserts RESET if supply voltage falls below a
preset minimum V . The RESET signal prevents
TRIP1
the microprocessor from operating in a power fail or
brownout condition. The V1FAIL signal remains active
until the voltage drops below 1V. It also remains active
until V returns and exceeds V
for t
.
PURST
CC
TRIP1
Characteristics subject to change without notice. 4 of 25
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X40420/X40421 – Preliminary
Figure 3. V
Set/Reset Conditions
TRIPX
V
(X = 1, 2)
V
/V2MON
TRIPX
CC
V
P
0
WDO
0
7
0
7
7
SCL
SDA
t
WC
A0h
00h
Figure 4. Watchdog Restart
Data Byte in order to program V
. The STOP bit
TRIPx
following a valid write operation initiates the programming
sequence. Pin WDO must then be brought LOW to
complete the operation.
.6µs
1.3µs
SCL
SDA
To check if the V
has been set, set VXMON to a
TRIPX
value slightly greater than V
set). Slowly ramp down VXMON and observe when the
corresponding outputs (LOWLINE and V2FAIL) switch.
(that was previously
TRIPX
Start
Stop
WDT Reset
V1 AND V2 THRESHOLD PROGRAM PROCEDURE
(OPTIONAL)
The voltage at which this occurs is the V
(actual).
TRIPX
CASE A
The X40420/21 is shipped with standard V1 and V2
threshold (V
V
) voltages.These values will not
Now if the desired V
is greater than the V
TRIP1, TRIP2
TRIPX
TRIPX
change over normal operating and storage conditions.
However, in applications where the standard thresholds
are not exactly right, or if higher precision is needed in the
threshold value, the X40420 trip points may be adjusted.
The procedure is described below, and uses the applica-
tion of a high voltage control signal.
(actual), then add the difference between V
(desired) – V (actual) to the original V
TRIPX
desired.
TRIPX
TRIPX
This is your new V
that should be applied to
TRIPX
VXMON and the whole sequence should be repeated
again (see Figure 5).
CASE B
Setting a V
Voltage (x=1, 2)
TRIPx
Now if the V
(actual), is higher than the V
TRIPX
TRIPX
There are two procedures used to set the threshold volt-
ages (V ), depending if the threshold voltage to be
(desired), perform the reset sequence as described in the
next section. The new V voltage to be applied to
VXMON will now be: V
TRIPx
TRIPX
stored is higher or lower than the present value. For
example, if the present V is 2.9 V and the new
(desired) – (V
(actual)
TRIPX
TRIPX
TRIPx
– V
(desired)).
TRIPX
V
is 3.2 V, the new voltage can be stored directly
TRIPx
Note: 1. This operation does not corrupt the memory
into the V
cell. If however, the new setting is to be
TRIPx
array.
2. Set V
lower than the present setting, then it is necessary to
“reset” the V voltage before setting the new value.
= 5V, when V
is being pro-
CC
TRIP2
TRIPx
grammed
Setting a Higher V
Voltage (x=1, 2)
TRIPx
Setting a Lower V
Voltage (x=1, 2)
To set a V
threshold to a new voltage which is higher
TRIPx
TRIPx
than the present threshold, the user must apply the
desired V threshold voltage to the corresponding
In order to set V
present value, then V
to a lower voltage than the
must first be “reset” accord-
TRIPx
TRIPx
TRIPx
input pin (Vcc(V1MON) or V2MON). Then, a program-
ming voltage (Vp) must be applied to the WDO pin before
a START condition is set up on SDA. Next, issue on the
SDA pin the Slave Address A0h, followed by the Byte
ing to the procedure described below. Once V
TRIPx
has been “reset”, then V
can be set to the desired
TRIPx
voltage using the procedure described in “Setting a
Higher V Voltage”.
TRIPx
Address 01h for V
, and 09h for V
, and a 00h
TRIP1
TRIP2
Characteristics subject to change without notice. 5 of 25
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X40420/X40421 – Preliminary
Resetting the V
Voltage
TRIPx
Condition
Mode of Operation
Normal Operation
To reset a V
voltage, apply the programming voltage
TRIPx
V
> V
CC
TRIP1
(Vp) to the WDO pin before a START condition is set up
on SDA. Next, issue on the SDA pin the Slave Address
A0h followed by the Byte Address 03h for V
V
V
> V
&
Normal Operation without battery
backup capability
CC
TRIP1
= 0
BATT
and
TRIP1
0 ≤ V ≤ V
Battery Backup mode; RESET
signal is asserted. No communica-
tion to the device is allowed.
0Bh for V
, followed by 00h for the Data Byte in order
CC
TRIP1
BATT
TRIP2
and V < V
CC
to reset V
.The STOP bit following a valid write oper-
TRIPx
ation initiates the programming sequence. Pin WDO must
then be brought LOW to complete the operation.
Control Register
After being reset, the value of V
value of 1.7V or lesser.
becomes a nominal
TRIPx
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
Note:This operation does not corrupt the memory array.
System Battery Switch
The Control Register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh. It
can only be modified by performing a byte write operation
directly to the address of the register and only one data
byte is allowed for each register write operation. Prior to
writing to the Control Register, the WEL and RWEL bits
must be set using a two step process, with the whole
sequence requiring 3 steps. See "Writing to the Control
Registers" on page 8.
As long as V exceeds the low voltage detect threshold
CC
V
, V
is connected to V through a 5 Ohm (typi-
TRIP OUT CC
cal) switch. When the V
has fallen below V1
, then
CC
TRIP
V
is applied to V
if V
is or equal to or greater
CC
OUT
CC
than V
– 0.03V. When V drops to less than V
BATT
CC BATT
– 0.03V, then V
is connected to V
through an 80
OUT
BATT
Ohm (typical) switch. V
typically supplies the system
OUT
static RAM voltage, so the switchover circuit operates to
protect the contents of the static RAM during a power fail-
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, PUP0, and BP. The X40420 will not
acknowledge any data bytes written after the first byte is
entered.
ure. Typically, when V has failed, the SRAMs go into a
CC
lower power state and draw much less current than in
their active mode. When V
returns, V
switches
CC
OUT
back to V when V exceeds V + 0.03V. There is
CC
CC
BATT
a 60mV hysteresis around this battery switch threshold to
The state of the Control Register can be read at any time
by performing a random read at address 01Fh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condi-
tion to be consistent with the bus protocol, but a stop is
not required to end this operation.
prevent oscillations between supplies.
While V
is connected to V
the BATT-ON pin is
CC
OUT
pulled LOW. The signal can drive an external PNP tran-
sistor to provide additional current to the external circuits
during normal operation.
7
6
5
4
3
2
1
0
Operation
PUP1 WD1 WD0
BP
0
RWEL WEL PUP0
The device is in normal operation with V
as long as
CC
V
> V
. It switches to the battery backup mode
CC
TRIP1
RWEL: Register Write Enable Latch (Volatile)
when V goes away.
CC
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 5. Sample V
Reset Circuit
TRIP
V
P
Adjust
Run
V2FAIL
RESET
µC
1
6
2
7
14
13
9
X40420
V
TRIP1
8
Adj.
SCL
SDA
V
TRIP2
4.7K
Adj.
Characteristics subject to change without notice. 6 of 25
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X40420/X40421 – Preliminary
Figure 6. V
Set/Reset Sequence (X = 1, 2)
TRIPX
Vx = V , VxMON
CC
Note: X = 1, 2
V
Programming
TRIPX
Let: MDE = Maximum Desired Error
Desired
TRIPX
No
V
<
MDE+
Acceptable
Present Value
Desired Value
YES
Error Range
MDE–
Execute
Reset Sequence
V
TRIPX
Error = Actual - Desired
Set V = desired V
X
TRIPX
New V applied =
Execute
New V applied =
X
X
Set Higher V Sequence
Old V applied - | Error |
Old V applied + | Error |
X
X
X
Apply V and Voltage
CC
Execute Reset V
TRIPX
Sequence
> Desired V
to
V
TRIPX
X
NO
Decrease
V
X
Output Switches?
YES
V
Error < MDE–
Error > MDE+
Actual
TRIPX -
V
Desired
TRIPX
| Error | < | MDE |
DONE
WEL: Write Enable Latch (Volatile)
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeroes to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register.
Characteristics subject to change without notice. 7 of 25
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X40420/X40421 – Preliminary
BP: Block Protect Bit (Nonvolatile)
– Write a one byte value to the Control Register that
has all the control bits set to the desired state. The
Control register can be represented as qxys 001r in
binary, where xy are the WD bits, and st are the BP
bits and qr are the power up bits. This operation pro-
ceeded by a start and ended with a stop bit. Since
this is a nonvolatile write cycle it will take up to 10ms
to complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the non-
volatile bits again. If bit 2 is set to ‘1’ in this third step
(qxys 011r) then the RWEL bit is set, but the WD1,
WD0, PUP1, PUP0, and BP bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.
The Block Protect Bits BP determines which blocks of
the array are write protected. A write to a protected
block of memory is ignored. The block protect bit will
prevent write operations to half the array segment.
Protected Addresses
(Size)
Memory
Array Lock
0
1
None
None
100h – 1FFh (256 bytes)
Upper Half of
Memory Array
PUP1, PUP0: Power Up Bits (Nonvolatile)
The Power Up bits, PUP1 and PUP0, determine the
t
time delay. The nominal power up times are
PURST
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
shown in the following table.
PUP1 PUP0 Power on Reset Delay (t
)
PURST
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
0
0
1
1
0
1
0
1
50ms
200ms (default)
400ms
800ms
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile
bits in the Control Register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer.The options are shown below.
Note: 1. t
is set to 200ms as factory default.
PURST
WD1
WD0
Watchdog Time Out Period
1.4 seconds
2. Watchdog timer bits are shipped disabled.
0
0
1
1
0
1
0
1
200 milliseconds
Fault Detection Register (FDR)
25 milliseconds
The Fault Detection Register provides the user the sta-
tus of what causes the system reset active. The Man-
ual Reset Fail, Watchdog Timer Fail and Three Low
Voltage Fail bits are volatile
disabled (factory default)
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
7
6
5
4
3
2
1
0
LV1F LV2F
0
WDF MRF
0
0
0
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a start and ended with a stop).
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
– Write a 06H to the Control Register to set the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
There is no need to set the WEL or RWEL in the con-
trol register to access this fault detection register.
Characteristics subject to change without notice. 8 of 25
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X40420/X40421 – Preliminary
Figure 7. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
At power-up, the Fault Detection Register is defaulted
to all “0”. The system needs to initialize this register to
all “1” before the actual monitoring take place. In the
event of any one of the monitored sources failed. The
corresponding bits in the register will change from a “1”
to a “0” to indicate the failure. At this moment, the sys-
tem should perform a read to the register and noted
the cause of the reset. After reading the register the
system should reset the register back to all “1” again.
The state of the Fault Detection Register can be read
at any time by performing a random read at address
0FFh, using the special preamble.
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family
operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 7.
The FDR can be read by performing a random read at
0FFh address of the register at any time. Only one byte
of data is read by the register read operation.
MRF, Manual Reset Fail Bit (Volatile)
Serial Start Condition
The MRF bit will set to “0” when Manual Reset input
goes active.
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 8.
WDF, Watchdog Timer Fail Bit (Volatile)
The WDF bit will set to “0” when WDO goes active.
LV1F, Low V
Reset Fail Bit (Volatile)
CC
The LV1F bit will be set to “0” when V
(V1MON) falls
CC
Serial Stop Condition
below V
.
TRIP1
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.
LV2F, Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls below
V
.
TRIP2
Characteristics subject to change without notice. 9 of 25
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X40420/X40421 – Preliminary
Figure 8. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Acknowledge
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. See Figure 9.
Serial Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array.
After receipt of the Word Address Byte, the device
responds with an acknowledge, and awaits the next
eight bits of data. After receiving the 8 bits of the Data
Byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating
a stop condition, at which time the device begins the
internal write cycle to the nonvolatile memory. During
this internal write cycle, the device inputs are disabled, so
the device will not respond to any requests from the mas-
ter.The SDA output is at high impedance. See Figure 12.
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
A write to a protected block of memory will suppress
the acknowledge bit.
Figure 9. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
Characteristics subject to change without notice. 10 of 25
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X40420/X40421 – Preliminary
Figure 10. Byte Write Sequence
S
t
a
r
t
S
t
o
p
Signals from
the Master
Byte
Address
Slave
Address
Data
SDA Bus
0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Page Write
This means that the master can write 16 bytes to the
page starting at any location on that page. If the mas-
ter begins writing at location 10, and loads 12 bytes,
then the first 6 bytes are written to locations 10 through
15, and the last 6 bytes are written to locations 0
through 5. Afterwards, the address counter would point
to location 6 of the page that was just written. If the
master supplies more than 16 bytes of data, then new
data over-writes the previous data, one byte at a time.
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page.
Figure 11. Page Write Operation
(1 ≤ n ≤ 16)
S
S
t
o
p
t
a
r
Signals from
the Master
Byte
Address
Slave
Address
Data
(1)
Data
(n)
t
SDA Bus
1 0 1
0 0
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.
6 Bytes
6 Bytes
address pointer
ends here
Addr = 6
address
10
address
= 5
address
n-1
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 11 for the address, acknowl-
edge, and data transfer sequence.
Characteristics subject to change without notice. 11 of 25
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X40420/X40421 – Preliminary
Stops and Write Modes
Figure 13. Acknowledge Polling Sequence
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full data
byte plus its associated ACK is sent, then the device
will reset itself without performing the write. The con-
tents of the array will not be effected.
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Acknowledge Polling
Issue Slave Address
Byte (Read or Write)
Issue STOP
The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
device initiates the internal high voltage cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
See Figure 13.
NO
ACK
Returned?
YES
High Voltage Cycle
Complete. Continue
Command Sequence?
Issue STOP
NO
YES
Continue Normal
Read or Write
Serial Read Operations
Command Sequence
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
PROCEED
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master
issues the start condition and the Slave Address Byte,
receives an acknowledge, then issues the Word Address
Bytes. After acknowledging receipts of the Word Address
Bytes, the master immediately issues another start condi-
tion and the Slave Address Byte with the R/W bit set to
one. This is followed by an acknowledge from the device
and then by the eight bit word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. See Figure 15 for the
address, acknowledge, and data transfer sequence.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The mas-
ter terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. See Figure 14 for the
address, acknowledge, and data transfer sequence.
Characteristics subject to change without notice. 12 of 25
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X40420/X40421 – Preliminary
A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 15. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF
hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF
hex
General Purpose Memory Organization, A8:A0
Address: 00h to 1FFh
Sequential Read
General Purpose Memory Array Configuration
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
Memory Address
A8:A0
000h
Lower 256 bytes
0FFh
100h
Upper 256 bytes
Block Protect Option
1FFh
Slave Address Byte
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter “rolls
Following a start condition, the master must output a
Slave Address Byte.This byte consists of several parts:
– a device type identifier that is always “1010” when
accessing the array and “1011” when accessing the
control register and fault detection register.
over” to address 0000 and the device continues to out-
H
– two bits of “0”.
put data for each acknowledge received. See Figure 17
for the acknowledge and data transfer sequence.
– one bit that becomes the MSB of the memory
address X .
4
– last bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the opera-
tion to be performed.When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. See Figure 16.
Figure 14. Current Address Read Sequence
.
S
Slave
Address
t
a
r
S
t
o
p
Signals from
the Master
t
SDA Bus
1 0 1
0 0
1
A
Signals from
the Slave
C
Data
K
Characteristics subject to change without notice. 13 of 25
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X40420/X40421 – Preliminary
Figure 15. Random Address Read Sequence
S
S
t
S
t
o
p
t
a
r
Slave
Address
Byte
Address
Slave
Address
Signals from
the Master
a
r
t
t
SDA Bus
1
1 0 1 0 0
0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
Figure 16. X40410/11 Addressing
Slave Byte
General Purpose Memory
Control Register
1
1
1
0
0
0
1
1
1
0
1
1
0
0
0
0
R/W
R/W
R/W
A8
0
0
1
0
Fault Detection Register
Word Address
General Purpose Memory
Control Register
A0
1
A7 A6 A5 A4 A3 A2 A1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Fault Detection Register
1
Word Address
Data Protection
The word address is either supplied by the master or
obtained from an internal counter.
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
Operational Notes
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– SDA pin is the input mode.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
– RESET/RESET Signal is active for t
.
PURST
Figure 17. Sequential Read Sequence
S
t
Slave
Address
Signals from
the Master
o
A
C
K
A
C
K
A
C
K
p
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
Characteristics subject to change without notice. 14 of 25
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X40420/X40421 – Preliminary
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... –65°C to +135°C
Storage temperature ........................ –65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
respect to V ......................................–1.0V to +7V
SS
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Monitored
Version ChipSupplyVoltage
Voltages*
2.6 to 5.5V
1.6V to 3.6V
-A or -B
-C
2.7V to 5.5V
2.7V to 5.5V
–40°C
+85°C
*See ordering Info
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)
Symbol
Parameter
Active Supply Current (V ) Read
Min.
Typ.(5)
Max.
Unit
Test Conditions
(1)
CC1
I
1.5
mA
mA
µA
V
V
f
= V x 0.1
CC
CC
IL
(Excludes I
)
= V
x 0.9,
OUT
IH
CC
(1)
CC2
= 400kHz
I
Active Supply Current (V ) Write Non
3.0
10
SCL
CC
Volatile Memory (Excludes I
)
OUT
(1)(7)
I
I
Standby Current (V ) AC (WDT off)
6
V
= V x 0.1
CC
SB1
CC
IL
VIH = V
x 0.9
CC
f
, f
= 400kHz
SCL SDA
(2)(7)
SB2
Standby Current (V ) DC (WDT on)
25
30
µA
V
= V
= V
CC
SDA
SCL
CC
CC
Others = GND or V
(3)(7)
(7)
I
V
V
Current (Excludes I
Current (Excludes I
)
0.4
1
6
µA
µA
V
= V
OUT
CC
BATT1
BATT
OUT
I
)
V
V
= 2.8V
BATT
BATT2
BATT
OUT
(Battery Backup Mode)
= Open
OUT
(7)
V
Output Voltage (V > V
+ 0.03V or
V
V
–0.05V
V
V
I
I
= 5mA (4.5–5.5V)
= 50mA (4.5–
OUT1
CC
BATT
CC
OUT
OUT
V
> V
)
V
–0.5V
CC
TRIP1
CC
5.5V)
(7)
OUT2
V
Output Voltage (V < V
– 0.03V and
–0.2
I
= 250µA
OUT
CC
BATT
BATT
V
< V
) {Battery Backup}
CC
TRIP1
V
Output (BATT-ON) LOW Voltage
Output (BATT-ON) HIGH Voltage
0.4
V
V
I
I
= 3.0mA (4.5–5.5V)
= -0.4mA (4.5–
OLB
OL
V
V
–0.8
OHB
OUT
OH
5.5V)
(7)
BSH
V
Battery Switch Hysteresis
30
-30
mV Power Up
Power Down
(V
< V
)
CC
TRIP1
I
Input Leakage Current (SCL, MR, WP)
10
10
µA
µA
V
V
= GND to V
CC
LI
IL
I
Output Leakage Current (SDA, V2FAIL,
WDO, RESET)
= GND to V
SDA
CC
LO
Device is in Standby(2)
(3)
V
Input LOW Voltage (SDA, SCL, MR, WP)
Input HIGH Voltage (SDA, SCL, MR, WP)
-0.5
x 0.7
CC
V
x 0.3
V
V
IL
CC
(3)
IH
V
V
V
+ 0.5
CC
Characteristics subject to change without notice. 15 of 25
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X40420/X40421 – Preliminary
D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)
Symbol
Parameter
Min.
Typ.(5)
Max.
Unit
Test Conditions
(7)
HYS
V
Schmitt Trigger Input Hysteresis
• Fixed input level
0.2
.05 x V
CC
V
V
• V
related level
CC
V
Output LOW Voltage (SDA, RESET/
RESET, LOWLINE, V2FAIL, WDO)
0.4
V
I
I
= 3.0mA (2.7–5.5V)
= 1.8mA (2.4–3.6V)
OL
OL
OL
V
Supply
CC
(6)
V
V
Reset Trip Point Voltage Range
2.0
4.75
4.65
2.95
5
V
TRIP1
CC
4.55
2.85
4.6
2.9
A, B Version
C Version
(7)
t
µS
V
V
to LOWLINE
RPDL
TRIP1
Second Supply Monitor
(6)
TRIP2
V
V2MON Reset Trip Point Voltage Range
0.9
3.5
2.95
2.65
1.65
5
2.85
2.55
1.55
2.9
2.6
1.6
A Version
B Version
C Version
(7)
t
µS
V
to V2FAIL
RPD2
TRIP2
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or t after a stop ending a write operation.
WC
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; t
after a stop that ini-
WC
tiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address
Byte.
(3) Negative numbers indicate charging current, positive numbers indicate discharge current.
(4) V Min. and V Max. are for reference only and are not tested.
IL
IH
(5) At 25°C, V = 3V.
CC
(6) See ordering information for standard programming levels. For custom programming levels, contact factory.
(7) Based on characterization data only.
EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2)
∆V = 100mV
R
∆V
V
REF
VxMON
+
–
Output
V
REF
C
t
= 5µs worst case
RPDX
Characteristics subject to change without notice. 16 of 25
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X40420/X40421 – Preliminary
CAPACITANCE
Symbol
Parameter
Max.
Unit
Test Conditions
= 0V
(1)
OUT
C
Output Capacitance (SDA, RESET, RESET/LOWLINE,
V2FAIL, WDO)
8
pF
V
OUT
(1)
IN
C
Input Capacitance (SCL, WP)
6
pF
V
= 0V
IN
Note: (1) This parameter is not 100% tested.
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
SYMBOL TABLE
V
= 5V
CC
WAVEFORM
INPUTS
OUTPUTS
V
5V
V2MON
OUT
Must be
steady
Will be
steady
4.6KΩ
4.6KΩ
2.06KΩ
May change
from LOW
Will change
from LOW
to HIGH
RESET
WDO/LOWLINE
SDA
V2FAIL
30pF
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
30pF
30pF
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
A.C. TEST CONDITIONS)
N/A
Center Line
is High
Impedance
Input pulse levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
Input rise and fall times
10ns
Input and output timing levels
Output load
V
CC
Standard output load
Characteristics subject to change without notice. 17 of 25
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X40420/X40421 – Preliminary
A.C. CHARACTERISTICS
400kHz
Symbol
Parameter
Min.
Max.
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
pF
f
SCL Clock Frequency
400
SCL
t
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
IN
t
0.9
AA
t
BUF
t
LOW
t
Clock HIGH Time
HIGH
t
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
t
t
t
t
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
0.6
50
20 +.1Cb(1)
t
DH
t
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
300
300
R
t
20 +.1Cb(1)
F
t
0.6
0
SU:WP
t
WP Hold Time
HD:WP
Cb
Capacitive load for each bus line
400
Note: (1) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
t
t
t
t
R
F
HIGH
LOW
SCL
SDA IN
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
t
t
DH
t
AA
BUF
SDA OUT
Characteristics subject to change without notice. 18 of 25
REV 1.2.14 7/12/02
www.xicor.com
X40420/X40421 – Preliminary
WP Pin Timing
START
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
t
t
HD:WP
SU:WP
WP
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
t
WC
Stop
Start
Condition
Condition
Nonvolatile Write Cycle Timing
Symbol
Parameter
Write Cycle Time
Min.
Typ.(1)
Max.
10
Unit
(1)
WC
t
5
ms
Note: (1) t
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
WC
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Power Fail Timings
V
TRIPX
t
t
RPDL
RPDL
t
RPDX
V
or
t
CC
RPDX
t
RPDL
V2MON
t
RPDX
t
F
t
R
LOWLINE or
V2FAIL
V
RVALID
X = 1, 2
Characteristics subject to change without notice. 19 of 25
REV 1.2.14 7/12/02
www.xicor.com
X40420/X40421 – Preliminary
RESET/RESET/MR Timings
V
TRIP1
V
CC
t
t
PURST
PURST
t
RPD1
t
F
t
R
RESET
V
RVALID
RESET
MR
t
MD
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V)
Symbol
Parameters
Min.
Typ.
Max.
Unit
(1)
t
V
V
to RESET/RESET (Power down only)
to LOWLINE
5
µs
RPD1
t
TRIP1
TRIP1
RPDL
(1)
t
LOWLINE to RESET/RESET delay (Power down only) [= t
-t ]
500
ns
µs
LR
RPD1 RPDL
(1)
RPD2
t
V
to V2FAIL
5
TRIP2
t
Power On Reset delay:
PUP1=0, PUP0=0
PUP1=0, PUP0=1 (factory default)
PUP1=1, PUP0=0
PURST
50(1)
200
ms
ms
ms
ms
400(1)
800(1)
PUP1=1, PUP0=1
t
V
V
V2MON Fall Time
V2MON Rise Time
20
20
1
mV/µs
mV/µs
V
F
CC,
t
R
CC,
V
Reset Valid V
CC
RVALID
t
MR to RESET/ RESET delay (activation only)
Pulse width Suppression Time for MR
500
50
ns
MD
in1
t
ns
t
Watchdog Timer Period:
WD1=0, WD0=0
WD1=0, WD0=1
WDO
1.4(1)
200(1)
25
s
ms
ms
WD1=1, WD0=0
WD1=1, WD0=1 (factory default)
OFF
t
Watchdog Reset Time Out Delay
WD1=0, WD0=0
100
200
300
ms
RST1
WD1=0, WD0=1
t
Watchdog Reset Time Out Delay WD1=1, WD0=0
Watchdog timer restart pulse width
12.5
1
25
37.5
ms
µs
RST2
t
RSP
Note: (1) Based on characterization data.
Characteristics subject to change without notice. 20 of 25
REV 1.2.14 7/12/02
www.xicor.com
X40420/X40421 – Preliminary
Watchdog Time Out For 2-Wire Interface
Start
Start
Clockin (0 or 1)
t
RSP
< t
WDO
SCL
SDA
t
t
WDO
t
RST
RST
WDO
WDT
Restart
Start
Minimum Sequence to Reset WDT
SCL
SDA
V
Set/Reset Conditions
TRIPX
(V
)
V
/V2MON
TRIPX
CC
t
THD
V
t
P
TSU
WDO
t
VPS
t
VPO
t
VPH
7
SCL
SDA
0
0
7
0
7
t
WC
A0h
00h
Start
resets V
resets V
01h*
09h*
03h*
0Bh*
sets V
sets V
TRIP1
TRIP1
TRIP2
TRIP2
* all others reserved
Characteristics subject to change without notice. 21 of 25
REV 1.2.14 7/12/02
www.xicor.com
X40420/X40421 – Preliminary
V
, V
Programming Specifications: V
= 2.0–5.5V; Temperature = 25°C
TRIP1 TRIP2
CC
Parameter
Description
WDO Program Voltage Setup time
WDO Program Voltage Hold time
Min. Max. Unit
t
10
10
10
10
10
1
µs
µs
µs
µs
ms
ms
V
VPS
VPH
t
t
V
V
V
Level Setup time
Level Hold (stable) time
Program Cycle
TSU
TRIPX
TRIPX
TRIPX
t
THD
t
WC
t
Program Voltage Off time before next cycle
Programming Voltage
VPO
V
15
2.0
0.9
-25
10
18
4.75
3.5
P
V
V
V
V
V
Set Voltage Range
V
TRAN1
TRIP1
TRIP2
TRIPX
Set Voltage Range
V
TRAN2
V
Set Voltage variation after programming (0-75°C).
+25
mV
µs
tv
t
WDO Program Voltage Setup time
VPS
V
programming parameters are periodically sampled and are not 100% tested.
TRIPX
Characteristics subject to change without notice. 22 of 25
REV 1.2.14 7/12/02
www.xicor.com
X40420/X40421 – Preliminary
PACKAGING INFORMATION
14-Lead Plastic Small Outline Gullwing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"Typical
0° – 8°
0.250"
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
0.030"Typical
14 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 23 of 25
REV 1.2.14 7/12/02
www.xicor.com
X40420/X40421 – Preliminary
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 24 of 25
REV 1.2.14 7/12/02
www.xicor.com
X40420/X40421 – Preliminary
ORDERING INFORMATION
Operating
Temperature
Range
Monitored
Supplies
V
V
Part Number Part Number
TRIP1
TRIP2
V
Range
Range
Package
with RESET
with RESET
CC
2.9-5.5
2.6-5.5
1.6-3.6
4.6V±50mV
2.9V±50mV
14L SOIC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
X40420S14-A
X40421S14-A
X40420S14I-A X40421S14I-A
X40420V14-A X40421V14-A
X40420V14I-A X40421V14I-A
X40420S14-B X40421S14-B
X40420S14I-B X40421S14I-B
X40420V14-B X40421V14-B
X40420V14I-B X40421V14I-B
X40420S14-C X40421S14-C
X40420S14I-C X40421S14I-C
X40420V14-C X40421V14-C
14L TSSOP
14L SOIC
4.6V±50mV
2.9V±50mV
2.6V±50mV
1.6V±50mV
14L TSSOP
14L SOIC
-40oC - 85oC
0oC - 70oC
14L TSSOP
-40oC - 85oC
X40420V14I-C X40421V14I-C
PART MARK INFORMATION
14-Lead SOIC
0/1
X4042XX
YYWWXX
Package - S/V
A, B, or C
I – Industrial
Blank – Commercial
WW – Workweek
YY – Year
LIMITED WARRANTY
©Xicor, Inc. 2001 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS ANDTRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 25 of 25
REV 1.2.14 7/12/02
www.xicor.com
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