X40431V14I-A [XICOR]
4kbit EEPROM, Triple Voltage Monitor with Integrated CPU Supervisor; 4k位EEPROM ，三重电压监控器，集成了CPU监控
| 型号： | X40431V14I-A |
| 厂家： | 
XICOR INC. |
| 描述： | 4kbit EEPROM, Triple Voltage Monitor with Integrated CPU Supervisor |
| 文件： | 总24页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
4kbit EEPROM
X40430/X40431
Triple Voltage Monitor with Integrated CPU Supervisor
FEATURES
DESCRIPTION
• Triple voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V/1.7V, 4.4V/2.6V/1.7V,
2.9V/1.7V/2.4V)
—Adjust low voltage reset threshold voltages
using special programming sequence
The X40430/31 combines power-on reset control,
watchdog timer, supply voltage supervision, secondary
and third voltage supervision, manual reset, and Block
Lock™ protect serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
—Reset signal valid to V = 1V
—Monitor three voltages or detect power fail
• Fault detection register
• Selectable power on reset timeout
• Selectable watchdog timer interval
• Debounced manual reset input
• Low power CMOS
—30µA typical standby current, watchdog on
—10µA typical standby current, watchdog off
• 4Kbits of EEPROM
CC
Applying voltage to V
activates the power on reset
CC
circuit which holds RESET/RESET active for a period of
time.This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low V
detection circuitry protects the user’s system
CC
from low voltage conditions, resetting the system when
falls below the minimum V point. RESET/
V
CC
TRIP1
RESET is active until V
returns to proper operating
CC
level and stabilizes. A second and third voltage monitor
circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Xicor’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
—16 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0, 1/4, 1/2, all of EEPROM
• 400kHz I2C interface
• 2.4V to 5.5V power supply operation
• Available packages
—14-lead SOIC,TSSOP
BLOCK DIAGRAM
+
V3MON
V3FAIL
V2FAIL
V
TRIP3
-
V3 Monitor
Logic
+
V2MON
V
V2 Monitor
Logic
TRIP2
-
Watchdog
and
Fault Detection
Register
Data
WDO
MR
Reset Logic
SDA
WP
Register
Status
Register
Command
Decode Test
& Control
Logic
EEPROM
Array
SCL
RESET
Power on,
Manual Reset
Low Voltage
Reset
X40430
RESET
X40431
+
V
CC
V
-
TRIP1
Generation
(V1MON)
V
Monitor
CC
Logic
LOWLINE
Characteristics subject to change without notice. 1 of 24
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X40430/X40431 – Preliminary Information
A manual reset input provides debounce circuitry for
minimum reset component count.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock protection. The
array is internally organized as x 8. The device features
a 2-wire interface and software protocol allowing opera-
tion on an I2C bus.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.
The device utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
X40431
X40430
14-Pin SOIC, TSSOP
14-Pin SOIC, TSSOP
V
V2FAIL
V2MON
LOWLINE
NC
MR
RESET
V
V2FAIL
V2MON
1
2
3
4
14
13
12
11
1
2
3
4
14
13
12
11
CC
CC
WDO
V3FAIL
V3MON
WP
SCL
SDA
WDO
V3FAIL
V3MON
WP
SCL
SDA
LOWLINE
NC
MR
RESET
5
6
7
10
9
8
5
6
7
10
9
8
V
V
SS
SS
PIN DESCRIPTION
Pin
Name
Function
1
V2FAIL
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V
and
TRIP2
goes HIGH when V2MON exceeds V
. There is no power up reset delay circuitry on this pin.
TRIP2
2
V2MON
V2 Voltage Monitor Input. When the V2MON input is less than the V
voltage, V2FAIL goes
TRIP2
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V or V
SS
CC
when not used.
3
LOWLINE Early Low V Detect. This CMOS output signal goes LOW when V
< V and goes high
TRIP1
CC
> V
CC
when V
.
CC
TRIP1
4
5
NC
MR
No connect.
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the t thereafter.
PURST
6
RESET/
RESET
RESET Output. (X40431) This open drain pin is an active LOW output which goes LOW whenever
falls below V voltage or if manual reset is asserted. This output stays active for the pro-
V
CC
TRIP
grammed time period (t
) on power up. It will also stay active until manual reset is released
PURST
and for t
thereafter.
PURST
RESET Output. (X40430) This pin is an active HIGH CMOS output which goes HIGH whenever
falls below V voltage or if manual reset is asserted. This output stays active for the pro-
V
CC
TRIP
grammed time period (t
and for t
) on power up. It will also stay active until manual reset is released
PURST
thereafter.
PURST
7
V
Ground
SS
Characteristics subject to change without notice. 2 of 24
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X40430/X40431 – Preliminary Information
PIN DESCRIPTION (Continued)
Pin
Name
Function
8
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This pin
requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
9
SCL
WP
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10
Write Protect. WP HIGH prevents writes to any location in the device (including all the registers).
It has an internal pull down resistor.
11
V3MON
V3 Voltage Monitor Input. When the V3MON input is less than the V
voltage, V3FAIL goes
TRIP3
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a third power supply with no external components. Connect V3MON to V or V
when
SS
CC
not used.
12
13
14
V3FAIL
WDO
V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than V
and
TRIP3
goes HIGH when V3MON exceeds V
. There is no power up reset delay circuitry on this pin.
TRIP3
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
V
Supply Voltage
CC
PRINCIPLES OF OPERATION
Power On Reset
Figure 1. Connecting a Manual Reset Push-Button
V
CC
X40430
Applying power to the X40430/31 activates a Power
On Reset Circuit that pulls the RESET/RESET pins
active.This signal provides several benefits.
System
Reset
RESET
MR
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
Manual
Reset
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
Manual Reset
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains HIGH/LOW
until the push-button is released and for t
after.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When V
exceeds the device V
threshold value
CC
TRIP1
there-
PURST
for t
(selectable) the circuit releases the RESET
PURST
(X40431) and RESET (X40430) pin allowing the system
to begin operation.
Characteristics subject to change without notice. 3 of 24
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X40430/X40431 – Preliminary Information
Low Voltage V
(V1 Monitoring)
Figure 2. Two Uses of Multiple Voltage Monitoring
CC
During operation, the X40430 monitors the V
level
CC
and asserts RESET if supply voltage falls below a pre-
set minimum V . The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal
remains active until the voltage drops below 1V. It also
V2MON
TRIP1
X40430
5V
Unreg.
Supply
V
CC
System
Reset
Reg
RESET
V2MON
V2FAIL
remains active until V
returns and exceeds V
CC
TRIP1
R
for t
.
PURST
R
Low Voltage V2 Monitoring
The X40430 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
mum V
. The V2FAIL signal is either ORed with
TRIP2
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V2FAIL signal remains active
until the V2MON drops below 1V (V2MON falling). It
also remains active until V2MON returns and exceeds
V2MON
V
V3MON
CC
X40431
Unreg.
Supply
5V
V
Reg
CC
System
Reset
RESET
V2MON
4V
Reg
V
by 0.2V.
TRIP2
V2FAIL
3V
Reg
Low Voltage V3 Monitoring
V3MON
V3FAIL
The X40430 also monitors a third voltage level and
asserts V3FAIL if the voltage falls below a preset mini-
Notice: No external components required to monitor three voltages.
mum V
. The V3FAIL signal is either ORed with
TRIP3
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V3FAIL signal remains active
until the V3MON drops below 1V (V3MON falling). It
also remains active until V3MON returns and exceeds
V
by 0.2V.
TRIP3
Early Low V
Detection (LOWLINE)
CC
This CMOS output goes LOW earlier than RESET/
RESET whenever V falls below the V voltage
CC
TRIP1
and returns high when V
age. There is no power up delay circuitry (t
this pin.
exceeds the V
volt-
) on
CC
TRIP1
PURST
Characteristics subject to change without notice. 4 of 24
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X40430/X40431 – Preliminary Information
Figure 3. V
Set/Reset Conditions
TRIPX
V
(X = 1, 2, 3)
TRIPX
V
/V2MON/V3MON
CC
V
P
0
WDO
SCL
7
0
0
7
7
SDA
t
WC
A0h
00h
WATCHDOG TIMER
precision is needed in the threshold value, the X40430
trip points may be adjusted. The procedure is described
below, and uses the application of a high voltage control
signal.
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL also toggles from HIGH to LOW
(this is a start bit) followed by a stop condition prior to
the expiration of the watchdog time out period to pre-
vent a WDO signal going active. The state of two non-
volatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits by writing to the X40430/
31 control register (also refer to page 20).
Setting a V
Voltage (x=1, 2, 3)
TRIPx
There are two procedures used to set the threshold
voltages (V ), depending if the threshold voltage to
TRIPx
be stored is higher or lower than the present value. For
example, if the present V is 2.9 V and the new
TRIPx
V
is 3.2 V, the new voltage can be stored directly
TRIPx
into the V
cell. If however, the new setting is to be
TRIPx
lower than the present setting, then it is necessary to
“reset” the V voltage before setting the new value.
TRIPx
Figure 4. Watchdog Restart
.6µs
Setting a Higher V
Voltage (x=1, 2, 3)
1.3µs
TRIPx
SCL
To set a V
threshold to a new voltage which is
TRIPx
higher than the present threshold, the user must apply
the desired V threshold voltage to the corre-
TRIPx
SDA
sponding input pin (Vcc(V1MON), V2MON or V3MON).
The Vcc(V1MON), V2MON and V3MON must be tied
together during this sequence. Then, a programming
voltage (Vp) must be applied to the WDO pin before a
START condition is set up on SDA. Next, issue on the
SDA pin the Slave Address A0h, followed by the Byte
Timer Start
V1, V2 AND V3 THRESHOLD PROGRAM
PROCEDURE
Address 01h for V
, 09h for V
, and 0Dh for
TRIP1
TRIP2
The X40430 is shipped with standard V1, V2 and V3
V
V
, and a 00h Data Byte in order to program
. The STOP bit following a valid write operation
TRIP3
TRIPx
threshold (V
V
V
) voltages. These
TRIP1, TRIP2, TRIP3
values will not change over normal operating and stor-
age conditions. However, in applications where the
standard thresholds are not exactly right, or if higher
initiates the programming sequence. Pin WDO must
then be brought LOW to complete the operation
Characteristics subject to change without notice. 5 of 24
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X40430/X40431 – Preliminary Information
Note: This operation does not corrupt the memory
The Control Register is accessed with a special pre-
array.
amble in the slave byte (1011) and is located at
address 1FFh. It can only be modified by performing a
byte write operation directly to the address of the regis-
ter and only one data byte is allowed for each register
write operation. Prior to writing to the Control Register,
the WEL and RWEL bits must be set using a two step
process, with the whole sequence requiring 3 steps.
See "Writing to the Control Registers" on page 7.
Setting a Lower V
Voltage (x=1, 2, 3)
TRIPx
In order to set V
present value, then V
ing to the procedure described below. Once V
has been “reset”, then V
voltage using the procedure described in “Setting a
Higher V Voltage”.
to a lower voltage than the
TRIPx
must first be “reset” accord-
TRIPx
TRIPx
can be set to the desired
TRIPx
TRIPx
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, BP1, and BP0. The X40430
will not acknowledge any data bytes written after the
first byte is entered.
Resetting the V
Voltage
TRIPx
To reset a V
voltage, apply the programming volt-
TRIPx
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
The state of the Control Register can be read at any
time by performing a random read at address 1FFh,
using the special preamble. Only one byte is read by
each register read operation. The master should
supply a stop condition to be consistent with the bus
protocol.
V
, 0Bh for V
, and 0Fh for V
, followed
TRIP1
TRIP2
TRIP3
by 00h for the Data Byte in order to reset V
. The
TRIPx
STOP bit following a valid write operation initiates the
programming sequence. Pin WDO must then be
brought LOW to complete the operation.
7
6
5
4
3
2
1
0
After being reset, the value of V
nal value of 1.7V or lesser.
becomes a nomi-
TRIPx
PUP1 WD1 WD0 BP1 BP0 RWEL WEL PUP0
Note: This operation does not corrupt the memory
array.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Control Register
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
Figure 5. Sample V
Reset Circuit
TRIP
V
P
Adjust
Run
V2FAIL
µC
1
6
2
7
14
13
9
RESET
X40430
V
TRIP1
8
Adj.
SCL
SDA
V
TRIP2
Adj.
Characteristics subject to change without notice. 6 of 24
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X40430/X40431 – Preliminary Information
Figure 6. V
Set/Reset Sequence (X = 1, 2, 3)
TRIP
V
Programming
TRIPX
Desired
TRIPX
No
V
Present Value
YES
Execute
V
Reset Sequence
TRIP
Execute
Set Higher V
Sequence
TRIP
New V applied =
Execute
New V applied =
X
X
Set Higher V Sequence
Old V applied - Error
Old V applied + Error
X
X
X
Apply V and Voltage
CC
Execute Reset V
TRIPX
Sequence
Desired V
to
V
TRIPX
X
NO
Decrease
V
X
Output Switches?
YES
Error < -MDE
V
Error > +MDE
Actual
TRIPX –
V
Desired
TRIPX
Error < | MDE |
DONE
Vx = V , V2MON, V3MON
CC
Note: X = 1, 2, 3
Let: MDE = Maximum Desired Error
WEL: Write Enable Latch (Volatile)
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeroes to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register.
Characteristics subject to change without notice. 7 of 24
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X40430/X40431 – Preliminary Information
BP1, BP0: Block Protect Bits (Nonvolatile)
– Write one byte value to the Control Register that has
all the control bits set to the desired state. The Con-
trol register can be represented as qxys t01r in
binary, where xy are the WD bits, and st are the BP
bits and qr are the power up bits. This operation pro-
ceeded by a start and ended with a stop bit. Since
this is a nonvolatile write cycle it will take up to 10ms
(max.) to complete. The RWEL bit is reset by this
cycle and the sequence must be repeated to change
the nonvolatile bits again. If bit 2 is set to ‘1’ in this
third step (qxys t11r) then the RWEL bit is set, but
the WD1, WD0, PUP1, PUP0, BP1 and BP0 bits
remain unchanged. Writing a second byte to the con-
trol register is not allowed. Doing so aborts the write
operation and returns a NACK.
The Block Protect Bits, BP1 and BP0, determine which
blocks of the array are write protected. A write to a pro-
tected block of memory is ignored. The block protect
bits will prevent write operations to one of eight seg-
ments of the array.
Protected Addresses
(Size)
Array Lock
None
0
0
1
1
0
1
0
1
None
180h – 1FFh (128 bytes)
Upper 1/4 (Q4)
100h – 1FFh (256 bytes) Upper 1/2 (Q3,Q4)
000h – 1FFh (512 bytes) Full Array (All)
PUP1, PUP0: Power Up Bits (Nonvolatile)
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
The Power Up bits, PUP1 and PUP0, determine the
t
time delay. The nominal power up times are
PURST
shown in the following table.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
PUP1 PUP0 Power on Reset Delay (t
)
PURST
0
0
1
1
0
1
0
1
50ms
200ms
400ms
800ms
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile
bits in the Control Register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the
Watchdog Timer.The options are shown below.
Fault Detection Register (FDR)
The Fault Detection Register provides the user the
status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and Three
Low Voltage Fail bits are volatile
WD1
WD0
Watchdog Time Out Period
1.4 seconds
0
0
1
1
0
1
0
1
200 milliseconds
25 milliseconds
disabled
7
6
5
4
3
2
1
0
LV1F LV2F LV3F WDF MRF
0
0
0
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a start and ended with a stop).
There is no need to set the WEL or RWEL in the
control register to access this FDR.
– Write a 06H to the Control Register to set the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
Characteristics subject to change without notice. 8 of 24
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X40430/X40431 – Preliminary Information
Figure 7. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
At power-up, the FDR is defaulted to all “0”. The sys-
tem needs to initialize this register to all “1” before the
actual monitoring can take place. In the event of any
one of the monitored sources fail. The corresponding
bit in the register will change from a “1” to a “0” to indi-
cate the failure. At this moment, the system should per-
form a read to the register and note the cause of the
reset. After reading the register the system should
reset the register back to all “1” again. The state of the
FDR can be read at any time by performing a random
read at address 0FFh, using the special preamble.
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family
operate as slaves in all applications.
Serial Clock and Data
The FDR can be read by performing a random read at
0FFh address of the register at any time. Only one byte
of data is read by the register read operation.
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 7.
MRF, Manual Reset Fail Bit (Volatile)
The MRF bit will be set to “0” when Manual Reset input
goes active.
Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 8.
WDF, Watchdog Timer Fail Bit (Volatile)
The WDF bit will be set to “0” when the WDO goes
active.
LV1F, Low V
Reset Fail Bit (Volatile)
CC
The LV1F bit will be set to “0” when V
(V1MON) falls
CC
Serial Stop Condition
below V
.
TRIP1
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.
LV2F, Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls below
V
.
TRIP2
LV3F, Low V3MON Reset Fail Bit (Volatile)
The LV3F bit will be set to “0” when the V3MON falls
below V
.
TRIP3
Characteristics subject to change without notice. 9 of 24
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X40430/X40431 – Preliminary Information
Figure 8. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Acknowledge
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. See Figure 9.
Serial Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array.
After receipt of the Word Address Byte, the device
responds with an acknowledge, and awaits the next
eight bits of data. After receiving the 8 bits of the Data
Byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating
a stop condition, at which time the device begins the
internal write cycle to the nonvolatile memory. During
this internal write cycle, the device inputs are disabled, so
the device will not respond to any requests from the mas-
ter.The SDA output is at high impedance. See Figure 10.
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
A write to a protected block of memory will suppress
the acknowledge bit.
Figure 9. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
Characteristics subject to change without notice. 10 of 24
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X40430/X40431 – Preliminary Information
Figure 10. Byte Write Sequence
S
t
a
r
t
S
t
o
p
Signals from
the Master
Byte
Address
Slave
Address
Data
SDA Bus
0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Page Write
This means that the master can write 16 bytes to the
page starting at any location on that page. If the mas-
ter begins writing at location 10, and loads 12 bytes,
then the first 6 bytes are written to locations 10 through
15, and the last 6 bytes are written to locations 0
through 5. Afterwards, the address counter would point
to location 6 of the page that was just written. If the
master supplies more than 16 bytes of data, then new
data overwrites the previous data, one byte at a time.
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page.
Figure 11. Page Write Operation
(1 ≤ n ≤ 16)
S
S
t
o
p
t
a
r
Signals from
the Master
Byte
Address
Slave
Address
Data
(1)
Data
(n)
t
SDA Bus
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.
7 Bytes
5 Bytes
address pointer
ends here
Addr = 7
address
10
address
= 6
address
n-1
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 11 for the address, acknowl-
edge, and data transfer sequence.
Characteristics subject to change without notice. 11 of 24
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X40430/X40431 – Preliminary Information
Stops and Write Modes
Figure 13. Acknowledge Polling Sequence
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full data
byte plus its associated ACK is sent, then the device
will reset itself without performing the write. The con-
tents of the array will not be effected.
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Acknowledge Polling
Issue Slave Address
Byte (Read or Write)
Issue STOP
The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
device initiates the internal high voltage cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
See Figure 13.
NO
ACK
Returned?
YES
High Voltage Cycle
Complete. Continue
Command Sequence?
Issue STOP
NO
YES
Continue Normal
Read or Write
Serial Read Operations
Command Sequence
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
PROCEED
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master
issues the start condition and the Slave Address Byte,
receives an acknowledge, then issues the Word Address
Bytes. After acknowledging receipts of the Word Address
Bytes, the master immediately issues another start condi-
tion and the Slave Address Byte with the R/W bit set to
one. This is followed by an acknowledge from the device
and then by the eight bit word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. See Figure 15 for the
address, acknowledge, and data transfer sequence.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The mas-
ter terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. See Figure 14 for the
address, acknowledge, and data transfer sequence.
Characteristics subject to change without notice. 12 of 24
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X40430/X40431 – Preliminary Information
A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 14. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter “rolls
over” to address 0000h and the device continues to out-
put data for each acknowledge received. See Figure 16
for the acknowledge and data transfer sequence.
SERIAL DEVICE ADDRESSING
Slave Address Byte
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
Following a start condition, the master must output a
Slave Address Byte.This byte consists of several parts:
– a device type identifier that is always ‘1010’.
– two bits that provide the device select bits.
– one bit that becomes the MSB of the address.
Figure 14. Current Address Read Sequence
.
S
Slave
Address
t
a
r
S
t
o
p
Signals from
the Master
t
SDA Bus
1
A
Signals from
the Slave
C
Data
K
Figure 15. Random Address Read Sequence
S
S
S
t
a
r
Slave
Address
Byte
Address
Slave
Address
t
a
r
Signals from
the Master
t
o
p
t
t
SDA Bus
0
1
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
– one bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the opera-
tion to be performed.When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation.
– After loading the entire Slave Address Byte from the
SDA bus, the device compares the device select bits
with the status of the Device Select pins. Upon a cor-
rect compare, the device outputs an acknowledge on
the SDA line.
Characteristics subject to change without notice. 13 of 24
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X40430/X40431 – Preliminary Information
Word Address
Data Protection
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
– SDA pin is the input mode.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
– RESET/RESET Signal is active for t
.
PURST
Figure 16. Sequential Read Sequence
S
t
Slave
Address
Signals from
the Master
o
A
C
K
A
C
K
A
C
K
p
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
Characteristics subject to change without notice. 14 of 24
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X40430/X40431 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... –65°C to +135°C
Storage temperature ........................ –65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
respect to V ......................................–1.0V to +7V
SS
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Version
-A or -B
-C
Supply Voltage Limits
2.7V to 5.5V
–40°C
+85°C
2.4V to 3.6V
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)
Symbol
Parameter
Active Supply Current (V ) Read
Min.
Typ.(4)
Max.
1.5
Unit
Test Conditions
(1)
I
I
mA
mA
V
V
= V x 0.1
CC
CC1
CC2
CC
IL
IH
(1)
= V
x 0.9,
CC
Active Supply Current (V ) Write
3.0
CC
f
= 400kHz
SCL
(1)
I
Standby Current (V ) AC (WDT off)
10
30
30
µA
V
= V x 0.1
CC
SB1
CC
IL
VIH = V
x 0.9
CC
f
, f
= 400kHz
SCL SDA
(2)
I
Standby Current (V ) DC (WDT on)
CC
50
10
10
µA
µA
µA
V
= V
= V
SB2
SDA
SCL CC
Others = GND or V
CC
I
Input Leakage Current (SCL, MR,
WP)
V
= GND to V
CC
LI
IL
I
Output Leakage Current (SDA,
V2FAIL, V3FAIL, WDO, RESET)
V
= GND to V
SDA
CC
LO
Device is in Standby(2)
(3)
V
Input LOW Voltage (SDA, SCL, MR,
WP)
-0.5
V
x 0.3
V
V
IL
CC
(3)
V
Input HIGH Voltage (SDA, SCL, MR,
WP)
V
x 0.7
CC
V
+ 0.5
IH
CC
V
Schmitt Trigger Input Hysteresis
• Fixed input level
HYS
0.2
.05 x V
V
V
• V
related level
CC
CC
V
Output LOW Voltage (SDA, RESET/
RESET, LOWLINE, V2FAIL,
V3FAIL, WDO)
0.4
V
I
I
= 3.0mA (2.7-5.5V)
= 1.8mA (2.4-3.6V)
OL
OL
OL
V
Output (RESET, LOWLINE) HIGH
Voltage
V
V
– 0.8
– 0.4
V
I
I
= -1.0mA (2.7-5.5V)
= -0.4mA (2.4-3.6V)
OH
CC
CC
OH
OH
V
Supply
CC
V
V
Trip Point Voltage
CC
2.0
4.75
60
V
TRIP1
V
Low V
RESET Hysteresis
CC
mV
LVRH
Characteristics subject to change without notice. 15 of 24
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X40430/X40431 – Preliminary Information
D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)
Symbol
Parameter
Min.
Typ.(4)
Max.
Unit
Test Conditions
Second Supply Monitor
I
V2MON Current
15
4.75
60
µA
V
V2
V
V2MON Trip Point Voltage
V2MON Hysteresis
1.7
TRIP2
V
mV
V2H
Third Supply Monitor
I
V3MON Current
15
4.75
60
µA
V
V3
V
V3MON Trip Point Voltage
V3MON Hysteresis
1.7
TRIP3
V
mV
V3H
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or t after a stop ending a write operation.
WC
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; t
after a stop that ini-
WC
tiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address
Byte.
(3) V Min. and V Max. are for reference only and are not tested.
IL
IH
(4) At 25°C, V = 3V
CC
CAPACITANCE
Symbol
Parameter
Max.
Unit
Test Conditions
= 0V
(1)
C
Output Capacitance (SDA, RESET/RESET, LOWLINE,
V2FAIL,V3FAIL, WDO)
8
pF
V
OUT
OUT
(1)
C
Input Capacitance (SCL, WP, MR)
6
pF
V
= 0V
IN
IN
Note: (1) This parameter is not 100% tested.
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
SYMBOL TABLE
V
= 5V
CC
WAVEFORM
INPUTS
OUTPUTS
V
5V
V2MON, V3MON
CC
Must be
steady
Will be
steady
4.6KΩ
4.6KΩ
2.06KΩ
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
RESET
WDO
V2FAIL,
V3FAIL
SDA
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
30pF
30pF
30pF
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
A.C. TEST CONDITIONS)
N/A
Center Line
is High
Impedance
Input pulse levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
Input rise and fall times
10ns
Input and output timing levels
Output load
V
CC
Standard output load
Characteristics subject to change without notice. 16 of 24
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X40430/X40431 – Preliminary Information
A.C. CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
pF
f
SCL Clock Frequency
0
400
SCL
t
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
50
IN
t
0.1
0.9
AA
t
1.3
BUF
t
1.3
LOW
t
Clock HIGH Time
0.6
HIGH
t
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
t
t
0.6
100
t
t
Data In Hold Time
0
Stop Condition Setup Time
Data Output Hold Time
0.6
t
50
20 +.1Cb(1)
20 +.1Cb(1)
0.6
DH
t
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
300
300
R
t
F
t
SU:WP
t
WP Hold Time
0
HD:WP
Cb
Capacitive load for each bus line
400
Note: (1) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
t
t
t
t
R
F
HIGH
LOW
SCL
SDA IN
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
t
t
DH
t
AA
BUF
SDA OUT
Characteristics subject to change without notice. 17 of 24
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X40430/X40431 – Preliminary Information
WP Pin Timing
START
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
WP
t
t
HD:WP
SU:WP
Write Cycle Timing
SCL
8th Bit of Last Byte
ACK
SDA
t
WC
Stop
Start
Condition
Condition
Nonvolatile Write Cycle Timing
Symbol
Parameter
Write Cycle Time
Min.
Typ.
Max.
10
Unit
(1)
t
5
ms
WC
Note: (1) t
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
WC
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Power Fail Timings
V
TRIPX
t
t
RPDL
RPDL
V
CC
t
RPDX
t
V2MON or
V3MON
RPDX
t
t
RPDL
RPDX
t
F
LOWLINE or
V2FAIL or
t
R
V
RVALID
V3FAIL
X = 2, 3
Characteristics subject to change without notice. 18 of 24
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X40430/X40431 – Preliminary Information
RESET/RESET/MR Timings
V
TRIP1
V
CC
t
t
PURST
PURST
t
RPD1
t
F
t
R
RESET
V
RVALID
RESET
MR
t
MD
t
IN1
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS
Symbol
Parameters
Min.
Typ.
Max.
Unit
t
t
V
V
to RESET/RESET (Power down only)
to LOWLINE
10
20
µs
RPD1
RPDL
TRIP1
TRIP1
t
LOWLINE to RESET/RESET delay (Power down only) [= t
-t ]
500
10
ns
µs
LR
RPD1 RPDL
t
V
to V2FAIL, or V to V3FAIL
TRIP3
20
RPDX
TRIP2
t
Power On Reset delay:
PUP1=0, PUP0=0
PUP1=0, PUP0=1
PUP1=1, PUP0=0
PUP1=1, PUP0=1
PURST
50
ms
ms
ms
ms
200
400
800
t
V
V
V2MON V3MON Fall Time
20
20
1
mV/µs
mV/µs
V
F
CC,
,
,
t
V2MON V3MON Rise Time
, ,
R
CC,
V
Reset Valid V
CC
RVALID
t
MR to RESET/ RESET delay (activation only)
Pulse width for MR
500
5
ns
MD
t
µs
in1
t
Watchdog Timer Period:
WD1=0, WD0=0
WDO
1.4
200
25
s
ms
ms
WD1=0, WD0=1
WD1=1, WD0=0
t
t
Watchdog Reset Time Out Delay
WD1=0, WD0=0
WD1=0, WD0=1
100
200
300
ms
RST1
Watchdog Reset Time Out Delay WD1=1, WD0=0
Watchdog timer restart pulse width
12.5
1
25
37.5
ms
µs
RST2
t
RSP
Characteristics subject to change without notice. 19 of 24
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X40430/X40431 – Preliminary Information
Watchdog Time Out For 2-Wire Interface
Start
Start
t
RSP
< t
WDO
SCL
Timer Start
SDA
t
t
WDO
t
RST
RST
WDO
Timer
Restart
Timer Start
V
Set/Reset Conditions
TRIPX
(V
)
V
/V2MON/V3MON
CC
TRIPX
t
THD
V
t
P
TSU
WDO
t
VPS
t
VPO
t
VPH
7
SCL
SDA
0
0
7
0
7
t
WC
A0h
00h
Start
resets V
01h*
09h*
0Dh*
03h*
0Bh*
0Fh*
sets V
sets V
sets V
TRIP1
TRIP1
resets V
resets V
TRIP2
TRIP3
TRIP2
TRIP3
* all others reserved
Characteristics subject to change without notice. 20 of 24
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X40430/X40431 – Preliminary Information
V
, V
, V
Programming Specifications: V
= 2.0–5.5V; Temperature = 25°C
TRIP1 TRIP2 TRIP3
CC
Parameter
Description
WDO Program Voltage Setup time
WDO Program Voltage Hold time
Min. Max. Unit
t
10
µs
µs
µs
µs
ms
ms
V
VPS
VPH
t
10
10
t
V
V
V
Level Setup time
Level Hold (stable) time
Program Cycle
TSU
THD
TRIPX
TRIPX
TRIPX
t
10
t
10
WC
t
Program Voltage Off time before next cycle
Programming Voltage
1
VPO
V
15
18
P
V
V
Set Voltage Range
2.0
-0.1
-25
-25
-25
10
4.75
+0.4
+25
+25
+25
V
TRAN
TRIPX
V
V
Initial V
Set Voltage accuracy (V
applied—V )
TRIPX
V
ta1
ta2
TRIPX
CC
Subsequent V
Program Voltage accuracy [(V
applied—V )–V )
TRIPX
mV
mV
mV
µs
TRIPX
CC
ta1
V
V
V
Set Voltage repeatability (Successive program operations.)
Set Voltage variation after programming (-40 to +85°C).
tr
tv
TRIPX
V
TRIPX
t
WDO Program Voltage Setup time
VPS
Characteristics subject to change without notice. 21 of 24
REV 1.2.3 11/28/00
www.xicor.com
X40430/X40431 – Preliminary Information
PACKAGING INFORMATION
14-Lead Plastic Small Outline Gullwing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"Typical
0° – 8°
0.250"
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
0.030"Typical
14 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 22 of 24
REV 1.2.3 11/28/00
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X40430/X40431 – Preliminary Information
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 23 of 24
REV 1.2.3 11/28/00
www.xicor.com
X40430/X40431 – Preliminary Information
ORDERING INFORMATION
Operating
V
V
V
V
TRIP3
Temperature Part Number
Part Number
with RESET
CC
Range
TRIP1
TRIP2
Range
Range
Range
Package
Range
with RESET
X40430S14-A
X40430S14I-A
X40430V14-A
X40430V14I-A
X40430S14-B
X40430S14I-B
X40430V14-B
X40430V14I-B
X40430S14-C
X40430S14I-C
X40430V14-C
X40430V14I-C
2.7-5.5 4.6V 50mV 2.9V 50mV 1.7V 50mV
2.7-5.5 4.4V 50mV 2.6V 50mV 1.7V 50mV
2.4-3.6 2.9V 50mV 1.7V 50mV 2.6V 50mV
14L SOIC
0oC–70oC
-40oC–85oC
0oC–70oC
-40oC–85oC
0oC–70oC
-40oC–85oC
0oC–70oC
-40oC–85oC
0oC–70oC
-40oC–85oC
0oC–70oC
-40oC–85oC
X40431S14-A
X40431S14I-A
X40431V14-A
X40431V14I-A
X40431S14-B
X40431S14I-B
X40431V14-B
X40431V14I-B
X40431S14-C
X40431S14I-C
X40431V14-C
X40431V14I-C
14L TSSOP
14L SOIC
14L TSSOP
14L SOIC
14L TSSOP
PART MARK INFORMATION
14-Lead SOIC
14-Lead TSSOP
EYWW
40430X
X40430SX
EYWW
A, B, or C
A, B, or C
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 24 of 24
REV 1.2.3 11/28/00
www.xicor.com
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