X4643V8_技术文档

64K

8K x 8 Bit

X4643/5

CPU Supervisor with 64K EEPROM

DESCRIPTION

FEATURES

• Selectable watchdog timer

The X4643/5 combines four popular functions, Power-on

Reset Control, Watchdog Timer, Supply Voltage

Supervision, and Serial EEPROM Memory in one

package. This combination lowers system cost,

reduces board space requirements, and increases reli-

ability.

• Low V

detection and reset assertion

CC

—Four standard reset threshold voltages

—Adjust low V reset threshold voltage using

CC

special programming sequence

—Reset signal valid to V = 1V

CC

• Low power CMOS

Applying power to the device activates the power on

reset circuit which holds RESET/RESET active for a

period of time. This allows the power supply and oscilla-

tor to stabilize before the processor can execute code.

—<20µA max standby current, watchdog on

—<1µA standby current, watchdog off

—3mA active current

• 64Kbits of EEPROM

—64-byte page write mode

—Self-timed write cycle

—5ms write cycle time (typical)

• Built-in inadvertent write protection

—Power-up/power-down protection circuitry

• 400kHz 2-wire interface

• 2.7V to 5.5V power supply operation

• Available packages

—8-lead SOIC

The Watchdog Timer provides an independent protection

mechanism for microcontrollers. When the microcon-

troller fails to restart a timer within a selectable time out

interval, the device activates the RESET/RESET signal.

The user selects the interval from three preset values.

Once selected, the interval does not change, even after

cycling the power.

The device’s low V

detection circuitry protects the

CC

user’s system from low voltage conditions, resetting the

system when V falls below the set minimum V trip

—8-lead TSSOP

CC

point. RESET/RESET is asserted until V

returns to

CC

proper operating level and stabilizes. Four industry

BLOCK DIAGRAM

Watchdog Transition

Detector

Watchdog

Timer Reset

WP

Protect Logic

RESET (X4643/5)

RESET (X4645)

Data

Register

SDA

Status

Register

EEPROM Array

Command

Reset &

Watchdog

Timebase

SCL

Decode &

Control

Logic

S0

S1

V

Threshold

CC

Reset Logic

Power on and

Low Voltage

Reset

+

-

V

CC

V

TRIP

Generation

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X4643/5

standard V

thresholds are available, however,

PIN CONFIGURATION

TRIP

Xicor’s unique circuits allow the threshold to be

reprogrammed to meet custom requirements or to ﬁne-

tune the threshold for applications requiring higher

precision.

8-Pin JEDEC SOIC

V

1

2

3

4

8

7

6

5

S

0

CC

S

1

WP

SCL

RESET/RESET

V

SDA

SS

8 Pin TSSOP

SCL

SDA

1

2

3

4

8

7

6

5

WP

V

CC

V

S

0

SS

S

RESET/RESET

1

PIN FUNCTION

(SOIC) (TSSOP)

Name

Function

1

2

3

4

5

S

Device Select Input

0

1

RESET/

RESET

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which

goes active whenever V_CCfalls below the minimum V sense level. It will remain

CC

active until V rises above the minimum V sense level for 250ms. RESET/

CC

RESET goes active if the Watchdog Timer is enabled and SDA remains either

HIGH or LOW longer than the selectable Watchdog time out period. A falling edge

on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes

active on power up and remains active for 250ms after the power supply stabilizes.

4

5

6

7

V

Ground

SS

SDA

Serial Data. SDA is a bidirectional pin used to transfer data into and out of the de-

vice. It has an open drain output and may be wire ORed with other open drain or

open collector outputs. This pin requires a pull up resistor and the input buffer is

always active (not gated).

Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts

the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog

time out period results in RESET/RESET going active.

6

7

8

1

SCL

WP

Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the

control register.

8

2

V

Supply Voltage

CC

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X4643/5

PRINCIPLES OF OPERATION

Power On Reset

periodically, while SCL is HIGH (this is a start bit) prior

to the expiration of the watchdog time out period to

prevent a RESET/RESET signal. The state of two non-

volatile control bits in the Status Register determine

the watchdog timer period. The microprocessor can

change these watchdog bits, or they may be “locked”

by tying the WP pin HIGH.

Application of power to the X4643/5 activates a Power

On Reset Circuit that pulls the RESET/RESET pin

active.This signal provides several beneﬁts.

– It prevents the system microprocessor from starting

to operate with insufﬁcient voltage.

EEPROM INADVERTENT WRITE PROTECTION

– It prevents the processor from operating prior to sta-

bilization of the oscillator.

When RESET/RESET goes active as a result of a low

voltage condition or Watchdog Timer Time Out, any in-

progress communications are terminated. While

RESET/RESET is active, no new communications are

allowed and no nonvolatile write operation can start.

Nonvolatile writes in-progress when RESET/RESET

goes active are allowed to ﬁnish.

– It allows time for an FPGA to download its conﬁgura-

tion prior to initialization of the circuit.

– It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power up.

When V

exceeds the device V

threshold value

CC

TRIP

Additional protection mechanisms are provided with

memory Block Lock and the Write Protect (WP) pin.

These are discussed elsewhere in this document.

for 200ms (nominal) the circuit releases RESET/

RESET allowing the system to begin operation.

LOW VOLTAGE MONITORING

V

THRESHOLD RESET PROCEDURE

CC

During operation, the X4643/5 monitors the V

level

CC

The X4643/5 is shipped with a standard V

(V

operating and storage conditions. However, in applica-

tions where the standard V is not exactly right, or if

higher precision is needed in the V

threshold

and asserts RESET/RESET if supply voltage falls

below a preset minimum V . The RESET/RESET

CC

) voltage. This value will not change over normal

TRIP

signal prevents the microprocessor from operating in a

power fail or brownout condition. The RESET/RESET

signal remains active until the voltage drops below 1V.

TRIP

value, the

TRIP

X4643/5 threshold may be adjusted. The procedure is

described below, and uses the application of a nonvol-

atile control signal.

It also remains active until V

returns and exceeds

CC

V

for 200ms.

TRIP

WATCHDOG TIMER

The Watchdog Timer circuit monitors the microprocessor

activity by monitoring the SDA and SCL pins. The

microprocessor must toggle the SDA pin HIGH to LOW

Figure 1. Set V

Level Sequence (V = desired V

values WEL bit set)

TRIP

CC

TRIP

V

= 12-15V

P

WP

0 1 2 3 4 5 6 7

SCL

SDA

A0h

00h

01h

00h

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X4643/5

Setting the V

Voltage

Resetting the V

Voltage

TRIP

This procedure is used to set the V

to a higher or

This procedure is used to set the V

to a “native”

TRIP

lower voltage value. It is necessary to reset the trip

point before setting the new value.

voltage level. For example, if the current V

is 4.4V

TRIP

and the new V

must be 4.0V, then the V

must

TRIP

be reset. When V

thing less than 1.7V. This procedure must be used to

set the voltage to a lower value.

is reset, the new V

is some-

TRIP

To set the new V

bit in the control register, then apply the desired V

threshold voltage to the V

voltage, start by setting the WEL

TRIP

pin and the programming

CC

voltage, V , to the WP pin and 2 byte address and 1

To reset the new V

voltage start by setting the

P

TRIP

byte of “00” data. The stop bit following a valid write

WEL bit in the control register, apply V

and the pro-

CC

operation initiates the V

programming sequence.

gramming voltage, V , to the WP pin and 2 byte

TRIP

P

Bring WP LOW to complete the operation.

address and 1 byte of “00” data. The stop bit of a valid

write operation initiates the V

programming

TRIP

sequence. Bring WP LOW to complete the operation.

Figure 2. Reset V

Level Sequence (V

> 3V. WP = 12-15V, WEL bit set)

TRIP

CC

V

= 12-15V

P

WP

0 1 2 3 4 5 6 7

SCL

SDA

A0h

00h

03h

00h

Figure 3. Sample V

Reset Circuit

TRIP

V

P

SOIC

Adjust

4.7K

µC

1

2

3

4

8

7

6

5

RESET

Run

X4643

V

TRIP

Adj.

SCL

SDA

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X4643/5

Figure 4. V

Programming Sequence

TRIP

V

Programming

Execute

TRIP

Reset V

Sequence

TRIP

Set V

= V

Desired V

Applied =

TRIP

CC

New V

Applied =

Applied + Error

New V

Applied =

CC

Applied - Error

Execute

CC

Set V

TRIP

Old V

CC

Sequence

Execute

Apply 5V to V

CC

Reset V

TRIP

Sequence

Decrement V

(V

= V

- 50mV)

CC

NO

RESET pin

goes active?

YES

Error ≤ –Emax

Error ≥ Emax

Measured V

Desired V

-

TRIP

–Emax < Error < Emax

DONE

Emax = Maximum Allowed V

Error

TRIP

Control Register

RWEL bits must be set using a two step process, with

the whole sequence requiring 3 steps. See "Writing to

the Control Register" below.

The Control Register provides the user a mechanism

for changing the Block Lock and Watchdog Timer set-

tings. The Block Lock and Watchdog Timer bits are

nonvolatile and do not change when power is removed.

The user must issue a stop after sending this byte to the

register to initiate the nonvolatile cycle that stores WD1,

and WD0. The X4643/5 will not acknowledge any data

bytes written after the ﬁrst byte is entered.

The Control Register is accessed at address FFFFh. It

can only be modiﬁed by performing a byte write opera-

tion directly to the address of the register and only one

data byte is allowed for each register write operation.

Prior to writing to the Control Register, the WEL and

The state of the Control Register can be read at any

time by performing a random read at address FFFFh.

Only one byte is read by each register read operation.

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X4643/5

The X4643/5 resets itself after the ﬁrst byte is read.

The master should supply a stop condition to be con-

sistent with the bus protocol, but a stop is not required

to end this operation.

zeroes to the other bits of the control register. Once

set, WEL remains set until either it is reset to 0 (by writ-

ing a “0” to the WEL bit and zeroes to the other bits of

the control register) or until the part powers up again.

Writes to the WEL bit do not cause a nonvolatile write

cycle, so the device is ready for the next operation

immediately after the stop condition.

7

6

5

4

3

2

1

0

WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2

WD1, WD0: Watchdog Timer Bits

BP2, BP1, BP0: Block Protect Bits (Nonvolatile)

The bits WD1 and WD0 control the period of the

Watchdog Timer.The options are shown below.

The Block Protect Bits, BP2, BP1 and BP0, determine

which blocks of the array are write protected. A write to

a protected block of memory is ignored. The block pro-

tect bits will prevent write operations to the following

segments of the array.

WD1

WD0

Watchdog Time Out Period

1.4 seconds

0

1

0

1

0

1

600 milliseconds

Protected Addresses

200 milliseconds

(Size)

Array Lock

None

disabled (factory setting)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

None (factory setting)

None

Write Protect Enable

None

These devices have an advanced block lock scheme that

protects one of ﬁve blocks of the array when enabled. It

provides hardware write protection through the use of a

WP pin and a nonvolatile Write Protect Enable (WPEN)

bit.

0000h - 1FFFh (8K bytes)

000h - 03Fh (64 bytes)

000h - 07Fh (128 bytes)

000h - 0FFh (256 bytes)

000h - 1FFh (512 bytes)

Full Array (All)

First Page (P1)

First 2 pgs (P2)

First 4 pgs (P4)

First 8 pgs (P8)

The Write Protect (WP) pin and the Write Protect

Enable (WPEN) bit in the Control Register control the

programmable Hardware Write Protect feature. Hard-

ware Write Protection is enabled when the WP pin and

the WPEN bit are HIGH and disabled when either the

WP pin or the WPEN bit is LOW. When the chip is Hard-

ware Write Protected, nonvolatile writes to the block pro-

tected sections in the memory array cannot be written

and the block protect bits cannot be changed. Only the

sections of the memory array that are not block pro-

tected can be written. Note that since the WPEN bit is

write protected, it cannot be changed back to a LOW

state; so write protection is enabled as long as the WP

pin is held HIGH.

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit must be set to “1” prior to a write to the

Control Register.

WEL: Write Enable Latch (Volatile)

The WEL bit controls the access to the memory and to

the Register during a write operation. This bit is a vola-

tile latch that powers up in the LOW (disabled) state.

While the WEL bit is LOW, writes to any address,

including any control registers will be ignored (no

acknowledge will be issued after the Data Byte). The

WEL bit is set by writing a “1” to the WEL bit and

Table 1. Write Protect Enable Bit and WP Pin Function

Memory Array not

Block Protected

Memory Array

Block Protect

Bits

WP

WPEN

Block Protected

Writes Blocked

WPEN Bit

Writes OK

Protection

Software

LOW

HIGH

X

0

1

Writes OK

Software

Writes Blocked Writes Blocked

Hardware

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X4643/5

Writing to the Control Register

– The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power

cycling the device or attempting a write to a write

protected block.

Changing any of the nonvolatile bits of the control reg-

ister requires the following steps:

– Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so

there is no delay after the write. (Operation pre-

ceeded by a start and ended with a stop).

To illustrate, a sequence of writes to the device consist-

ing of [02H, 06H, 02H] will reset all of the nonvolatile

bits in the Control Register to 0. A sequence of [02H,

06H, 06H] will leave the nonvolatile bits unchanged

and the RWEL bit remains set.

– Write a 06H to the Control Register to set both the

Register Write Enable Latch (RWEL) and the WEL

bit. This is also a volatile cycle. The zeros in the data

byte are required. (Operation preceeded by a start

and ended with a stop).

SERIAL INTERFACE

Serial Interface Conventions

– Write a value to the Control Register that has all the

control bits set to the desired state. This can be rep-

resented as 0xys t01r in binary, where xy are the WD

bits, and rst are the BP bits. (Operation preceeded

by a start and ended with a stop). Since this is a non-

volatile write cycle it will take up to 10ms to com-

plete. The RWEL bit is reset by this cycle and the

sequence must be repeated to change the nonvola-

tile bits again. If bit 2 is set to ‘1’ in this third step

(0xys t11r) then the RWEL bit is set, but the WD1,

WD0, BP2, BP1 and BP0 bits remain unchanged.

Writing a second byte to the control register is not

allowed. Doing so aborts the write operation and

returns a NACK.

The device supports a bidirectional bus oriented proto-

col. The protocol deﬁnes any device that sends data

onto the bus as a transmitter, and the receiving device

as the receiver. The device controlling the transfer is

called the master and the device being controlled is

called the slave. The master always initiates data

transfers, and provides the clock for both transmit and

receive operations. Therefore, the devices in this family

operate as slaves in all applications.

Serial Clock and Data

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions. See

Figure 5.

– A read operation occurring between any of the previ-

ous operations will not interrupt the register write

operation.

Figure 5. Valid Data Changes on the SDA Bus

SCL

SDA

Data Stable

Data Change

Data Stable

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X4643/5

Serial Start Condition

Serial Stop Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL is

HIGH. The device continuously monitors the SDA and

SCL lines for the start condition and will not respond to

any command until this condition has been met. See

Figure 6.

All communications must be terminated by a stop condi-

tion, which is a LOW to HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the device into the Standby power mode after a read

sequence. A stop condition can only be issued after the

transmitting device has released the bus. See Figure 6.

Figure 6. Valid Start and Stop Conditions

SCL

SDA

Start

Stop

Serial Acknowledge

will acknowledge all incoming data and address bytes,

except for the Slave Address Byte when the Device

Identiﬁer and/or Select bits are incorrect.

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device, either

master or slave, will release the bus after transmitting

eight bits. During the ninth clock cycle, the receiver will

pull the SDA line LOW to acknowledge that it received

the eight bits of data. Refer to Figure 7.

In the read mode, the device will transmit eight bits of

data, release the SDA line, then monitor the line for an

acknowledge. If an acknowledge is detected and no

stop condition is generated by the master, the device

will continue to transmit data. The device will terminate

further data transmissions if an acknowledge is not

detected. The master must then issue a stop condition

to return the device to Standby mode and place the

device into a known state.

The device will respond with an acknowledge after rec-

ognition of a start condition and if the correct Device

Identiﬁer and Select bits are contained in the Slave

Address Byte. If a write operation is selected, the

device will respond with an acknowledge after the

receipt of each subsequent eight bit word. The device

Figure 7. Acknowledge Response From Receiver

SCL from

Master

1

8

9

Data Output

from Transmitter

Data Output

from Receiver

Start

Acknowledge

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X4643/5

Serial Write Operations

data. After receiving the 8 bits of the Data Byte, the

device again responds with an acknowledge. The mas-

ter then terminates the transfer by generating a stop

condition, at which time the device begins the internal

write cycle to the nonvolatile memory. During this inter-

nal write cycle, the device inputs are disabled, so the

device will not respond to any requests from the master.

The SDA output is at high impedance. See Figure 8.

BYTE WRITE

For a write operation, the device requires the Slave

Address Byte and a Word Address Byte. This gives the

master access to any one of the words in the array. After

receipt of the Word Address Byte, the device responds

with an acknowledge, and awaits the next eight bits of

Figure 8. Byte Write Sequence

S

t

Signals from

the Master

S

t

o

Slave

WordAddress WordAddress

Byte 1 Byte 0

a

r

Data

SDA Bus

1 0 1 0

0

A

C

K

A

C

K

A

C

K

A

C

K

Signals from

the Slave

A write to a protected block of memory will suppress

the acknowledge bit.

counter reaches the end of the page, it “rolls over” and

goes back to ‘0’ on the same page. This means that the

master can write 64-bytes to the page starting at any

location on that page. If the master begins writing at

location 60, and loads 12-bytes, then the ﬁrst 4-bytes

are written to locations 60 through 63, and the last

8-bytes are written to locations 0 through 7. After-

wards, the address counter would point to location 8 of

the page that was just written. If the master supplies

more than 64-bytes of data, then new data over-writes

the previous data, one byte at a time.

Page Write

The device is capable of a page write operation. It is

initiated in the same manner as the byte write opera-

tion; but instead of terminating the write cycle after the

ﬁrst data byte is transferred, the master can transmit

an unlimited number of 8-bit bytes. After the receipt of

each byte, the device will respond with an acknowl-

edge, and the address is internally incremented by

one. The page address remains constant. When the

Figure 9. Page Write Operation

(1 < n < 64)

S

t

a

r

Signals from

the Master

Data

t

Word Ad-

Slave

o

SDA Bus

1 0 1 0

0

A

C

A

C

A

C

A

C

A

C

Signals from

the Slave

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X4643/5

Figure 10. Writing 12 bytes to a 64-byte page starting at location 60.

8 Bytes

4 Bytes

Address Pointer

Ends Here

Addr = 8

Address

= 7

Address

n-1

60

The master terminates the Data Byte loading by issuing

a stop condition, which causes the device to begin the

nonvolatile write cycle. As with the byte write operation,

all inputs are disabled until completion of the internal

write cycle. See Figure 9 for the address, acknowledge,

and data transfer sequence.

Figure 11. Acknowledge Polling Sequence

Byte load completed

by issuing STOP.

Enter ACK Polling

Issue START

Stops and Write Modes

Stop conditions that terminate write operations must

be sent by the master after sending at least 1 full data

byte plus the subsequent ACK signal. If a stop is

issued in the middle of a data byte, or before 1 full data

byte plus its associated ACK is sent, then the device

will reset itself without performing the write. The con-

tents of the array will not be effected.

Issue Slave Address

Byte (Read or Write)

Issue STOP

NO

ACK

returned?

Acknowledge Polling

YES

The disabling of the inputs during nonvolatile cycles

can be used to take advantage of the typical 5ms write

cycle time. Once the stop condition is issued to indi-

cate the end of the master’s byte load operation, the

device initiates the internal nonvolatile cycle. Acknowl-

edge polling can be initiated immediately. To do this,

the master issues a start condition followed by the

Slave Address Byte for a write or read operation. If the

device is still busy with the nonvolatile cycle then no

ACK will be returned. If the device has completed the

write operation, an ACK will be returned and the host

can then proceed with the read or write operation.

Refer to the ﬂow chart in Figure 11.

NO

Nonvolatile Cycle

complete. Continue

command sequence?

Issue STOP

YES

Continue Normal

Read or Write

Command Sequence

PROCEED

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X4643/5

Serial Read Operations

Upon receipt of the Slave Address Byte with the R/W

bit set to one, the device issues an acknowledge and

then transmits the eight bits of the Data Byte.The mas-

ter terminates the read operation when it does not

respond with an acknowledge during the ninth clock

and then issues a stop condition. Refer to Figure 12 for

the address, acknowledge, and data transfer

sequence.

Read operations are initiated in the same manner as

write operations with the exception that the R/W bit of

the Slave Address Byte is set to one. There are three

basic read operations: Current Address Reads, Ran-

dom Reads, and Sequential Reads.

Current Address Read

Internally the device contains an address counter that

maintains the address of the last word read incre-

mented by one. Therefore, if the last read was to

address n, the next read operation would access data

from address n+1. On power up, the address of the

address counter is undeﬁned, requiring a read or write

operation for initialization.

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read

operation, the master must either issue a stop condi-

tion during the ninth cycle or hold SDA HIGH during

the ninth clock cycle and then issue a stop condition.

Figure 12. Current Address Read Sequence

S

t

Signals from

a

S

t

o

p

Slave

Address

the Master

r

t

SDA Bus

1 0 1 0

1

A

C

Signals from

the Slave

Data

K

Random Read

of the Word Address Bytes, the master immediately

issues another start condition and the Slave Address

Byte with the R/W bit set to one. This is followed by an

acknowledge from the device and then by the eight bit

word. The master terminates the read operation by not

responding with an acknowledge and then issuing a

stop condition. Refer to Figure 13 for the address,

acknowledge, and data transfer sequence.

Random read operation allows the master to access

any memory location in the array. Prior to issuing the

Slave Address Byte with the R/W bit set to one, the

master must ﬁrst perform a “dummy” write operation.

The master issues the start condition and the Slave

Address Byte, receives an acknowledge, then issues

the Word Address Bytes. After acknowledging receipts

Figure 13. Random Address Read Sequence

S

Signals from

the Master

t

a

r

S

t

o

p

t

a

r

Slave

Address

Word Address

Byte 1

Word Address

Byte 0

Slave

Address

t

SDA Bus

1 0 1 0

0

1

A

C

K

A

C

K

A

C

K

A

C

K

Signals from

the Slave

Data

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X4643/5

There is a similar operation, called “Set Current

Address” where the device does no operation, but

enters a new address into the address counter if a stop

is issued instead of the second start shown in Figure

13. The device goes into standby mode after the stop

and all bus activity will be ignored until a start is

detected. The next Current Address Read operation

reads from the newly loaded address. This operation

could be useful if the master knows the next address it

needs to read, but is not ready for the data.

cating it requires additional data. The device continues

to output data for each acknowledge received. The

master terminates the read operation by not respond-

ing with an acknowledge and then issuing a stop con-

dition.

The data output is sequential, with the data from

address n followed by the data from address n + 1. The

address counter for read operations increments

through all page and column addresses, allowing the

entire memory contents to be serially read during one

operation. At the end of the address space the counter

Sequential Read

“rolls over” to address 0000 and the device continues

H

Sequential reads can be initiated as either a current

address read or random address read. The ﬁrst Data

Byte is transmitted as with the other modes; however,

the master now responds with an acknowledge, indi-

to output data for each acknowledge received. Refer to

Figure 14 for the acknowledge and data transfer

sequence.

Figure 14. Sequential Read Sequence

S

t

o

p

Signals from

Slave

the Master

SDA Bus

A

C

K

A

C

K

A

C

K

Address

1

A

C

K

Signals from

the Slave

Data

(2)

Data

(n-1)

Data

(1)

Data

(n)

(n is any integer greater than 1)

X4643/5 Addressing

– After loading the entire Slave Address Byte from the

SDA bus, the device compares the input slave byte

data to the proper slave byte. Upon a correct com-

pare, the device outputs an acknowledge on the SDA

line.

SLAVE ADDRESS BYTE

Following a start condition, the master must output a

Slave Address Byte.This byte consists of several parts:

Word Address

– a device type identiﬁer that is ‘1010’ to access the

array

The word address is either supplied by the master or

obtained from an internal counter. The internal counter

is undeﬁned on a power up condition.

– one bits of ‘0’.

– next two bits are the device address.

– one bit of the slave command byte is a R/W bit. The

R/W bit of the Slave Address Byte deﬁnes the opera-

tion to be performed.When the R/W bit is a one, then

a read operation is selected. A zero selects a write

operation. Refer to Figure 15.

Characteristics subject to change without notice. 12 of 22

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X4643/5

Figure 15. X4643/5 Addressing

Device Identifier

Device Select

1

0

1

0

S1

S0

R/W

Slave Address Byte

High Order Word Address

A12

(X6)

A11

(X5)

A10

(X4)

A9

(X3)

A8

(X2)

0

Word Address Byte 0–64K

Low Order Word Address

A7

(X1)

A6

(X0)

A5

(Y5)

A4

(Y4)

A3

(Y3)

A2

(Y2)

A1

(Y1)

A0

(Y0)

Word Address Byte 0 for all options

D7

D6

D5

D4

D3

D2

D1

D0

Data Byte for all options

Operational Notes

– Communication to the device is inhibited while

RESET/RESET is active and any in-progress com-

munication is terminated.

The device powers-up in the following state:

– The device is in the low power standby state.

– Block Lock bits can protect sections of the memory

array from write operations.

– The WEL bit is set to ‘0’. In this state it is not possible

to write to the device.

SYMBOL TABLE

– SDA pin is the input mode.

– RESET/RESET Signal is active for t

.

PURST

WAVEFORM

INPUTS

OUTPUTS

Data Protection

Must be

steady

Will be

steady

The following circuitry has been included to prevent

inadvertent writes:

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

– The WEL bit must be set to allow write operations.

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

– The proper clock count and bit sequence is required

prior to the stop bit in order to start a nonvolatile

write cycle.

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

– A three step sequence is required before writing into

the Control Register to change Watchdog Timer or

block lock settings.

N/A

Center Line

is High

Impedance

– The WP pin, when held HIGH, and WPEN bit at logic

HIGH will prevent all writes to the Control Register.

Characteristics subject to change without notice. 13 of 22

REV 1.27 2/11/04

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X4643/5

ABSOLUTE MAXIMUM RATINGS

COMMENT

Temperature under bias .................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on any pin with respect to VSS....-1.0V to +7V

D.C. output current ............................................... 5mA

Lead temperature (soldering, 10 seconds).........300°C

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device (at these or any other conditions above those

listed in the operational sections of this speciﬁcation) is

not implied. Exposure to absolute maximum rating con-

ditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature

Commercial

Industrial

Min.

0°C

Max.

70°C

Option

Supply Voltage Limits

2.7V to 5.5V

–2.7 and –2.7A

Blank and –4.5A

-40°C

+85°C

4.5V to 5.5V

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise speciﬁed.)

V

= 2.7 to 5.5V

CC

Symbol

Parameter

Min

Max

1.0

3.0

1

Unit

mA

µA

Test Conditions

= V x 0.1, V = V x 0.9

(1)

I

Active Supply Current Read

Active Supply Current Write

Standby Current DC (WDT off)

V

f

CC1

CC2

IL

CC

IH

CC

(1)

= 400kHz, SDA = Commands

SCL

(2)

V

= V

SB1

SDA

SCL SB

Others = GND or V

SB

(2)

I

Standby Current DC (WDT on)

20

µA

V

= V

SB2

SDA

SCL

SB

Others = GND or V

SB

I

Input Leakage Current

Output Leakage Current

10

µA

V

= GND to V

CC

LI

IN

I

= GND to V

CC

LO

SDA

Device is in Standby⁽¹⁾

(3)

V

Input LOW Voltage

Input nonvolatile

-0.5

V

x 0.3

+ 0.5

V

IL

CC

(3)

V

x 0.7

CC

IH

CC

Schmitt Trigger Input Hysteresis

Fixed input level

HYS

0.2

V

related level .05 x V

CC

V

Output LOW Voltage

0.4

V

I

= 3.0mA (2.7–5.5V)

OL

Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave

Address Byte are incorrect; 200ns after a stop ending a read operation; or t after a stop ending a write operation.

WC

(2) The device goes into Standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; t

after a stop that initiates

WC

a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.

(3) V Min. and V Max. are for reference only and are not tested.

IL

IH

Characteristics subject to change without notice. 14 of 22

REV 1.27 2/11/04

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X4643/5

CAPACITANCE (T = 25°C, f = 1.0 MHz, V

= 5V)

A

CC

Symbol

Parameter

Max.

Unit

pF

Test Conditions

= 0V

(4)

C

Output Capacitance (SDA, RST/RST)

Input Capacitance (SCL, WP)

8

6

V

OUT

(4)

pF

V

= 0V

IN

Notes: (4) This parameter is periodically sampled and not 100% tested.

EQUIVALENT A.C. LOAD CIRCUIT

A.C. TEST CONDITIONS

Input pulse levels

0.1V to 0.9V

CC

5V

Input rise and fall times

10ns

Input and output timing levels 0.5V

For V = 0.4V

OL

CC

1533Ω

and I = 3 mA

OL

SDA

or

RESET

Output load

Standard output load

100pF

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)

Symbol

Parameter

Min.

Max.

Unit

kHz

ns

µs

ns

µs

ns

µs

pF

f

SCL Clock Frequency

0

50

400

SCL

t

Pulse width Suppression Time at inputs

SCL LOW to SDA Data Out Valid

Time the bus free before start of new transmission

Clock LOW Time

IN

t

0.1

0.9

AA

t

1.3

BUF

t

1.3

LOW

t

Clock HIGH Time

0.6

HIGH

t

Start Condition Setup Time

Start Condition Hold Time

Data In Setup Time

0.6

SU:STA

HD:STA

SU:DAT

HD:DAT

SU:STO

t

0.6

100

0

t

Data In Hold Time

Stop Condition Setup Time

Data Output Hold Time

0.6

t

50

DH

t

SDA and SCL Rise Time

SDA and SCL Fall Time

WP Setup Time

20 + .1Cb

0.6

300

R

t

F

t

SU:WP

t

WP Hold Time

0

HD:WP

Cb

Capacitive load for each bus line

400

Notes: (1) Typical values are for T = 25°C and V = 5.0V

A

CC

(2) Cb = total capacitance of one bus line in pF.

Characteristics subject to change without notice. 15 of 22

REV 1.27 2/11/04

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X4643/5

TIMING DIAGRAMS

Bus Timing

t

F

t

LOW

R

HIGH

SCL

t

SU:DAT

t

SU:STO

SU:STA

HD:DAT

t

HD:STA

SDA IN

t

BUF

AA

DH

SDA OUT

WP Pin Timing

START

SCL

Clk 1

Clk 9

Slave Address Byte

SDA IN

WP

t

HD:WP

SU:WP

Write Cycle Timing

SCL

SDA

8th bit of Last Byte

ACK

t

WC

Stop

Start

Condition

Nonvolatile Write Cycle Timing

Symbol

Parameter

Write Cycle Time

Min.

Typ.⁽¹⁾

Max.

Unit

(1)

t

5

10

ms

WC

Notes: (1) t

is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.

WC

It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

Characteristics subject to change without notice. 16 of 22

REV 1.27 2/11/04

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X4643/5

Power-Up and Power-Down Timing

V

TRIP

V

CC

t

0 Volts

PURST

t

PURST

F

t

R

t

RPD

V

RVALID

RESET

(X4645)

V

RVALID

RESET

(X4643)

RESET Output Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

V

Reset Trip Point Voltage, X4643/5-4.5A

Reset Trip Point Voltage, X4643/5

Reset Trip Point Voltage, X4643/5-2.7A

Reset Trip Point Voltage, X4643/5-2.7

4.5

4.62

4.38

2.92

2.62

4.75

4.5

3.0

2.7

V

TRIP

4.25

2.85

2.55

t

Power-up Reset Time Out

100

250

400

500

ms

ns

µs

V

PURST

(8)

t

V

Detect to Reset/Output

Fall Time

RPD

CC

(8)

t

100

1

F

(8)

t

Rise Time

R

V

Reset Valid V

CC

RVALID

Notes: (8) This parameter is periodically sampled and not 100% tested.

SDA vs. RESET Timing

t

>t

RSP

RSP WDO

t

>t

t

RST

t

<t

RST

RSP WDO

SCL

SDA

RESET

Note: All inputs are ignored during the active reset period (t

).

RST

Characteristics subject to change without notice. 17 of 22

REV 1.27 2/11/04

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X4643/5

RESET Output Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

t

Watchdog Time Out Period,

WD1 = 1, WD0 = 1 (factory setting)

WD1 = 1, WD0 = 0

WDO

OFF

250

650

1.5

100

450

1

300

850

2

ms

sec

WD1 = 0, WD0 = 1

WD1 = 0, WD0 = 0

t

Reset Time Out

100

250

400

ms

RST

V

Programming Timing Diagram (WEL = 1)

TRIP

V

CC

V

TRIP

(V

)

TRIP

t

TSU

t

THD

V

P

WP

t

VPH

VPS

VPO

SCL

SDA

t

RP

00h

01h or 03h

00h

A0h

V

Programming Parameters

TRIP

Parameter

Description

Min. Max. Unit

t

V

Program Enable Voltage Setup time

Program Enable Voltage Hold time

Setup time

1

µs

ms

µs

ms

V

VPS

VPH

TRIP

t

1

TSU

THD

t

Hold (stable) time

10

t

Write Cycle Time

10

18

WC

t

Program Enable Voltage Off time (Between successive adjustments)

Program Recovery Period (Between successive adjustments)

0

VPO

t

10

15

RP

V

Programming Voltage

Programmed Voltage Range

P

V

2.55 4.75

V

TRAN

TRIP

V

Initial V

Program Voltage accuracy (V applied–V ) (Programmed at 25°C.) -0.1

TRIP

+0.4

+25

V

ta1

ta2

TRIP

CC

Subsequent V

Programmed at 25°C.)

Program Voltage accuracy [(V applied–V )—V .

TRIP

-25

mV

TRIP

CC

ta1

V

Program Voltage repeatability (Successive program operations. Programmed

+25

mV

tr

TRIP

at 25°C.)

V

TRIP

Program variation after programming (0–75°C). (Programmed at 25°C.)

tv

V

programming parameters are periodically sampled and are not 100% tested.

TRIP

Characteristics subject to change without notice. 18 of 22

REV 1.27 2/11/04

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X4643/5

PACKAGING INFORMATION

8-Lead Plastic Small Outline Gull Wing Package Type S

0.150 (3.80) 0.228 (5.80)

0.158 (4.00) 0.244 (6.20)

Pin 1 Index

Pin 1

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

(4X) 7°

0.053 (1.35)

0.069 (1.75)

0.004 (0.19)

0.010 (0.25)

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

0.050"Typical

X 45°

0.050"

Typical

0° - 8°

0.0075 (0.19)

0.010 (0.25)

0.250"

0.016 (0.410)

0.037 (0.937)

0.030"

Typical

8 Places

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

Characteristics subject to change without notice. 19 of 22

REV 1.27 2/11/04

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X4643/5

PACKAGING INFORMATION

8-Lead Plastic, TSSOP, Package Type V

.025 (.65) BSC

.169 (4.3)

.252 (6.4) BSC

.177 (4.5)

.114 (2.9)

.122 (3.1)

.047 (1.20)

.0075 (.19)

.0118 (.30)

.002 (.05)

.006 (.15)

.010 (.25)

Gage Plane

0° – 8°

Seating Plane

.019 (.50)

.029 (.75)

(7.72)

(4.16)

Detail A (20X)

(1.78)

(0.42)

.031 (.80)

.041 (1.05)

(0.65)

All Measurements Are Typical

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

Characteristics subject to change without notice. 20 of 22

REV 1.27 2/11/04

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X4643/5

Ordering Information

V

Operating

Temperature Range

Part Number RESET

(Active LOW)

Part Number RESET

(Active HIGH)

CC

TRIP

Range

Package

4.5-5.5V

4.5-4.75

8L SOIC

0°C–70°C

-40°C–85°C

0°C–70°C

X4643S8–4.5A

X4643S8I–4.5A

X4643V8–4.5A

X4643V8I–4.5A

X4643S8

X4645S8–4.5A

X4645S8I–4.5A

X4645V8–4.5A

X4645V8I–4.5A

X4645S8

8L TSSOP

8L SOIC

-40°C–85°C

0°C–70°C

4.5-5.5V

2.7-5.5V

4.25-4.5

2.85-3.0

2.55-2.7

-40°C–85°C

0°C–70°C

X4643S8I

X4645S8I

8L TSSOP

8L SOIC

X4643V8

X4645V8

-40°C–85°C

0°C–70°C

X4643V8I

X4645V8I

X4643S8–2.7A

X4643S8I–2.7A

X4643V8–2.7A

X4643V8I–2.7A

X4643S8–2.7

X4643S8I–2.7

X4643V8–2.7

X4643V8I–2.7

X4645S8–2.7A

X4645S8I–2.7A

X4645V8–2.7A

X4645V8I–2.7A

X4645S8–2.7

X4645S8I–2.7

X4645V8–2.7

X4645V8I–2.7

-40°C–85°C

0°C–70°C

8LTSSOP

8L SOIC

-40°C–85°C

0°C–70°C

-40°C–85°C

0°C–70°C

8L TSSOP

-40°C–85°C

Part Mark Information

8-Lead TSSOP

8-Lead SOIC/PDIP

EYWW

XXXXX

Blank = 8-Lead SOIC

X4643/5 X

XX

ADB/ADK = –4.5A (0 to +70°C)

AL = –4.5A (0 to +70°C)

ADD/ADM = No Suffix (0 to +70°C)

ADF/ADO = –2.7A (0 to +70°C)

ADH/ADQ= –2.7 (0 to +70°C)

AM = –4.5A (-40 to +85°C)

Blank = No Suffix (0 to +70°C)

I = No Suffix (-40 to +85°C)

AN = –2.7A (0 to +70°C)

AP = –2.7A (-40 to +85°C)

F = –2.7 (0 to +70°C)

4283/4285

G = –2.7 (-40 to +85°C)

Characteristics subject to change without notice. 21 of 22

REV 1.27 2/11/04

www.xicor.com

X4643/5

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemniﬁcation provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,

express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.

Xicor, Inc. makes no warranty of merchantability or ﬁtness for any purpose. Xicor, Inc. reserves the right to discontinue production and change speciﬁcations and prices

at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All

others belong to their respective owners.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;

4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;

5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection

and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signiﬁcant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

Characteristics subject to change without notice. 22 of 22

REV 1.27 2/11/04

www.xicor.com


型号：	X4643V8
厂家：	XICOR INC.
描述：	Power Supply Management Circuit, Adjustable, 1 Channel, CMOS, PDSO8, PLASTIC, TSSOP-8 光电二极管
文件：	总22页 (文件大小：507K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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