X5045S8I_技术文档

4K

512 x 8 Bit

X5043/X5045

CPU Supervisor with 4K SPI EEPROM

DESCRIPTION

FEATURES

• Selectable time out watchdog timer

• Low V detection and reset assertion

These devices combine four popular functions, Power-

on Reset Control, Watchdog Timer, Supply Voltage

Supervision, and Block Lock Protect Serial EEPROM

Memory in one package. This combination lowers

system cost, reduces board space requirements, and

increases reliability.

CC

—Five standard reset threshold voltages

—Re-program low V reset threshold voltage

CC

using special programming sequence.

—Reset signal valid to V = 1V

CC

• Long battery life with low power consumption

—<50µA max standby current, watchdog on

—<10µA max standby current, watchdog off

—<2mA max active current during read

• 2.7V to 5.5V and 4.5V to 5.5V power supply

versions

• 4Kbits of EEPROM–1M write cycle endurance

• Save critical data with Block Lock^™memory

—Protect 1/4, 1/2, all or none of EEPROM array

• Built-in inadvertent write protection

—Write enable latch

—Write protect pin

• 3.3MHz clock rate

• Minimize programming time

—16-byte page write mode

—Self-timed write cycle

Applying power to the device activates the power on

reset circuit which holds RESET/RESET active for a

period of time. This allows the power supply and oscil-

lator to stabilize before the processor executes code.

The Watchdog Timer provides an independent protec-

tion mechanism for microcontrollers. When the micro-

controller fails to restart a timer within a selectable

time out interval, the device activates the RESET/

RESET signal. The user selects the interval from three

preset values. Once selected, the interval does not

change, even after cycling the power.

The device’s low V

detection circuitry protects the

CC

user’s system from low voltage conditions, resetting

the system when V

falls below the minimum V

CC

trip point. RESET/RESET is asserted until V

returns

CC

—5ms write cycle time (typical)

• SPI modes (0,0 & 1,1)

• Available packages

—8-lead MSOP, 8-lead SOIC, 8-pin PDIP

—14-lead TSSOP

to proper operating level and stabilizes. Five industry

standard V thresholds are available, however,

TRIP

Xicor’s unique circuits allow the threshold to be repro-

grammed to meet custom requirements or to ﬁne-tune

the threshold for applications requiring higher precision.

BLOCK DIAGRAM

Watchdog Transition

Detector

Watchdog

Timer Reset

WP

Protect Logic

RESET/RESET

SI

Data

Register

Status

Register

SO

X5043 = RESET

X5045 = RESET

Command

Decode &

Control

Reset &

Watchdog

Timebase

SCK

1Kbits

CS/WDI

Logic

V

Threshold

CC

2Kbits

Reset Logic

Power on and

Low Voltage

Reset

V

+

-

CC

V

Generation

TRIP

Characteristics subject to change without notice. 1 of 20

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X5043/X5045

The memory portion of the device is a CMOS Serial

EEPROM array with Xicor’s block lock protection. The

array is internally organized as x 8. The device features

a Serial Peripheral Interface (SPI) and software proto-

col allowing operation on a simple four-wire bus.

Chip Select (CS)

When CS is high, the X5043/45 is deselected and the

SO output pin is at high impedance and, unless an

internal write operation is underway, the X5043/45 will

be in the standby power mode. CS low enables the

X5043/45, placing it in the active power mode. It should

be noted that after power-up, a high to low transition on

CS is required prior to the start of any operation.

The device utilizes Xicor’s proprietary Direct Write^™

cell, providing a minimum endurance of 1,000,000

cycles and a minimum data retention of 100 years.

Write Protect (WP)

PIN CONFIGURATION

When WP is low, nonvolatile writes to the X5043/45 are

disabled, but the part otherwise functions normally.

When WP is held high, all functions, including non vol-

atile writes operate normally. WP going low while CS is

still low will interrupt a write to the X5043/45. If the

internal write cycle has already been initiated, WP

going low will have no affect on a write.

8-Lead SOIC/PDIP/MSOP

V

1

2

3

4

8

7

6

5

CS/WDI

SO

CC

RESET/RESET

X5043/45

WP

SCK

SI

V

SS

Reset (RESET, RESET)

X5043/45, RESET/RESET is an active low/HIGH,

14-Lead TSSOP

open drain output which goes active whenever V

CC

falls below the minimum V sense level. It will remain

V

1

2

3

4

5

6

7

14

13

12

11

10

9

CC

CS

SO

NC

CC

active until V

rises above the minimum V

sense

CC

RESET/RESET

level for 200ms. RESET/RESET also goes active if the

Watchdog timer is enabled and CS remains either high

or low longer than the Watchdog time out period. A fall-

ing edge of CS will reset the watchdog timer.

NC

X5043/45

NC

SCK

SI

WP

PIN NAMES

V

8

SS

Symbol

CS

Description

Chip Select Input

Serial Output

Serial Input

PIN DESCRIPTIONS

Serial Output (SO)

SO

SI

SO is a push/pull serial data output pin. During a read

cycle, data is shifted out on this pin. Data is clocked out

by the falling edge of the serial clock.

SCK

WP

Serial Clock Input

Write Protect Input

Ground

V

SS

Serial Input (SI)

V

Supply Voltage

Reset Output

CC

SI is the serial data input pin. All opcodes, byte

addresses, and data to be written to the memory are

input on this pin. Data is latched by the rising edge of

the serial clock.

RESET/RESET

Serial Clock (SCK)

The Serial Clock controls the serial bus timing for data

input and output. Opcodes, addresses, or data present

on the SI pin is latched on the rising edge of the clock

input, while data on the SO pin changes after the fall-

ing edge of the clock input.

Characteristics subject to change without notice. 2 of 20

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X5043/X5045

PRINCIPLES OF OPERATION

Power On Reset

V

Threshold Reset Procedure

CC

The X5043/X5045 is shipped with a standard V

threshold (V

CC

) voltage. This value will not change

TRIP

Application of power to the X5043/X5045 activates a

Power On Reset Circuit. This circuit pulls the RESET/

RESET pin active. RESET/RESET prevents the sys-

tem microprocessor from starting to operate with insuf-

ﬁcient voltage or prior to stabilization of the oscillator.

over normal operating and storage conditions. How-

ever, in applications where the standard V is not

TRIP

exactly right, or if higher precision is needed in the

value, the X5043/X5045 threshold may be

V

TRIP

adjusted. The procedure is described below, and uses

the application of a high voltage control signal.

When V

exceeds the device V

value for 200ms

CC

TRIP

(nominal) the circuit releases RESET/RESET, allowing

the processor to begin executing code.

Setting the V

Voltage

TRIP

This procedure is used to set the V

age value. For example, if the current V

to a higher volt-

TRIP

Low Voltage Monitoring

is 4.4V

TRIP

During operation, the X5043/X5045 monitors the V

and the new V

is 4.6V, this procedure will directly

CC

TRIP

level and asserts RESET/RESET if supply voltage falls

below a preset minimum V . The RESET/RESET

signal prevents the microprocessor from operating in a

power fail or brownout condition. The RESET/RESET

signal remains active until the voltage drops below 1V.

make the change. If the new setting is to be lower than

the current setting, then it is necessary to reset the trip

point before setting the new value.

TRIP

To set the new V

voltage, apply the desired V

TRIP

threshold voltage to the V

pin and tie the WP pin to

CC

It also remains active until V

returns and exceeds

CC

the programming voltage V . Then send a WREN com-

P

V

for 200ms.

TRIP

mand, followed by a write of Data 00h to address 01h.

CS going HIGH on the write operation initiates the

Watchdog Timer

V

programming sequence. Bring WP LOW to com-

TRIP

The Watchdog Timer circuit monitors the microproces-

sor activity by monitoring the WDI input. The micropro-

cessor must toggle the CS/WDI pin periodically to

prevent an active RESET/RESET signal. The CS/WDI

pin must be toggled from HIGH to LOW prior to the

expiration of the watchdog time out period. The state of

two nonvolatile control bits in the Status Register

determines the watchdog timer period. The micropro-

cessor can change these watchdog bits. With no

microprocessor action, the watchdog timer control bits

remain unchanged, even during total power failure.

plete the operation.

Note: This operation also writes 00h to array address 01h.

Figure 1. Set V

Level Sequence (V = desired V

value.)

TRIP

CC

TRIP

V

= 15-18V

PE

WP

CS

0

1 2 3 4 5 6 7

0

1

2 3

4

5 6 7 8 9 10 11 12 13 14 15

SCK

8 Bits

SI

06h

02h

00h

01h

WREN

Write

Address

Data

Characteristics subject to change without notice. 3 of 20

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X5043/X5045

Resetting the V

Voltage

To reset the V

voltage, apply at least 3V to the V

TRIP

TRIP CC

pin and tie the WP pin to the programming voltage V .

Then send a WREN command, followed by a write of

Data 00h to address 03h. CS going HIGH on the write

P

This procedure is used to set the V

voltage level. For example, if the current V

to a “native”

TRIP

is 4.4V

TRIP

and the new V

must be 4.0V, then the V

must

TRIP

operation initiates the V

programming sequence.

TRIP

be reset. When V

is reset, the new V

is some-

TRIP

Bring WP LOW to complete the operation.

thing less than 1.7V. This procedure must be used to

set the voltage to a lower value.

Note: This operation also writes 00h to array address

03h.

Figure 2. Reset V

Level Sequence (V

> 3V. WP = 15–18V)

TRIP

CC

V

= 15-18V

PE

WP

CS

0

1 2 3 4 5 6 7

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

8 Bits

SCK

SI

06h

WREN

02h

Write

00h

03h

Address

Data

Figure 3. Sample V

Reset Circuit

TRIP

4.7K

V

P

µC

RESET

1

8

Adjust

Run

2

3

4

7

6

5

X5043

X5045

SCK

SI

V

TRIP

Adj.

SO

CS

Characteristics subject to change without notice. 4 of 20

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X5043/X5045

Figure 4. V

Programming Sequence

SPI Serial Memory

TRIP

The memory portion of the device is a CMOS Serial

EEPROM array with Xicor’s block lock protection. The

array is internally organized as x8 bits. The device fea-

tures a Serial Peripheral Interface (SPI) and software

protocol allowing operation on a simple four-wire bus.

V

Programming

TRIP

Execute

Reset V

TRIP

Sequence

The device utilizes Xicor’s proprietary Direct Write^™

cell, providing a minimum endurance of 1,000,000

cycles and a minimum data retention of 100 years.

Set V

= V

Desired V

Applied =

TRIP

CC

The device is designed to interface directly with the

synchronous Serial Peripheral Interface (SPI) of many

popular microcontroller families.

New V

Old V

Applied

New V

Old V

Applied

CC

=

CC

=

Execute

Set V

CC

TRIP

CC

Sequence

- Error

The device contains an 8-bit instruction register that

controls the operation of the device. The instruction

code is written to the device via the SI input. There are

two write operations that requires only the instruction

byte. There are two read operations that use the

instruction byte to initiate the output of data. The

remainder of the operations require an instruction byte,

an 8-bit address, then data bytes. All instruction,

address and data bits are clocked by the SCK input. All

instructions (Table 1), addresses and data are trans-

ferred MSB ﬁrst.

Apply 5V to V

CC

Execute

TRIP

Sequence

Reset V

Decrement V

CC

(V

= V –10mV)

CC

NO

RESET pin

goes active?

YES

Clock and Data Timing

Data input on the SI line is latched on the first rising

edge of SCK after CS goes LOW. Data is output on the

SO line by the falling edge of SCK. SCK is static,

allowing the user to stop the clock and then start it

again to resume operations where left off. CS must be

LOW during the entire operation.

Measured V

-Desired V

TRIP

Error ≤ -Emax

Error ≥ Emax

-Emax < Error < Emax

DONE

Emax = Maximum Desired Error

Table 1. Instruction Set

Instruction Name Instruction Format*

Operation

WREN

WRDI

0000 0110

0000 0100

0000 0101

0000 0001

Set the Write Enable Latch (Enable Write Operations)

Reset the Write Enable Latch (Disable Write Operations)

Read Status Register

RSDR

WRSR

READ

WRITE

Write Status Register (Watchdog and Block Lock)

Read Data from Memory Array Beginning at Selected Address

Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)

0000 A 011

8

0000 A 010

8

Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB ﬁrst.

Characteristics subject to change without notice. 5 of 20

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X5043/X5045

Write Enable Latch

The block lock bits, BL0 and BL1, set the level of block

lock protection. These nonvolatile bits are programmed

using the WRSR instruction and allow the user to pro-

tect one quarter, one half, all or none of the EEPROM

array. Any portion of the array that is block lock pro-

tected can be read but not written. It will remain pro-

tected until the BL bits are altered to disable block lock

protection of that portion of memory.

The device contains a Write Enable Latch. This latch

must be SET before a Write Operation is initiated. The

WREN instruction will set the latch and the WRDI

instruction will reset the latch (Figure 3). This latch is

automatically reset upon a power-up condition and after

the completion of a valid byte, page, or status register

write cycle.The latch is also reset if WP is brought LOW.

Status Reg Bits

Array Addresses Protected

X5043/X5045

None

When issuing a WREN, WRDI or RDSR commands, it

is not necessary to send a byte address or data.

BL1

BL0

0

1

0

1

0

1

Figure 5. Write Enable/Disable Latch Sequence

$180–$1FF

$100–$1FF

CS

$000–$1FF

0

1

2

3

4

5

6

7

The Watchdog Timer bits, WD0 and WD1, select the

Watchdog Time-out Period. These nonvolatile bits are

programmed with the WRSR instruction.

SCK

Status Register Bits

Watchdog Time Out

SI

WD1

WD0

(Typical)

High Impedance

SO

0

1

0

1

0

1

1.4 seconds

600 milliseconds

200 milliseconds

disabled (factory default)

Status Register

The Status Register contains four nonvolatile control

bits and two volatile status bits. The control bits set the

operation of the watchdog timer and the memory block

lock protection. The Status Register is formatted as

shown in “Status Register”.

Read Status Register

To read the Status Register, pull CS low to select the

device, then send the 8-bit RDSR instruction. Then the

contents of the Status Register are shifted out on the

SO line, clocked by CLK. Refer to the Read Status

Register Sequence (Figure 6). The Status Register

may be read at any time, even during a Write Cycle.

Status Register: (Default = 30H)

7

6

5

4

3

2

1

0

WD1 WD0 BL1 BL0 WEL WIP

Write Status Register

The Write-In-Progress (WIP) bit is a volatile, read only

bit and indicates whether the device is busy with an

internal nonvolatile write operation. The WIP bit is read

using the RDSR instruction. When set to a “1”, a non-

volatile write operation is in progress. When set to a

“0”, no write is in progress.

Prior to any attempt to write data into the status regis-

ter, the “Write Enable” Latch (WEL) must be set by

issuing the WREN instruction (Figure 5). First pull CS

LOW, then clock the WREN instruction into the device

and pull CS HIGH. Then bring CS LOW again and

enter the WRSR instruction followed by 8 bits of data.

These 8 bits of data correspond to the contents of the

status register. The operation ends with CS going

HIGH. If CS does not go HIGH between WREN and

WRSR, the WRSR instruction is ignored.

The Write Enable Latch (WEL) bit indicates the status

of the “write enable” latch. When WEL = 1, the latch is

set and when WEL = 0 the latch is reset. The WEL bit is

a volatile, read only bit. The WREN instruction sets the

WEL bit and the WRDS instruction resets the WEL bit.

Characteristics subject to change without notice. 6 of 20

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X5043/X5045

Table 2. Device Protect Matrix

Memory Block

Status Register

(BL0, BL1, WD0, WD1)

Protected

WREN CMD

(WEL)

Device Pin

(WP)

Protected Area

Unprotected Area

Protected

0

x

1

x

0

1

Protected

Writable

Figure 6. Read Status Register Sequence

CS

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14

15

SCK

Instruction

SI

Data Out

High Impedance

SO

7

6

5

4

3

2

1

0

MSB

Figure 7. Write Status Register Sequence

CS

0

1

2

3

4

5

6

7

8

7

9

6

10 11 12 13 14 15

SCK

Data Byte

Instruction

5

4

3

2

1

0

SI

High Impedance

SO

Read Memory Array

address can be read sequentially by continuing to pro-

vide clock pulses. The address is automatically incre-

mented to the next higher address after each byte of

data is shifted out. When the highest address is

reached, the address counter rolls over to address

$000 allowing the read cycle to be continued indeﬁ-

nitely. The read operation is terminated by taking CS

high. Refer to the Read EEPROM Array Sequence

(Figure 8).

When reading from the EEPROM memory array, CS is

ﬁrst pulled low to select the device. The 8-bit READ

instruction is transmitted to the device, followed by the

8-bit address. Bit 3 of the READ instruction selects the

upper or lower half of the device. After the READ

opcode and address are sent, the data stored in the

memory at the selected address is shifted out on the

SO line. The data stored in memory at the next

Characteristics subject to change without notice. 7 of 20

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X5043/X5045

Figure 8. Read EEPROM Array Sequence

CS

0

1

2

3

4

5

6

7

8

9

6

10

12 13 14 15 16 17 18 19 20 21 22

SCK

SI

Instruction

8 Bit Address

7

5

3

2

1

0

8

9^thBit of Address

Data Out

High Impedance

7

6

5

4

3

2

1

0

SO

MSB

Write Memory Array

must reside within the same page. A page address

begins with address [x xxxx 0000] and ends with [x

xxxx 1111]. If the byte address reaches the last byte on

the page and the clock continues, the counter will roll

back to the ﬁrst address of the page and overwrite any

data that has been previously written.

Prior to any attempt to write data into the memory

array, the “Write Enable” Latch (WEL) must be set by

issuing the WREN instruction (Figure 5). First pull CS

LOW, then clock the WREN instruction into the device

and pull CS HIGH. Then bring CS LOW again and

enter the WRITE instruction followed by the 8-bit

address and then the data to be written. Bit 3 of the

For the write operation (byte or page write) to be com-

pleted, CS must be brought HIGH after bit 0 of the last

complete data byte to be written is clocked in. If it is

brought HIGH at any other time, the write operation will

not be completed (Figure 9).

WRITE instruction contains address bit A , which

8

selects the upper or lower half of the array. If CS does

not go HIGH between WREN and WRITE, the WRITE

instruction is ignored.

While the write is in progress following a status register

or memory array write sequence, the Status Register

may be read to check the WIP bit. WIP is HIGH while

the nonvolatile write is in progress.

The WRITE operation requires at least 16 clocks. CS

must go low and remain low for the duration of the

operation. The host may continue to write up to 16

bytes of data. The only restriction is that the 16 bytes

Characteristics subject to change without notice. 8 of 20

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X5043/X5045

Figure 9. Write Memory Sequence

CS

0

1

2

3

4

8

5

6

7

8

7

9

10

12 13 14 15 16 17 18 19 20 21 22 23

SCK

SI

Instruction

8 Bit Address

Data Byte 1

6

5

3

2

1

0

7

6

5

4

3

2

1

0

9^thBit of Address

CS

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SCK

Data Byte 2

Data Byte 3

Data Byte N

SI

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

6

5

4

3

2

1

0

OPERATIONAL NOTES

The device powers-up in the following state:

– The device is in the low power standby state.

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

– A WREN instruction must be issued to set the Write

Enable Latch.

– A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

– CS must come HIGH at the proper clock count in

order to start a nonvolatile write cycle.

– SO pin is high impedance.

– The Write Enable Latch is reset.

– The Flag Bit is reset.

– Block Protect bits provide additional level of write

protection for the memory array.

– Reset Signal is active for t

.

– The WP pin LOW blocks nonvolatile write operations.

PURST

Characteristics subject to change without notice. 9 of 20

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X5043/X5045

ABSOLUTE MAXIMUM RATINGS

COMMENT

Temperature under bias ....................–65°C to +135°C

Storage temperature ........................–65°C to +150°C

Voltage on any pin with

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device (at these or any other conditions above those

listed in the operational sections of this speciﬁcation) is

not implied. Exposure to absolute maximum rating con-

ditions for extended periods may affect device reliability.

respect to V ......................................–1.0V to +7V

SS

D.C. output current ............................................... 5mA

Lead temperature (soldering, 10 seconds).........300°C

RECOMMENDED OPERATING CONDITIONS

Temperature

Commercial

Industrial

Min.

0°C

Max.

70°C

Option

-2.7, -2.7A

Blank, -4.5A

Supply Voltage Limits

2.7V to 5.5V

–40°C

+85°C

4.5V to 5.5V

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise speciﬁed.)

Limits

Symbol

Parameter

Min.

Typ.⁽²⁾

Max.

Unit

Test Conditions/Comments

I

V

Write Current (Active)

3

mA SCK = 3.3MHz⁽³⁾; SO, RESET,

RESET = Open

CC1

CC

I

Read Current (Active)

2

mA SCK = 3.3MHz⁽³⁾; SI = V , RESET,

CC2

SS

RESET = Open

I

Standby Current

10

50

µA

CS = V , SCK, SI = V

,

SB1

SB2

CC

SS

WDT = OFF

V

= 5.5V

CC

V

Standby Current

CS = V , SCK, SI = V

CC

SS

WDT = ON

V

= 5.5V

I

Input Leakage Current

Output Leakage Current

Input LOW Voltage

Input HIGH Voltage

Output LOW Voltage (SO)

0.1

10

µA

V

SCK, SI, WP = V to V

SS CC

LI

I

SO, RESET, RESET = V to V

SS

LO

CC

(1)

V

–0.5

V

x 0.3

SCK, SI, WP, CS

IL

CC

(1)

V

x 0.7

V

+ 0.5

V

IH

CC

V

0.4

V

I

= 2mA @ V = 2.7V

CC

OL

= 0.5mA @ V = 1.8V

CC

V

Output HIGH Voltage (SO)

V

– 0.8

– 0.4

– 0.2

V

> 3.3V, I

= –1.0mA

OH1

OH2

OH3

CC

OH

2V < V ≤ 3.3V, I

= –0.4mA

CC

OH

V

≤ 2V, I

= –0.25mA

CC

OH

V

Output LOW Voltage

(RESET, RESET)

0.4

I

= 1mA

OL

OLRS

CAPACITANCE T = +25°C, f = 1MHz, V

= 5V

A

CC

Symbol

Test

Max.

Unit

Conditions

= 0V

(2)

OUT

C

Output Capacitance (SO, RESET, RESET)

Input Capacitance (SCK, SI, CS, WP)

8

6

pF

V

OUT

(2)

IN

C

V

= 0V

IN

Notes: (1) V min. and V max. are for reference only and are not tested.

IL

IH

(2) This parameter is periodically sampled and not 100% tested.

(3) SCK frequency measured from V x 0.1/V x 0.9

CC

Characteristics subject to change without notice. 10 of 20

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X5043/X5045

Equivalent A.C. Load Circuit at 5V V

A.C. Test Conditions

CC

Input pulse levels

V

x 0.1 to V x 0.9

CC

5V

Input rise and fall times

Input and output timing level

10ns

V

x0.5

CC

4.6KΩ

1.64KΩ

Output

1.64KΩ

RESET/RESET

30pF

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise speciﬁed)

Data Input Timing

2.7V–5.5V

Symbol

Parameter

Min.

0

Max.

Unit

MHz

ns

f

Clock Frequency

Cycle Time

3.3

SCK

CYC

t

300

150

130

30

t

CS Lead Time

CS Lag Time

ns

LEAD

t

ns

LAG

t

Clock HIGH Time

Clock LOW Time

Data Setup Time

Data Hold Time

Input Rise Time

Input Fall Time

CS Deselect Time

Write Cycle Time

ns

WH

t

ns

WL

t

ns

SU

t

30

ns

H

(3)

t

2

µs

RI

(3)

µs

FI

t

100

ns

CS

(4)

WC

t

10

ms

Data Output Timing

2.7–5.5V

Symbol

Parameter

Min.

Max.

3.3

Unit

MHz

ns

f

Clock Frequency

0

SCK

t

Output Disable Time

150

120

DIS

t

Output Valid from Clock Low

Output Hold Time

ns

V

t

0

ns

HO

(3)

t

Output Rise Time

50

ns

RO

(3)

Output Fall Time

ns

FO

Notes: (3) This parameter is periodically sampled and not 100% tested.

(4) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile

WC

write cycle.

Characteristics subject to change without notice. 11 of 20

REV 1.1.2 5/29/01

www.xicor.com

X5043/X5045

Serial Output Timing

CS

t

CYC

t

LAG

WH

SCK

SO

t

DIS

V

HO

WL

MSB Out

MSB–1 Out

LSB Out

ADDR

LSB IN

SI

Serial Input Timing

t

CS

SCK

SI

t

LAG

LEAD

t

RI

SU

H

tFI

MSB In

LSB In

High Impedance

SO

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

Characteristics subject to change without notice. 12 of 20

REV 1.1.2 5/29/01

www.xicor.com

X5043/X5045

Power-Up and Power-Down Timing

V

TRIP

V

CC

t

PURST

0 Volts

t

F

PURST

t

RPD

R

RESET (X5043)

RESET (X5045)

RESET Output Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

V

Reset Trip Point Voltage, (-4.5A)

Reset Trip Point Voltage, (Blank)

Reset Trip Point Voltage, (-2.7A)

Reset Trip Point Voltage, (-2.7)

4.5

4.62

4.38

2.92

2.62

4.75

4.5

3.0

2.7

TRIP

4.25

2.85

2.55

V

t

Power-up Reset Time Out

100

200

400

500

ms

ns

µs

ns

V

PURST

(5)

t

V

Detect to Reset/Output

Fall Time

RPD

CC

(5)

F

t

10

0.1

1

(5)

R

t

Rise Time

V

Reset Valid V

CC

RVALID

Note: (5) This parameter is periodically sampled and not 100% tested.

CS/WDI vs. RESET/RESET Timing

CS/WDI

t

CST

RESET

t

RST

WDO

RST

WDO

RESET

RESET/RESET Output Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

t

Watchdog Time Out Period,

WD1 = 1, WD0 = 0

WDO

100

450

1

200

600

1.4

300

800

2

ms

sec

WD1 = 0, WD0 = 1

WD1 = 0, WD0 = 0

t

CS Pulse Width to Reset the Watchdog

Reset Time Out

400

100

ns

CST

t

200

400

ms

RST

Characteristics subject to change without notice. 13 of 20

REV 1.1.2 5/29/01

www.xicor.com

X5043/X5045

V

Programming Timing Diagram

TRIP

V

TRIP

CC

V

TRIP

(V

)

t

THD

TSU

V

P

WP

t

VPH

VPS

VPO

t

PCS

CS

t

RP

SCK

SI

06h

02h

01h or

03h

V

Programming Parameters

TRIP

Parameter

Description

Min Max

Unit

µs

ms

µs

ms

V

t

V

Program Enable Voltage Setup time

Program Enable Voltage Hold time

Programming CS inactive time

Setup time

1

VPS

VPH

PCS

TRIP

t

1

t

1

TSU

t

Hold (stable) time

10

0

THD

t

Write Cycle Time

WC

t

Program Enable Voltage Off time (Between successive adjustments)

Program Recovery Period (Between successive adjustments)

VPO

t

10

RP

V

Programming Voltage

Programmed Voltage Range

15

1.7

-0.1

18

5.0

P

V

TRAN

TRIP

V

Initial V

at 25°C.)

Program Voltage accuracy (V applied–V ) (Programmed

TRIP

+0.4

V

ta1

TRIP

CC

V

Subsequent V

Program Voltage accuracy [(V applied–V )–V .

TRIP

-25

+25

mV

ta2

TRIP

CC

ta1

Programmed at 25°C.)

V Program Voltage repeatability (Successive program operations.

TRIP

V

tr

Programmed at 25°C.)

V

TRIP

Program variation after programming (0–75°C). (Programmed at 25°C.)

tv

V

programming parameters are periodically sampled and are not 100% tested.

TRIP

Characteristics subject to change without notice. 14 of 20

REV 1.1.2 5/29/01

www.xicor.com

X5043/X5045

PACKAGING INFORMATION

8-Lead Miniature Small Outline Gull Wing Package Type M

0.118 ± 0.002

(3.00 ± 0.05)

0.012 + 0.006 / -0.002

(0.30 + 0.15 / -0.05)

0.0256 (0.65) Typ.

R 0.014 (0.36)

0.118 ± 0.002

(3.00 ± 0.05)

0.030 (0.76)

0.0216 (0.55)

7° Typ.

0.036 (0.91)

0.032 (0.81)

0.040 ± 0.002

(1.02 ± 0.05)

0.008 (0.20)

0.004 (0.10)

0.0256" Typical

0.025"

Typical

0.150 (3.81)

0.007 (0.18)

0.005 (0.13)

Ref.

0.193 (4.90)

Ref.

0.220"

0.020"

Typical

8 Places

FOOTPRINT

NOTE:

1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)

Characteristics subject to change without notice. 15 of 20

REV 1.1.2 5/29/01

www.xicor.com

X5043/X5045

PACKAGING INFORMATION

8-Lead Plastic Dual In-Line Package Type P

0.430 (10.92)

0.360 (9.14)

0.260 (6.60)

0.240 (6.10)

Pin 1 Index

Pin 1

0.060 (1.52)

0.020 (0.51)

0.300

(7.62) Ref.

Half Shoulder Width On

All End Pins Optional

0.145 (3.68)

0.128 (3.25)

Seating

Plane

0.025 (0.64)

0.015 (0.38)

0.065 (1.65)

0.150 (3.81)

0.125 (3.18)

0.045 (1.14)

0.110 (2.79)

0.090 (2.29)

0.020 (0.51)

0.016 (0.41)

0.325 (8.25)

0.300 (7.62)

.073 (1.84)

Max.

0°

Typ. 0.010 (0.25)

15°

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

Characteristics subject to change without notice. 16 of 20

REV 1.1.2 5/29/01

www.xicor.com

X5043/X5045

PACKAGING INFORMATION

8-Lead Plastic Small Outline Gull Wing Package Type S

0.150 (3.80) 0.228 (5.80)

0.158 (4.00) 0.244 (6.20)

Pin 1 Index

Pin 1

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

(4X) 7°

0.053 (1.35)

0.069 (1.75)

0.004 (0.19)

0.010 (0.25)

0.050 (1.27)

0.010 (0.25)

0.050"Typical

X 45°

0.020 (0.50)

0.050"

Typical

0° - 8°

0.0075 (0.19)

0.010 (0.25)

0.250"

0.016 (0.410)

0.037 (0.937)

0.030"

Typical

8 Places

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

Characteristics subject to change without notice. 17 of 20

REV 1.1.2 5/29/01

www.xicor.com

X5043/X5045

PACKAGING INFORMATION

14-Lead Plastic, TSSOP, Package Type V

.025 (.65) BSC

.169 (4.3)

.177 (4.5)

.252 (6.4) BSC

.193 (4.9)

.200 (5.1)

.047 (1.20)

.0075 (.19)

.0118 (.30)

.002 (.05)

.006 (.15)

.010 (.25)

Gage Plane

0° - 8°

Seating Plane

.019 (.50)

.029 (.75)

Detail A (20X)

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

Characteristics subject to change without notice. 18 of 20

REV 1.1.2 5/29/01

www.xicor.com

X5043/X5045

Ordering Information

V

Operating

Temperature Range

Part Number RESET Part Number RESET

CC

TRIP

Range

Package

8-Pin PDIP

8L SOIC

(Active LOW)

X5043PI-4.5A

X5043S8I-4.5A

X5043M8I-4.5A

X5043V14I-4.5A

X5043PI

(Active HIGH)

X5045PI-4.5A

X5045S8I-4.5A

X5045M8I-4.5A

X5045V14I-4.5A

X5045PI

4.5-5.5V

4.5-4.75

-40°C–85°C

0°C–70°C

8L MSOP

14L TSSOP

8-Pin PDIP

8L SOIC

4.25-4.5

X5043S8

X5045S8

-40°C–85°C

0°C–70°C

X5043S8I

X5045S8I

8L MSOP

14L TSSOP

8L PDIP

X5043M8I

X5045M8I

X5043V14I

X5045V14I

2.7-5.5V

2.85-3.0

2.55-2.7

X5043PI-2.7A

X5043S8I-2.7A

X5043M8I-2.7A

X5043V14I-2.7A

X5043PI-2.7

X5043S8-2.7

X5043S8I-2.7

X5043M8I-2.7

X5043V14I-2.7

X5045PI-2.7A

X5045S8I-2.7A

X5045M8I-2.7A

X5045V14I-2.7A

X5045PI-2.7

X5045S8-2.7

X5045S8I-2.7

X5045M8I-2.7

X5045V14I-2.7

8L SOIC

8L MSOP

14L TSSOP

8-Pin PDIP

8L SOIC

-40°C–85°C

8L MSOP

14L TSSOP

Characteristics subject to change without notice. 19 of 20

REV 1.1.2 5/29/01

www.xicor.com

X5043/X5045

Part Mark Information

PDIP/SOIC

MSOP

YWW

X5043/45 X

X

Blank = 8-Lead SOIC

P= 8 Pin Plastic DIP

XXX

Blank = No sufﬁx, 0°C to +70°C

I = No Sufﬁx; –40°C to +85°C

A = -4,5A; 0°C to +70°C,

IA = -4.5A; –40°C to +85°C

F = -2.7; 0°C to +70°C

AEP/AEY = No Sufﬁx; –40°C to +85°C

AEN/AEW = -4.5A; –40°C to +85°C

AET/AFC = -2.7; –40°C to +85°C

AER/AFA = -2.7A; –40°C to +85°C

G = -2.7; –40°C to +85°C

FA = -2.7A; 0°C to +70°C

GA = -2.7A; –40°C to +85°C

X5043/X5045

TSSOP

V = 14 Lead TSSOP

X5043/45 W

X

Blank = 5V ±10%, 0°C to +70°C, V

= 4.25-4.5

TRIP

AL = 5V±10%, 0°C to +70°C, V

= 4.5-4.75

TRIP

I = 5V ±10%, –40°C to +85°C, V

= 4.25-4.5

TRIP

AM = 5V ±10%, –40°C to +85°C, V

= 4.5-4.75

TRIP

F = 2.7V to 5.5V, 0°C to +70°C, V

= 2.55-2.7

TRIP

AN = 2.7V to 5.5V, 0°C to +70°C, V

= 2.85-3.0

TRIP

G = 2.7V to 5.5V, –40°C to +85°C, V

= 2.55-2.7

TRIP

AP = 2.7V to 5.5V, –40°C to +85°C, V

= 2.85-3.0

TRIP

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemniﬁcation provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,

express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.

Xicor, Inc. makes no warranty of merchantability or ﬁtness for any purpose. Xicor, Inc. reserves the right to discontinue production and change speciﬁcations and prices

at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

COPYRIGHTS ANDTRADEMARKS

Xicor, Inc., the Xicor logo, E²POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,

E²KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are

used for identification purposes only, and are trademarks or registered trademarks of their respective holders.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;

4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;

5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection

and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signiﬁcant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

Characteristics subject to change without notice. 20 of 20

REV 1.1.2 5/29/01

www.xicor.com


型号：	X5045S8I
厂家：	XICOR INC.
描述：	CPU Supervisor with 4K SPI EEPROM CPU监控器， 4K SPI EEPROM 电源电路电源管理电路光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总20页 (文件大小：110K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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