X76F041W-3 [XICOR]
PASS TM SecureFlash; PASS TM SecureFlash
| 型号： | X76F041W-3 |
| 厂家： | 
XICOR INC. |
| 描述： | PASS TM SecureFlash |
| 文件： | 总21页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTE
A V A I L A B L E
AN83 • Development Tools XK76C
Password Access Security Supervisor
4K
4 x 128 x 8 Bit
X76F041
PASSTM SecureFlash
DESCRIPTION
FEATURES
• 64-Bit Password Security
• Three Password Modes
—Secure Read Access
The X76F041 is a password access security supervisor
device, containing four 128 x 8 bit SecureFlash arrays.
Access can be controlled by three 64-bit programmable
passwords, one for read operations, one for write opera-
tions and one for device configuration.
—Secure Write Access
—Secure Configuration Access
• Programmable Configuration
—Read, Write and Configuration Access
Passwords
—Multiple Array Access/Functionality
—Retry Register/Counter
• 8 Byte Sector Write
The X76F041 features a serial interface and software
protocol allowing operation on a simple two wire bus.The
bus signals are a clock input (SCL) and a bidirectional
data input and output (SDA). Access to the device is con-
trolled through a chip select input (CS), allowing any
number of devices to share the same bus.
• (4) 1K Memory Arrays
• ISO Response to Reset
• Low Power CMOS
—50µA Standby Current
—3mA Active Current
• 1.8V to 3.6V or 5V “Univolt” Read and Program
Power Supply Versions
The X76F041 also features a synchronous response to
reset; providing an automatic output of a pre-configured
32-bit data stream conforming to the ISO standard for
memory cards.
The X76F041 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
per sector and a minimum data retention of 100 years.
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100Years
—ESD Protection: 2000V on All Pins
FUNCTIONAL DIAGRAM
CHIP
ENABLE
CS
000–07F
080–0FF
100–17F
180–1FF
DATA
TRANSFER
RETRY
COUNTER
ARRAY ACCESS
ENABLE
SCL
INTERFACE
LOGIC
SDA
PASSWORD ARRAY AND
PASSWORD VERIFICATION
LOGIC
ISO RESET RESPONSE
DATA REGISTER
RST
CONFIGURATION
REGISTER
(4) 16 x 64
SECUREFLASH
ARRAYS
7002 ILL F01
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7002-2.2 4/30/97 T3/C0/D0 SH
Characteristics subject to change without notice
1
X76F041
PIN DESCRIPTION
PIN CONFIGURATION
Serial Data Input/Output (SDA)
DIP/SOIC
X76F041
SDA is a true three state serial data input/output pin.
During a read cycle, data is shifted out on this pin.
During a write cycle, data is shifted in on this pin. In all
other cases this pin is in a high impedance state.
V
1
2
3
4
8
7
6
5
V
CC
SS
RST
SCL
NC
CS
SDA
NC
Serial Clock (SCL)
The Serial Clock controls the serial bus timing for data
input and output.
Chip Select (CS)
7002 ILL F02
When CS is HIGH, the X76F041 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway the X76F041 will be in the
standby power mode. CS LOW enables the X76F041,
placing it in the active power mode.
Symbol
CS
Description
Chip Select Input
Reset (RST)
SDA
RST
Serial Data Input/Output
Reset Input
RST is a device reset pin. When RST is pulsed HIGH
while CS is LOW the X76F041 will output 32 bits of
fixed data which conforms to the ISO standard for
“synchronous response to reset”. CS must remain
LOW and the part must not be in a write cycle for the
response to reset to occur. If at any time during the
response to reset CS goes HIGH, the response to
reset will be aborted and the part will return to the
standby mode.
SCL
Serial Clock Input
Ground
V
SS
V
Supply Voltage
No Connect
CC
NC
7002 FRM T01
2
X76F041
DEVICE OPERATION
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
There are three primary modes of operation for the
X76F041; READ, WRITE and CONFIGURATION. The
READ and WRITE modes may be performed with or
without an 8-byte password. The CONFIGURATION
mode always requires an 8-byte password.
If the X76F041 is in a nonvolatile write cycle a “no ACK”
(SDA HIGH) response will be issued in response to load-
ing of the command + high order address byte. If a stop
condition is issued prior to the nonvolatile write cycle the
write operation will be terminated and the part will reset
and enter into a standby mode.
The basic method of communication is established by
first enabling the device (CS LOW), generating a start
condition and then transmitting a command and address
field followed by the correct password (if configured to
require a password). All parts will be shipped from the
factory in the non-password mode. The user must per-
form an ACK Polling routine to determine the validity of
the password and start the data transfer (see Acknowl-
edge Polling). Only after the correct password is
accepted and an ACK Polling has been performed can
the data transfer occur.
The basic sequence is illustrated in Figure 1.
After each transaction is completed, the X76F041 will
reset and enter into a standby mode.This will also be the
response if an attempt is made to access any limited
array.
Password Registers
The three passwords, Read, Write and Configuration
are stored in three 64 bit Write Only registers as illus-
trated in figure 2.
To ensure correct communication, RST must remain
LOW under all conditions except when initiating a
“Response to Reset sequence”.
Figure 2. Password Registers
Figure 1. X76F041 Device Operation
63
0
64 BIT WRITE PASSWORD
64 BIT READ PASSWORD
LOAD
COMMAND+HIGH ORDER ADDRESS
BYTE
LOAD
64 BIT CONFIGURATION PASSWORD
LOW ORDER ADDRESS / CONFIGURATION INSTRUCTION
BYTE
7002 ILL F04
LOAD 8–BYTE PASSWORD
(IF APPLICABLE)
Device Configuration
Five 8-Bit configuration registers are used to configure
the X76F041.These are shown in figure 3.
VERIFY PASSWORD ACCEPTANCE BY USE
OF ACK POLLING (IF APPLICABLE)
Figure 3. Configuration Registers
READ / WRITE
DATA BYTES
63
ACR1 ACR2 CR
0
RR
RC
RES
RES RES
7002 ILL F03
RESERVED
RETRY COUNTER
RETRY REGISTER
CONFIGURATION REGISTER
ARRAY CONTROL REGISTER 2
ARRAY CONTROL REGISTER 1
7002 ILL F04B
3
X76F041
Array Control
Access Bits
The four 1K arrays, are each programmable to different
levels of access and functionality. Each array can be pro-
grammed to require or not require the read/write pass-
words.The functional options are:
READ
PASSWORD
WRITE
PASSWORD
X
0
1
0
1
Y
0
0
1
1
NOT REQUIRED NOT REQUIRED
NOT REQUIRED REQUIRED
• Read and Write Access.
• Read access with all write operations locked out.
• Read access and program only (writing a “1” to a
“0”). If an attempt to change a “0” to a “1” occurs the
X76F041 will reset, issue a “no ACK” and enter the
standby power mode.
REQUIRED
REQUIRED
NOT REQUIRED
REQUIRED
7002 FRM T03
8-Bit Configuration Register
• No read or write access to the memory. Access only
through use of the configuration password.
MSB
LSB
UA1
UA2
1
0
RCR RCE
0
0
Array Map
RESERVED
RETRY COUNTER ENABLE
RETRY COUNTER RESET
RESERVED
RESERVED
UNAUTHORIZED ACCESS BIT 2
UNAUTHORIZED ACCESS BIT 1
First ‘1k’
Addresses 000
07F (hex)
0FF (hex)
17F (hex)
1FF (hex)
Second ‘1k’ Addresses 080
High-order
Addresses
7002 ILL F06
Third ‘1k’
Addresses 100
Addresses 180
Fourth ‘1k’
Unauthorized Access Bits (UA1, UA2):
1 0
7002 ILL F04A
Access is forbidden if retry register equals the retry
counter (provided that the retry counter is enabled) and
no further access of any kind will be allowed.
8 Bit Array Control Register 1
SECOND 1K
FIRST 1K
0 1, 0 0, 1 1
X2
Y2
Z2
T2
X1
Y1
Z1
T1
Only configuration operations are allowed if the retry reg-
ister equals the retry counter (provided that the retry
counter is enabled).
ACCESS
MSB
FUNCTION
ACCESS
FUNCTION
LSB
7002 ILL F05A
Retry Counter Reset Bit (RCR):
If the retry counter reset bit is a “1” then the retry counter
will be reset following a correct password, provided the
retry counter is enabled.
8 Bit Array Control Register 2
UPPER 1K
THIRD 1K
X4
Y4
Z4
T4
X3
Y3
Z3
T3
If the retry counter reset bit is a “0” then the retry counter
will not be reset following a correct password, provided
the retry counter is enabled.
ACCESS
MSB
FUNCTION
ACCESS
FUNCTION
LSB
7002 ILL F05B
Retry Counter Enable Bit (RCE):
If the Retry counter enable bit is a “1”, then the retry
counter is enabled. An initial comparison between the
retry register and retry counter determines whether the
number of allowed incorrect password attempts has
been reached. If not, the protocol continues and in case
of a wrong password, the retry counter is incremented by
one. If the password is correct then the retry counter will
either be reset or unchanged, depending on the reset bit.
Functional Bits
Z
0
1
T
0
0
FUNCTIONALITY
READ AND WRITE UNLIMITED
READ ONLY, WRITE LIMITED
PROGRAM & READ ONLY,
ERASE LIMITED
0
1
1
1
NO READ OR WRITE, FULLY
LIMITED
7002 FRM T02
4
X76F041
The retry register must have a higher value than the retry
counter for correct device operation. If the retry counter
value is larger than the retry register and the retry
counter is enabled, the device will wrap around allowing
up to an additional 255 incorrect access attempts.
DEVICE PROTOCOL
The X76F041 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device as
the receiver. The device controlling the transfer is a mas-
ter and the device being controlled is the slave.The mas-
ter will always initiate data transfers, and provide the
clock for both transmit and receive operations. Therefore,
the X76F041 will be considered a slave in all applica-
tions.
If the Retry counter enable bit is a “0”, then the retry
counter is disabled.
Retry Register/Counter
Both the retry register and retry counter are accessible in
the configuration mode and may be programmed with a
value of 0 to 255.
Start Condition
All commands except for response to reset are preceded
by the start condition, which is a HIGH to LOW transition
of SDA when SCL is HIGH. The X76F041 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condition
has been met.
The difference between the retry register and the retry
counter is the number of access attempts allowed, there-
fore the retry counter must be programmed to a smaller
value than the retry register to prevent wrap around.
Figure 4. Data Validity During Write
SCL
SDA
DATA STABLE DATA
CHANGE
7002 ILL F07
Figure 5. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
7002 ILL F08
NOTE: The part requires the SCL input to be LOW during non-active periods of operation. In other words, the SCL will need to be LOW prior to
any START condition and LOW after a STOP condition.This is also reflected in the timing diagram.
5
X76F041
Stop Condition
Acknowledge
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when
SCL is HIGH. A stop condition can only be issued after
the transmitting device has released the bus.
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.
OPERATIONAL MODES
THE FIRST BYTE
IN THE PROTOCOL
THE SECOND BYTE
IN THE PROTOCOL
COMMAND DESCRIPTION
Write (Sector)
PASSWORD USED:
Write
0 0 0XXXXA
0 0 1XXXXA
0 1 0XXXXA
0 1 1XXXXA
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
1 0 0XXXXX
All the rest
Write address
Read address
Write address
Read address
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 0 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
Read (Random / Sequential)
Write (Sector)
Read
Configuration
Configuration
Write
Read (Random / Sequential)
Program write-password
Program read-password
Program configuration-password
Reset write password (all 0’s)
Reset read password (all 0’s)
Program configuration registers
Read configuration registers
Mass program
Read
Configuration
Configuration
Configuration
Configuration
Configuration
Configuration
Configuration
Mass erase
Reserved
7002 FRM T04
6
X76F041
WRITE OPERATION
Sector Write
ure 6. Eight bytes must be transferred. After the last byte
to be transferred is acknowledged, a stop condition is
issued, which starts the nonvolatile write cycle. If more
than 8 bytes are transferred the data will wrap around
and previous data will be overwritten. All data will be writ-
The Sector Write mode requires issuing the 3-bit write
command followed by the address, password if required
and then the data bytes transferred as illustrated in Fig-
ten to the same sector as defined by A –A .
8
3
Figure 6. Sector Write
S
T
A
R
T
WRITE
PASSWORD 7
WRITE
PASSWORD 0
C M D A A A A A A A A A A A A A
X X X X 8 7 6 5 4 3 2 1 0
WAIT
/ACK POLLING
SDA LINE
S
t
WC
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
DATA 0
DATA 1
DATA 2
DATA 7
WAIT
IF PASSWORD
MATCH THEN
t
WC
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
7002 ILL F10.1
7
X76F041
ACK Polling
After a password sequence, there is always a nonvolatile
write cycle. In order to continue the transaction, the
X76F041 requires the master to perform an ACK polling
with the specific code of C0h. As with regular acknowl-
edge polling the user can either time out for 10ms, and
then issue the ACK polling once, or continuously loop as
described in the flow.
Once a stop condition is issued to indicate the end of the
host’s write sequence, the X76F041 initiates the internal
nonvolatile write cycle. In order to take advantage of the
typical 5ms write cycle, ACK polling can be initiated
immediately. This involves issuing the Start condition fol-
lowed by the new command code of eight bits (1st byte of
the protocol). If the X76F041 is still busy with the nonvol-
atile write operation, it will issue a “no ACK” in response.
If the nonvolatile write operation has completed, an
“ACK” will be returned and the host can then proceed
with the rest of the protocol. Refer to the following flow:
As with regular acknowledge polling, if the user chooses
to loop, then as long as the nonvolatile write cycle is
active, a no ACK will be issued in response to each poll-
ing cycle.
If the password that was inserted was correct, then an
“ACK” will be returned once the nonvolatile write cycle is
over, in response to the ACK polling cycle immediately
following it.
ACK Polling Sequence
WRITE SEQUENCE
COMPLETED
ENTER ACK POLLING
If the password that was inserted was incorrect, then a
“no ACK” will be returned even if the nonvolatile write
cycle is over. Therefore, the user cannot be certain that
the password is incorrect until the 10ms write cycle time
has elapsed.
ISSUE
A START
ISSUE NEW
COMMAND CODE
(1ST BYTE)
ACK
RETURNED
NO ACK (SDA HIGH)
YES (SDA LOW)
PROCEED
7002 ILL F12A
Figure 7. Acknowledge Polling
8th clk.
of 8th
pwd. byte
‘ACK’
clk
8th
clk
ACK
clk
SCL
8th
bit
SDA
‘ACK’
START
condition
ACK or
no ACK
7002 ILL F11
8
X76F041
READ OPERATION
This is followed by the eight byte read password
sequence which includes the 10ms wait time and the
password acknowledge polling sequence. If the pass-
word is accepted an “ACK” will be returned followed by
eight bits of “secure read setup” which is to be ignored. At
this point a START is issued followed by the address and
data to be read within the original 1K block. See figure 8.
Once the first byte has been read, another start can be
issued followed by a new 8-bit address. Random reads
are allowed only within the original 1K-bit block. To
access another 1K-bit block, a stop must be issued fol-
lowed by a new command/block address/password
sequence.
Random Read with Password
Random read with password operations are initiated
with a START command followed by the read command
and the address of the first byte of the block in which data
is to be read:
Block 0 = 000h
Block 1 = 080h
Block 2 = 100h
Block 3 = 180h
Figure 8. Random Read with Password
FIRST BYTE
BLOCK ADDRESS
S
T
A
R
T
READ
PASSWORD 7
READ
PASSWORD 0
A A A A A A A A
7 6 5 4 3 2 1 0
C M D A A A A A
X X X X 8
WAIT
/ACK POLLIN
SDA LINE
S
t
WC
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
A
R
T
S
T
A
R
T
S
T
O
P
SECURE
READ SETUP
A A A A A A A A
7 6 5 4 3 2 1 0
DATA 0
A A A A A A A A
7 6 5 4 3 2 1 0
DATA 1
IF PASSWORD
MATCH THEN
S
S
S
X X X X X X X X
A
C
K
A
C
K
A
C
K
7002 ILL F13
9
X76F041
Random Read without Password
Sequential Read
Random read operations without a password do not
require the first byte block initiation address.To perform a
random read without password, a START is followed by
the read command plus address location of the byte to
be read.This is followed by an “ACK” and the eight bits of
data to be read. Other bytes within the same 1K-bit block
may be read by issuing another START followed by a
new 8-bit address as shown in figure 9.
Once past the password acceptance sequence (when
required) and “secure read setup”, the host can read
sequentially within the originally addressed 1K-bit array.
The data output is sequential, with the data from address
n followed by the data from address n+1. The address
counter for read operations increments the address,
allowing the 1K memory contents to be serially read dur-
ing one operation. At the end of the address space
(address 127), the counter “rolls over” to address space 0
within the 1K Block and the X76F041 continues to output
data for each acknowledge received. Refer to figure 10
for the address, acknowledge and data transfer
sequence. An acknowledge must follow each 8-bit data
transfer. After the last bit has been read, a stop condition
is generated without a preceding acknowledge.
Figure 9. Random Read without Password
S
S
T
A
T
A
R
T
S
T
O
P
C M D A A A A A A A A A A A A A
R
DATA 0
A A A A A A A A
7 6 5 4 3 2 1 0
DATA 1
X X X X 8 7 6 5 4 3 2 1 0
T
S
S
S
SDA LINE
A
C
K
A
C
K
A
C
K
7002 ILL F13A.2
Figure 10. Sequential Read with Password
FIRST BYTE
S
T
A
R
T
BLOCK ADDRESS
READ
PASSWORD 7
READ
PASSWORD 0
C M D A A A A A A A A A A A A A
X X X X 8 7 6 5 4 3 2 1 0
WAIT
SDA LINE
S
t
/ACK POLLING
WC
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
A
R
T
S
T
O
P
SECURE
READ SETUP
A A A A A A A A
7 6 5 4 3 2 1 0
DATA 0
DATA 1
DATA X
IF PASSWORD
MATCH THEN
X X X X X X X X S
S
A
C
K
A
C
K
A
C
K
7002 ILL F12.3
10
X76F041
CONFIGURATION OPERATIONS
Configuration Read/Write
Configuration read/write allows access to all of the non-
volatile memory arrays regardless of the contents of the
configuration registers. Access includes sector writes,
random and sequential reads using the same format as
normal reads and writes.
Configuration commands generally require the configu-
ration password. The exception is that programming a
new read/write password requires the old read/write
password and not the configuration password. In most
cases these operations will be performed by the equip-
ment manufacturer or end distributor of the equipment or
card.
In general, the configuration read/write operation enables
access to any memory location that may otherwise be
limited. The configuration password, in this sense, is like
a master key that can override the limits caused by the
control partitioning of the arrays.
Figure 11. Configuration Write
S
T
A
R
T
CONFIGURATION
PASSWORD 7
CONFIGURATION
PASSWORD 0
C M D A A A A A A A A A A A A A
X X X X 8 7 6 5 4 3 2 1 0
WAIT
SDA LINE
S
t
/ACK POLLING
WC
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
DATA 0
DATA 1
DATA 2
DATA X
WAIT
IF PASSWORD
MATCH THEN
t
WC
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
7002 ILL F14.1
Figure 12. Configuration Sequential Read
FIRST BYTE
S
T
A
R
T
BLOCK ADDRESS
CONFIGURATION
PASSWORD 7
CONFIGURATION
PASSWORD 0
C M D A A A A A A A A A A A A A
X X X X 8 7 6 5 4 3 2 1 0
WAIT
SDA LINE
S
t
/ACK POLLING
WC
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
A
R
T
S
T
O
P
SECURE
READ SETUP
A A A A A A A A
7 6 5 4 3 2 1 0
DATA 0
DATA 1
DATA X
IF PASSWORD
MATCH THEN
S
X X X X X X X X
S
A
C
K
A
C
K
A
C
K
7002 ILL F15.3
11
X76F041
Configuration of Passwords
Program Configuration Registers
The sequence in figure 14 will change (program) the
write, read and configuration passwords. The program-
ming of passwords is done twice prior to the nonvolatile
write cycle in order to verify that the new password is
consistent. After the eight bytes are entered in the sec-
ond pass, a comparison takes place. A mismatch will
cause the part to reset and enter into the standby mode
and a “no ACK” will be issued.
This mode allows programming of the five configuration/
control registers using the configuration password. The
retry counter must be programmed with a value less than
the retry register. If it is programmed with a value larger
than the retry register there will be a wrap around.
Read Configuration Registers
This mode allows reading of the 5 configuration/control
registers with the configuration password. It may be use-
ful for monitoring purposes.
There is no way to read the Read/Write/Configuration
passwords.
Figure 13. Configuration Random Read
FIRST BYTE
S
BLOCK ADDRESS
T
A
CONFIGURATION
PASSWORD 7
CONFIGURATION
PASSWORD 0
A A A A A A A A
7 6 5 4 3 2 1 0
C M D A A A A A
X X X X 8
R
T
WAIT
/ACK POLLING
SDA LINE
S
t
WC
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
S
T
A
R
T
T
A
R
T
S
SECURE
READ SETUP
T
O
P
DATA 0
DATA 1
A A A A A A A A
7 6 5 4 3 2 1 0
A A A A A A A A
7 6 5 4 3 2 1 0
IF PASSWORD
MATCH THEN
S
S
X X X X X X X X S
A
C
K
A
C
K
A
C
K
7002 ILL F16.3
Figure 14. Program Passwords
S
T
A
READ/WRITE/
CONFIGURATION
INSTRUCTION
OLD
PASSWORD 7
OLD
PASSWORD 0
C M D A A A A A
R
X X X X 8
T
WAIT
/ACK POLLING
SDA LINE
S
t
WC
A
C
K
A
C
K
A
A
C
K
C
K
S
T
NEW
PASSWORD 7
NEW
NEW
NEW
PASSWORD 0
PASSWORD 0
PASSWORD 7
O
P
IF PASSWORD
MATCH THEN
WAIT
t
WC
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
7002 ILL F17.1
12
X76F041
Read Password Reset
Mass Program
This mode allows resetting of the READ password to all
“0”s in case re-programming is needed and the old pass-
word is not known.
This mode allows mass programming of the array, con-
figuration registers and password to all “0”s using a spe-
cial configuration command. All parts are shipped mass
programmed.
Write Password Reset
Mass Erase
This mode allows resetting of the WRITE password to all
“0”s in case re-programming is needed and the old pass-
word is not known.
This mode allows mass erase of the array, configuration
register and password to all “1”s using a special configu-
ration command.
Figure 15. Program Configuration Registers
S
T
A
R
T
CONFIGURATION CONFIGURATION
CONFIGURATION
PASSWORD 0
INSTRUCTION
PASSWORD 7
C M D A A A A A
X X X X 8
WAIT
SDA LINE
S
t
/ACK POLLING
WC
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
BCR 1
BYTE
BCR 2
BYTE
CR
BYTE
RR
BYTE
RC
BYTE
T
O
P
IF PASSWORD
MATCH THEN
WAIT
t
S WC
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
7002 ILL F18.1
Figure 16. Read Configuration Registers
S
T
A
R
T
CONFIGURATION CONFIGURATION
CONFIGURATION
PASSWORD 0
C M D A A A A A
X X X X 8
INSTRUCTION
PASSWORD 7
WAIT
SDA LINE
S
t
/ACK POLLING
WC
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
BCR 1
BYTE
BCR 2
BYTE
CR
BYTE
RR
BYTE
RC
BYTE
IF PASSWORD
MATCH THEN
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
7002 ILL F19.1
13
X76F041
Figure 17. Read/Write Password Reset
WAIT
t
/ACK POLLING
WC
S
T
A
R
T
S
T
O
P
CONFIGURATION CONFIGURATION
INSTRUCTION PASSWORD 7
CONFIGURATION
PASSWORD 0
C M D A A A A A
X X X X 8
WAIT
SDA LINE
S
S
t
WC
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
7002 ILL F20.1
Figure 18. Mass Program/Erase
WAIT
/ACK POLLING
t
WC
S
T
A
S
CONFIGURATION CONFIGURATION
INSTRUCTION PASSWORD 7
CONFIGURATION
PASSWORD 0
T
O
P
C M D A A A A A
R
X X X X 8
T
WAIT
SDA LINE
S
S
t
WC
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
7002 ILL F20A.1
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias ..................... –65°Cto+135°C
Storage Temperature .......................... –65°Cto+150°C
Voltage on any Pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Respect to V .....................................–1V to +7V
SS
D.C. Output Current ................................................. 5mA
Lead Temperature
(Soldering, 10 seconds) .................................300°C
14
X76F041
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Extended
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
X76F041
Limits
4.5V to 5.5V
3V to 3.6V
–20°C
X76F041 – 3
7002 FRM T05
7002 FRM T06.1
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
= V x 0.1/V x 0.9 Levels @ 1MHz,
f
SCL
CC
CC
I
V
V
Supply Current (Read)
SDA = Open
RST = CS = V
2
mA
CC1
CC
SS
f
= V x 0.1/V x 0.9 Levels @ 1MHz,
CC CC
SCL
(3)
Supply Current (Write)
SDA = Open
RST = CS = V
I
3
mA
CC
CC2
SS
SCL = V , CS = V
– 0.3V
SS
CC
(1)
V
V
Supply Current (Standby)
Supply Current (Standby)
I
100
50
µA
µA
CC
SB1
SDA = Open, RST = V = 5.5V
CC
SCL = V , CS = V
– 0.3V
SS
CC
(1)
SB2
I
CC
SDA = Open, RST = V , V
= 3V
SS CC
I
V
V
V
= V to V
SS CC
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
LI
IN
I
= V to V
SS CC
LO
OUT
(2)
V
V
x 0.3
= 5.5V
= 5.5V
= 3.0V
= 3.0V
–0.5
CC
CC
CC
CC
CC
CC
CC
CC
IL1
(2)
V
V
x 0.7 V
V
–0.5
+ 0.5
x 0.1
+ 0.5
V
V
V
I
Input HIGH Voltage
V
V
CC
IH1
(2)
V
Input LOW Voltage
IL2
(2)
V
V
V
x 0.9 V
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
V
V
CC
IH2
V
= 2mA
0.4
OL
OL
V
– 0.8
I
= –1mA
OH
CC
OH
7002 FRM T07.1
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Test
Output Capacitance (SDA)
Input Capacitance (RST, SCL, CS)
Max.
Units
Conditions
(3)
OUT
V
= 0V
= 0V
C
10
pF
pF
I/O
(3)
C
V
10
IN
IN
7002 FRM T08
NOTES: (1) Must perform a stop command after a read command prior to measurement
(2) min. and V max. are for reference only and are not tested.
V
IL
IH
(3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
V
x 0.1 to V x 0.9
CC
Input Pulse Levels
CC
5V
3V
Input Rise and Fall Times
Input and Output Timing Level
Output Load
10ns
2.3KΩ
1.3KΩ
V
x 0.5
CC
OUTPUT
OUTPUT
100pF
100pF
100pF
7002 FRM T09
7002 ILL F21.1
15
X76F041
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Read & Write Cycle Limits
Symbol
Parameter
Min.
Max.
1
Units
MHz
ns
f
SCL Clock Frequency
SCL
TI
Noise Suppression Time Constant at SCL & SDA Inputs
SCL HIGH to SDA Data Valid
20
t
t
t
t
t
t
t
t
t
t
t
t
t
450
ns
DV
Clock LOW Period
500
500
150
150
50
ns
LOW
Clock HIGH Period
ns
HIGH
Start Condition Setup Time to Rising Edge of SCL
Start Condition Setup Time to Falling Edge of SCL
Start Condition Hold Time to Rising Edge of SCL
Start Condition Hold Time to Falling Edge of SCL
Stop Condition Setup Time to Rising Edge of SCL
Stop Condition Setup Time to Falling Edge of SCL
Stop Condition Hold Time to Rising Edge of SCL
Stop Condition Hold Time to Falling Edge of SCL
Data in Hold Time
ns
STAS1
STAS2
STAH1
STAH2
STPS1
STPS2
STPH1
STPH2
HD:DAT
SU:DAT
ns
ns
50
ns
150
150
50
ns
ns
ns
50
ns
10
ns
Data in Setup Time
150
ns
(4)
t
t
t
SCL Rise Time
90
90
90
90
ns
ns
ns
RSCL
(4)
SCL Fall Time
FSCL
(4)
R
SDA, CS, RST Rise Time
SDA, CS, RST Fall Time
Data Out Hold Time
(4)
F
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
ns
ns
0
DH
SCL LOW to High Impedance
SCL HIGH to Output Active
150
ns
HZ1
0
ns
LZ
V
to CS Setup Time
5
ms
ns
VCCS
SU:CS
HD:CS
HZ2
CC
CS Setup Time
200
100
CS Hold Time
ns
CS Deselect Time
150
ns
SCL Setup Time to CS LOW after Power Up
RST HIGH Time
200
1500
500
ns
SU:SCL
RST
ns
RST Setup Time
ns
SU:RST
SCL:RST
LOW:RST
HIGH:RST
PD
SCL Frequency During Response to Reset
SCL LOW Time During Response to Reset
SCL HIGH Time During Response to Reset
SCL LOW to SDA Valid During Response to Reset
RST to SCL Non-Overlap
1
MHz
ns
500
500
ns
450
10
ns
500
ns
NOL
Nonvolatile Write Cycle
ms
WC
7002 FRM T10
NOTES: (4) This parameter is periodically sampled and not 100% tested.
16
X76F041
Bus Timing(1) — SDA Driven by the Bus Master
t
t
FSCL
RSCL
t
t
LOW
HIGH
SCL
t
t
F
R
t
t
SU:DAT
HD:DAT
SDA (IN)
from master
Start
bit
7002 ILL F22
Bus Timing(2) — SDA Driven by the Slave
1st clock
pulse of
sequence
last clock
pulse of
sequence
SCL
t
t
DV
DH
SDA (OUT)
from slave
t
LZ
t
HZ1
7002 ILL F23
START Condition Timing
SCL
t
t
t
STAH2
STAS1
STAH1
t
STAS2
SDA (IN)
from master
Start Bit
7002 ILL F24
NOTES: (1) The master may issue a STOP condition at any given time in which it is driving the SDA line. In other words, when the part is sending
ACK or data the master may NOT issue a STOP condition. The part will not respond to any such attempt which also causes bus con-
tention. At any other time, a STOP condition will cause the part to reset and stop (enter a stand-by mode). Write operations will termi-
nate prior to entering the stand-by mode.
(2) When the part drives the SDA line, it will tri-state the bus only after the last bit of the sequence. In other words, after the 8th bit of a byte
that is read or after ACK between incoming bytes. In all other cases when the part drives the bus (between successive bits) it will con-
tinue to drive the bus also during the clock LOW periods.
17
X76F041
STOP Condition Timing
SCL
t
t
t
STPH2
STPS1
STPH1
t
STPS2
SDA (IN)
from master
Stop Bit
7002 ILL F25
Acknowledge Response from Slave (Same Timing as Data Out)
SCL
t
t
DV
SDA (OUT)
from slave
(acknowledge)
DH
t
t
LZ
HZ1
7002 ILL F26
Acknowledge Response from Master
SCL
t
SU:DAT
t
HD:DAT
SDA (OUT)
from master
(acknowledge)
7002 ILL F27
CS Timing Diagram (Selecting/Deselecting the Part)
SCL
t
t
SU:CS
HD:CS
CS
from
master
7002 ILL F28
18
X76F041
V
to CS Setup Timing Diagram
CC
V
VCC
CCMIN
t
VCCS
CS
t
SU:SCL
t
SU:CS
SCL
7002 ILL F29
CS Deselect
CS
t
HZ2
SDA (OUT)
from slave
7002 ILL F29A
RST Timing Diagram — Response to a Synchronous Reset (ISO)
RST
t
RST
f
SCL_RST
t
t
NOL
HIGH_RST
1st
clk.
2nd
clk.
3rd
clk.
SCL
SDA
CS
pulse
pulse
pulse
t
LOW_RST
t
SU:RST
t
t
PD
PD
1st DATA BIT
2nd DATA BIT
(low)
7002 ILL F30
NOTES: (1) The reset operation results in an answer from the part containing a header transmitted from the part to the master. The header has a
fixed length of 32 bits and begins with two mandatory fields of eight bits : H1 and H2.
(2) The chronological order of transmission of the information bits shall correspond to bit identification b1 to b32 with the LEAST
significant bit transmitted first.
(3) The current values are:
H1 : 19 h
H2 : 55 h
H3 : AA h
H4 : 55 h
19
X76F041
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
8-LEAD PLASTIC, 0.200” WIDE SMALL OUTLINE
GULLWING PACKAGE TYP “A” (EIAJ SOIC)
0.020 (.508)
0.012 (.305)
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
.213 (5.41)
.205 (5.21)
.330 (8.38)
.300 (7.62)
PIN 1 INDEX
PIN 1
PIN 1 ID
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
.050 (1.27) BSC
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
.212 (5.38)
.203 (5.16)
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
.080 (2.03)
.070 (1.78)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
.013 (.330)
.004 (.102)
0
8
0.325 (8.25)
0.300 (7.62)
REF
0.015 (0.38)
MAX.
.010 (.254)
.007 (.178)
.035 (.889)
.020 (.508)
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 ILL F33.1
3926 FHD F01
20
X76F041
ORDERING INFORMATION
X76F041
X
X
–X
Device
V
Limits
CC
Blank = 5V ±10%
3 = 3V to 3.6V
Temperature Range
Blank = Commercial = 0°C to +70°C
E = Extended = –20°C to +85°C
Package
P = 8-Lead Plastic DIP
A = 8-Lead SOIC (EIAJ)
H = Die in Waffle Packs
W = Die in Wafer Form
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detec-
tion and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure
to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life sup-
port device or system, or to affect its safety or effectiveness.
21
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