X76F100S8-3 [XICOR]
Flash, 128X8, PDSO8, PLASTIC, SOIC-8;
| 型号： | X76F100S8-3 |
| 厂家： | 
XICOR INC. |
| 描述： | Flash, 128X8, PDSO8, PLASTIC, SOIC-8 时钟 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1K
128 x 8 Bit
X76F100
Secure SerialFlash
FEATURES
DESCRIPTION
• 64-bit password security
• One array (112-bytes) two passwords (16-bytes)
—Read password
—Write password
• Programmable passwords
• Retry counter register
—Allows 8 tries before clearing of the array
• 32-bit response to reset (rst input)
• 8-byte sector Write Mode
• 1MHz clock rate
• 2-wire serial interface
• Low power CMOS
The X76F100 is a Password Access Security Supervi-
sor, containing one 896-bit Secure SerialFlash array.
Access to the memory array can be controlled by two
64-bit passwords. These passwords protect read and
write operations of the memory array.
The X76F100 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same bus.
—3.0 to 5.5V operation
The X76F100 also features a synchronous response
to reset providing an automatic output of a hard-wired
32-bit data stream conforming to the industry standard
for memory cards.
—Standby current less than 1µA
—Active current less than 3 mA
• High reliability endurance:
—100,000 write cycles
• Data retention: 100 years
• Available in:
The X76F100 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
—8-lead PDIP, SOIC, MSOP, and smart car module
BLOCK DIAGRAM
CS
Chip Enable
Data Transfer
8K Byte
SerialFlash Array
Array 0
SCL
SDA
(Password Protected)
Array Access
Enable
Interface
Logic
32 Byte
SerialFlash Array
Array 1
Password Array
and Password
(Password Protected)
Verification Logic
RST
Retry Counter
Reset
Response Register
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X76F100
PIN DESCRIPTIONS
Serial Clock (SCL)
To ensure the correct communication, RST must
remain LOW under all conditions except when running
a “Response to Reset sequence”.
The SCL input is used to clock all data into and out of
the device.
Data is transferred in 8-bit segments, with each trans-
fer being followed by an ACK, generated by the receiv-
ing device.
Serial Data (SDA)
If the X76F100 is in a nonvolatile write cycle a “no
ACK” (SDA=High) response will be issued in response
to loading of the command byte. If a stop is issued prior
to the nonvolatile write cycle the write operation will be
terminated and the part will reset and enter into a
standby mode.
SDA is an open drain serial data input/output pin. Dur-
ing a read cycle, data is shifted out on this pin. During
a write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
Chip Select (CS)
When CS is high, the X76F100 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway, the X76F100 will be in
standby mode. CS low enables the X76F100, placing it
in the active mode.
The basic sequence is illustrated in Figure 1.
PIN NAMES
Symbol
CS
Description
Chip Select Input
Reset (RST)
SDA
SCL
Serial Data Input/Output
Serial Clock Input
Reset Input
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F100 will output 32 bits of fixed
data which conforms to the standard for “synchronous
response to reset”. CS must remain LOW and the part
must not be in a write cycle for the response to reset to
occur. See Figure 7. If at any time during the response
to reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state.
The response to reset is “mask programmable” only!
RST
V
Supply Voltage
Ground
CC
V
SS
NC
No Connect
PIN CONFIGURATION
Smart Card
PDIP
DEVICE OPERATION
RST
SCL
SDA
CS
V
CC
1
2
8
7
6
5
The X76F100 memory array consists of fourteen
8-byte sectors. Read or write access to the array
always begins at the first address of the sector. Read
operations then can continue indefinitely. Write opera-
tions must total 8-bytes.
NC
NC
3
4
V
SS
SOIC
There are two primary modes of operation for the
X76F100; Protected READ and protected WRITE. Pro-
tected operations must be performed with one of two 8-
byte passwords.
V
V
CC
SS
1
8
V
GND
CC
RST
CS
SDA
NC
2
7
6
5
SCL
NC
RST
CS
3
4
The basic method of communication for the device is
established by first enabling the device (CS LOW),
generating a start condition, then transmitting a com-
mand, followed by the correct password. All parts will
be shipped from the factory with all passwords equal to
‘0’. The user must perform ACK Polling to determine
the validity of the password, before starting a data
transfer (see Acknowledge Polling.) Only after the cor-
rect password is accepted and a ACK polling has been
performed, can the data transfer occur.
SCL
NC
SDA
NC
MSOP
V
V
CC
SS
1
8
NC
NC
2
7
6
5
RST
SCL
CS
3
4
SDA
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X76F100
After each transaction is completed, the X76F100 will
reset and enter into a standby mode. This will also be
the response if an unsuccessful attempt is made to
access a protected array.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figure 2 and Figure 3.
Figure 1. X76F100 Device Operation
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F100 continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition is met.
Load Command/Address Byte
Load 8-Byte
Password
A start may be issued to terminate the input of a con-
trol byte or the input data to be written. This will reset
the device and leave it ready to begin a new read or
write command. Because of the push/pull output, a
start cannot be generated while the part is outputting
data. Starts are inhibited while a write is in progress.
Verify Password
Acceptance by
Use of Ack Polling
Stop Condition
Read/Write
Data
All communications must be terminated by a stop con-
dition. The stop condition is a LOW to HIGH transition
of SDA when SCL is HIGH. The stop condition is also
used to reset the device during a command or data
input sequence and will leave the device in the standby
power mode. As with starts, stops are inhibited when
outputting data and while a write is in progress.
Bytes
Retry Counter
The X76F100 contains a retry counter. The retry
counter allows 8 accesses with an invalid password
before any action is taken. The counter will increment
with any combination of incorrect passwords. If the
retry counter overflows, the memory area and both of
the passwords are cleared to “0”. If a correct password
is received prior to retry counter overflow, the retry
counter is reset and access is granted.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.
Device Protocol
The X76F100 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as a receiver. The device controlling the transfer
is a master and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive opera-
tions. Therefore, the X76F100 will be considered a
slave in all applications.
The X76F100 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F100 will respond with an acknowl-
edge after the receipt of each subsequent eight-bit
word.
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X76F100
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
Start Condition
Stop Condition
Table 1. X76F100 Instruction Set
Command after Start
1 0 0 S S S S 0
Command Description
Sector Write
Password Used
Write
3
2
1
0
1 0 0 S S S S 1
Sector Read
Read
3
2
1
0
1 1 1 1 1 1 0 0
1 1 1 1 1 1 1 0
0 1 0 1 0 1 0 1
Change Write Password
Change Read Password
Password ACK Command
Write
Write
None
Illegal command codes will be disregarded. The part
will respond with a “no-ACK” to the illegal byte and
then return to the standby mode. All write/read opera-
tions require a password.
ACK Polling
Once a stop condition is issued to indicate the end of
the host’s write sequence, the X76F100 initiates the
internal nonvolatile write cycle. In order to take advan-
tage of the typical 5ms write cycle, ACK polling can
begin immediately. This involves issuing the start con-
dition followed by the new command code of 8-bits (1st
byte of the protocol.) If the X76F100 is still busy with
the nonvolatile write operation, it will issue a “no-ACK”
in response. If the nonvolatile write operation has com-
pleted, an “ACK” will be returned and the host can then
proceed with the rest of the protocol.
PROGRAM OPERATIONS
Sector Write
The sector write mode requires issuing the 8-bit write
command followed by the password and then the data
bytes transferred as illustrated in Figure 4. The write
command byte contains the address of the sector to be
written. Data is written starting at the first address of a
sector and eight bytes must be transferred. After the
last byte to be transferred is acknowledged a stop con-
dition is issued which starts the nonvolatile write cycle.
If more or less than 8-bytes are transferred, the data in
the sector remains unchanged.
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X76F100
Data ACK Polling Sequence
Password ACK Polling Sequence
Write Sequence
Completed
Password Load
Completed
Enter ACK Polling
Enter ACK Polling
Issue START
Issue START
Issue New
Command Code
Issue Password
ACK Command
NO
ACK
ACK
NO
returned?
returned?
YES
YES
PROCEED
PROCEED
After the password sequence, there is always a nonvol-
atile write cycle. This is done to discourage random
guesses of the password if the device is being tam-
pered with. In order to continue the transaction, the
X76F100 requires the master to perform a password
ACK polling sequence with the specific command code
of 55h. As with regular Acknowledge polling the user
can either time out for 10ms, and then issue the ACK
polling once, or continuously loop as described in the
flow.
READ OPERATIONS
Read operations are initiated in the same manner as
write operations but with a different command code.
Sector Read
With sector read, a sector address is supplied with the
read command. Once the password has been acknowl-
edged data may be read from the sector. An acknowl-
edge must follow each 8-bit data transfer. A read
operation always begins at the first byte in the sector,
but may stop at any time. Random accesses to the
array are not possible. Continuous reading from the
array will return data from successive sectors. After
reading the last sector in the array, the address is auto-
matically set to the first sector in the array and data can
continue to be read out. After the last bit has been
read, a stop condition is generated without sending a
preceding acknowledge.
If the password that was inserted was correct, then an
“ACK” will be returned once the nonvolatile cycle in
response to the password ACK polling sequence is
over.
If the password that was inserted was incorrect, then a
“no ACK” will be returned even if the nonvolatile cycle is
over. Therefore, the user cannot be certain that the
password is incorrect until the 10ms write cycle time
has elapsed.
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X76F100
Figure 4. Sector Write Sequence (Password Required)
Write
Password
7
Write
Password
0
Host
Commands
Write
Command
Wait t
WC
OR
Password
SDA
S
X76F100
ACK
Response
Command
If ACK, Then
Password Matches
Host
Commands
Password ACK
Command
Wait t
WC
P
S
Data ACK Polling
X76F100
Responce
Figure 5. Acknowledge Polling
SCL
8th CLK
of 8th
Pwd. Byte
8th
CLK
‘ACK’
CLK
‘ACK’
CLK
SDA
8th Bit
‘ACK’
Start
Condition
ACK or
no ACK
Figure 6. Sector Read Sequence (Password Required)
Read
Password
7
Read
Password
0
Host
Commands
Read
Command
Wait t
WC
OR
Password
ACK
Command
SDA
S
X76F100
Response
If ACK, Then
Password Matches
Host
Commands
Password ACK
Command
P
S
Data n
Data 0
X76F100
Response
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X76F100
PASSWORDS
After initiating a nonvolatile write cycle the RST pin
must not be pulsed until the nonvolatile write cycle is
complete. If not, the ISO response will not be acti-
vated. Also, any attempt to pulse the RST pin in the
middle of an ISO transaction will stop the transaction
with the SDA pin in high impedance. The user will have
to issue a stop condition and start the transaction
again. If at any time during the Response to Reset CS
goes HIGH, the response to reset will be aborted and
the part will return to the standby state. A Response to
Reset is not available during a nonvolatile write cycle.
Passwords are changed by sending the “change read
password” or “change write password” commands in a
normal sector write operation. A full eight bytes con-
taining the new password must be sent, following suc-
cessful transmission of the current write password and
a valid password ACK response. The user can use a
repeated ACK Polling command to check that a new
password has been written correctly. An ACK indicates
that the new password is valid.
There is no way to read any of the passwords.
Continued clocks after the 32-bits, will output the 32-bit
sequence again, starting at byte 0.
Response to Reset (Default = 19 00 AA 55)
The ISO Response to reset is controlled by the RST,
CS and CLK pins. When RST is pulsed high, while CS
is low, the device will output 32-bits of data, one bit per
clock. This conforms to the ISO standard for “synchro-
nous response to reset”. CS must remain LOW and the
part must not be in a write cycle for the response to
reset to occur.
Figure 7. Response to RESET(RST)
CS
RST
SCK
0
0
1
0
1
0
SO
0
0
1
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0 0
0
0
1
1 1
0
1
MSB
LSB
LSB
MSB
MSB LSB
MSB
LSB
2
3
Byte
0
1
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X76F100
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ....................–65°C to +135°C
Storage temperature ........................–65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
respect to V .........................................–1V to +7V
SS
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
X76F100
Limits
4.5V to 5.5V
3.0V to 5.5V
–40°C
X76F100-3
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
= V x 0.1/V x 0.9 Levels @ 400 kHz,
SDA = Open
I
V
Supply Current
(Read)
1
mA
f
SCL
CC1
CC
CC
CC
RST = CS = V
SS
(3)
CC2
I
V
Supply Current
3
mA
f
= V x 0.1/V x 0.9 Levels @ 400 kHz,
CC
SCL CC CC
(Write)
SDA = Open
RST = CS = V
SS
(1)
(1)
I
I
V
Supply Current
1
1
µA
µA
V
= V x 0.1, V = V x 0.9
SB1
CC
IL
CC
IH
CC
(Standby)
f
= 400 kHz, f
= 400 kHz
SCL
SDA
V
Supply Current
V
= V
= V
SB2
CC
SDA
SCC CC
(Standby)
Other = GND or V –0.3V
CC
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
(2)
V
–0.5
V
V
x 0.3
IL
CC
(2)
V
Input HIGH Voltage
Output LOW Voltage
V
x 0.7
+ 0.5
V
IH
CC
CC
V
0.4
V
I
= 3mA
OL
OL
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Test
Output Capacitance (SDA)
Input Capacitance (RST, SCL, CS)
Max.
Unit
pF
Conditions
(3)
OUT
C
8
6
V
= 0V
= 0V
I/O
(3)
IN
C
pF
V
IN
Notes: (1) Must perform a stop command after a read command prior to measurement.
(2) V min. and V max. are for reference only and are not tested.
IL
IH
(3) This parameter is periodically sampled and not 100% tested.
Characteristics subject to change without notice. 8 of 16
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X76F100
AC CHARACTERISTICS (T = -40°C to +85°C, V
= +3.0V to +5.5V, unless otherwise specified.)
A
CC
Symbol
Parameter
Min.
Max. Unit
f
SCL Clock Frequency
0
1
MHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
µs
ns
ns
ns
SCL
(3)
t
SCL LOW to SDA Data Out Valid
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
0.1
0.9
AA
t
1.2
BUF
t
t
0.6
HD:STA
t
Clock LOW Period
1.2
LOW
t
Clock HIGH Period
0.6
HIGH
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
0.6
SU:STA
HD:DAT
t
10
t
Data In Setup Time
100
SU:DAT
(2)
(2)
t
SDA and SCL Rise Time
20+0.1XC
300
300
R
b
b
t
SDA and SCL Fall Time
20+0.1XC
F
t
Stop Condition Setup Time
Data Out Hold Time
0.6
0
SU:STO
t
DH
t
RST to SCL Non-Overlap
500
0
NOL
RDV
CDV
t
t
RST LOW to SDA Valid During Response to Reset
CLK LOW to SDA Valid During Response to Reset
Device Deselect to SDA high impedance
Device Select to RST active
RST High Time
450
450
450
0
(1)
t
0
DHZ
(1)
t
0
SR
t
1.5
500
200
100
RST
t
RST Setup Time
SU:RST
t
t
CS Setup Time
SU:CS
CS Hold Time
SU:CS
Notes: (1) These Specs are not defined in the ISO 7816-3 Standard, since CS is not defined.
(2) C = total capacitance of one bus line in pF
b
(3) t = 1.1µs Max below V = 3.0V.
AA
CC
RESET AC SPECIFICATIONS
Power Up Timing
Symbol
Parameter
Min.
Typ.(2)
Max.
Unit
(1)
t
Time from Power Up to Read
Time from Power Up to Write
1
5
ms
ms
PUR
(1)
PUW
t
Notes: (1) DelaysaremeasuredfromthetimeV isstableuntilthespecifiedoperationcanbeinitiated.Theseparametersareperiodicallysampled
CC
and not 100% tested.
(2) Typical values are for T = 25°C and V = 5.0V
A
CC
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X76F100
Nonvolatile Write Cycle Timing
Symbol
Parameter
Write Cycle Time
Min.
Typ.(1)
Max.
Unit
(1)
WC
t
5
10
ms
Note: (1) t
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
WC
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Bus Timing
t
t
t
R
t
HIGH
LOW
F
SCL
t
t
t
t
SU:STO
t
SU:STA
HD:DAT
SU:DAT
HD:STA
SDA IN
t
t
DH
t
AA
BUF
SDA OUT
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
t
WC
Stop Condition
Start Condition
CS Timing Diagram (Selecting/Deselecting the Part)
SCL
t
t
HD:CS
SU:CS
CS from
Master
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X76F100
RST Timing Diagram—Response to a Synchronous Reset
t
SR
CS
RST
t
RST
t
t
HIGH_RST
t
NOL
NOL
1st
2nd
CLK
3rd
CLK
Pulse
CLK
I/O
CLK
Pulse
Pulse
t
LOW_RST
t
SU:RST
t
t
CDV
RDV
Data Bit (2)
Data Bit (1)
CS
RST
CLK
t
DHZ
Data Bit (N+1)
(N+2)
Data Bit (N)
I/O
GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS
100
V
CCMAX
80
60
40
20
R
= -------------------------- = 1. 8 KΩ
MIN
I
R
OLMIN
MAX
t
R
R
= -----------------
C
MAX
BUS
R
MIN
20 40 60 80 100
t
= maximum allowable SDA rise time
R
Bus Capacitance in pF
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X76F100
PACKAGING INFORMATION
8-Lead Miniature Small Outline Gull Wing Package Type M
0.118 ± 0.002
(3.00 ± 0.05)
0.012 + 0.006 / -0.002
(0.30 + 0.15 / -0.05)
0.0256 (0.65) Typ.
R 0.014 (0.36)
0.118 ± 0.002
(3.00 ± 0.05)
0.030 (0.76)
0.0216 (0.55)
7° Typ.
0.036 (0.91)
0.032 (0.81)
0.040 ± 0.002
(1.02 ± 0.05)
0.008 (0.20)
0.004 (0.10)
0.0256" Typical
0.025"
Typical
0.150 (3.81)
0.007 (0.18)
0.005 (0.13)
Ref.
0.193 (4.90)
Ref.
0.220"
0.020"
Typical
8 Places
FOOTPRINT
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
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X76F100
PACKAGING INFORMATION
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
Pin 1 Index
Pin 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) Ref.
Half Shoulder Width On
All End Pins Optional
0.145 (3.68)
0.128 (3.25)
Seating
Plane
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.150 (3.81)
0.125 (3.18)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
.073 (1.84)
Max.
0°
Typ. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 13 of 16
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X76F100
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050"Typical
X 45°
0.020 (0.50)
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 14 of 16
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X76F100
PACKAGING INFORMATION
8 Pad Chip on Board Smart Card Module Type X
0.465 ± 0.002
(11.81 ± 0.05)
0.285 (7.24) Max.
See Note 7 Sht. 2
0.088 (2.24) Min Epoxy
Free Area (Typ.)
R. 0.078 (2.00)
0.069 (1.75) Min Epoxy
Free Area (Typ.)
0.270 (6.86) Max.
See Note 7 Sht. 2
0.420 ± 0.002
(10.67 ± 0.05)
A
A
0.008 ± 0.001
(0.20 ± 0.03)
0.210 ± 0.002
(5.33 ± 0.05)
0.233 ± 0.002
(5.92 ± 0.05)
Die
0.0235 (0.60) Max.
SECTION A-A
FR4 Tape
Glob Size
0.015 (0.38) Max.
0.008 (0.20) Max.
See Detail Sheet 3
Copper, Nickel Plated, Gold Flash
0.174 ± 0.002
(4.42 ± 0.05)
0.146 ± 0.002
(3.71 ± 0.05)
R. 0.013 (0.33) (8x)
V
V
SS
CC
0.105 ± 0.002
(2.67 ± 0.05) Typ.
RST
SCL
NC
CS
(8x)
SDA
NC
0.105 ± 0.002
(8x)
(2.67 ± 0.05)
NOTE: ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
Characteristics subject to change without notice. 15 of 16
REV 1.0 6/22/00
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X76F100
Ordering Information
X76F100
X
X
–X
Device
V
Limits
CC
Blank = 5V ±10%
3.0 = 3.0V to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial= –40°C to +85°C
Package
S8 = 8-Lead SOIC
M8 = 8-Lead MSOP
P = 8-Lead PDIP
H = Die in Waffle Packs
W = Die in Wafer Form
X = Smart Card Module
Part Mark Convention
8-Lead MSOP
8-Lead SOIC/PDIP
EYWW
XXX
Blank = 8-Lead SOIC
X76F100 X
XX
AAQ = 3.0 to 5.5V, 0 to +70°C
AAR = 3.0 to 5.5V, -40 to +85°C
AAS = 4.5 to 5.5V, 0 to +70°C
AAT = 4.5 to 5.5V, -40 to +85°C
D = 3.0 to 5.5V, 0 to +70°C
E = 3.0 to 5.5V, -40 to +85°C
Blank = 4.5 to 5.5V, 0 to +70°C
I = 4.5 to 5.5V, -40 to +85°C
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 16 of 16
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