X76F128Y-2.7 [XICOR]
Secure SerialFlash; 安全SerialFlash
| 型号： | X76F128Y-2.7 |
| 厂家： | 
XICOR INC. |
| 描述： | Secure SerialFlash |
| 文件： | 总17页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128K
16Kx8+64x8
X76F128
Secure SerialFlash
FEATURES
DESCRIPTION
• 64-bit Password Security
—Five 64-bit Passwords for Read, Program
and Reset
• 16384 Byte+64 Byte Password Protected Arrays
—Seperate Read Passwords
—Seperate Write Passwords
—Reset Password
• Programmable Passwords
• Retry Counter Register
—Allows 8 tries before clearing of both arrays
—Password Protected Reset
• 32-bit Response to Reset (RST Input)
• 64 byte Sector Program
• 400kHz Clock Rate
The X76F128 is a Password Access Security Supervisor,
containing one 131072-bit Secure SerialFlash array and
one 512-bit Secure SerialFlash array. Access to each
memory array is controlled by two 64-bit passwords.
These passwords protect read and write operations of
the memory array. A separate RESET password is used
to reset the passwords and clear the memory arrays in
the event the read and write passwords are lost.
The X76F128 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the device
is controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
• 2 wire Serial Interface
• Low Power CMOS
—2.7 to 5.5V operation
The X76F128 also features a synchronous response to
reset providing an automatic output of a hard-wired 32-bit
data stream conforming to the industry standard for
memory cards.
—Standby current Less than 1µA
—Active current less than 3 mA
• High Reliability Endurance:
—100,000 Write Cycles
• Data Retention: 100 years
• Available in:
TM
The X76F128 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
—SmartCard Module
—TQFP Package
Functional Diagram
CS
CHIP ENABLE
16K BYTE
SerialFlash ARRAY
ARRAY 0
DATA TRANSFER
SCL
(PASSWORD PROTECTED)
SDA
ARRAY ACCESS
ENABLE
INTERFACE
LOGIC
64 BYTE
SerialFlash ARRAY
ARRAY 1
PASSWORD ARRAY
AND PASSWORD
(PASSWORD PROTECTED)
VERIFICATION LOGIC
RST
RESET
RETRY COUNTER
RESPONSE REGISTER
7052 FM 01
Xicor, Inc. 1994, 1995, 1996 Patents Pending
7052 10/7/97 T0/C0/D0 SH
Characteristics subject to change without notice
1
X76F128
PIN DESCRIPTIONS
Serial Clock (SCL)
If the X76F128 is in a nonvolatile write cycle a “no ACK”
(SDA=High) response will be issued in response to load-
ing of the command byte. If a stop is issued prior to the
nonvolatile write cycle the write operation will be termi-
nated and the part will reset and enter into a standby
mode.
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a true three state serial data input/output pin. Dur-
ing a read cycle, data is shifted out on this pin. During a
write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
The basic sequence is illustrated in Figure 1.
PIN NAMES
Symbol
CS
Description
Chip Select Input
Chip Enable (CS)
When CS is high, the X76F128 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway, the X76F128 will be in
standby mode. CS low enables the X76F128, placing it in
the active mode.
SDA
SCL
RST
Vcc
Vss
NC
Serial Data Input/Output
Serial Clock Input
Reset Input
Supply Voltage
Ground
Reset (RST)
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F128 will output 32 bits of fixed
data which conforms to the standard for “synchronous
response to reset”. CS must remain LOW and the part
must not be in a write cycle for the response to reset to
occur. See Figure 11. If at any time during the response
to reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state. The
response to reset is "mask programmable" only!
No Connect
7052 FM T01
PIN CONFIGURATION
Smart Card
GND
CS
V
CC
RST
SCL
NC
SDA
NC
DEVICE OPERATION
7052 FM 02
There are two primary modes of operation for the
X76F128; Protected READ and protected WRITE.
Protected operations must be performed with one of four
8-byte passwords.
1
2
3
4
5
6
7
8
36
35
34
33
32
31
30
29
28
27
26
25
VCC
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
CS
The basic method of communication for the device is
established by first enabling the device (CS LOW), gen-
erating a start condition, then transmitting a command,
followed by the correct password. All parts will be
shipped from the factory with all passwords equal to ‘0’.
The user must perform ACK Polling to determine the
validity of the password, before starting a data transfer
(see Acknowledge Polling.) Only after the correct pass-
word is accepted and a ACK polling has been performed,
can the data transfer occur.
NC
NC
NC
NC
NC
NC
NC
NC
NC
RST
SCL
9
10
11
12
SDA
To ensure the correct communication, RST must remain
LOW under all conditions except when running a
“Response to Reset sequence”.
After each transaction is completed, the X76F128 will
reset and enter into a standby mode.This will also be the
response if an unsuccessful attempt is made to access a
protected array.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
2
X76F128
Figure 1. X76F128 Device Operation
Start Condition
All commands are preceeded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F128 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition is met.
LOAD COMMAND BYTE
LOAD 8-BYTE
PASSWORD
A start may be issued to terminate the input of a control
byte or the input data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start can-
not be generated while the part is outputting data. Starts
are inhibited while a write is in progress.
VERIFY PASSWORD
ACCEPTANCE BY
USE OF PASSWORD ACK POLLING
Stop Condition
LOAD 2 BYTE ADDRESS
All communications must be terminated by a stop condi-
tion. The stop condition is a LOW to HIGH transition of
SDA when SCL is HIGH. The stop condition is also used
to reset the device during a command or data input
sequence and will leave the device in the standby power
mode. As with starts, stops are inhibited when outputting
data and while a write is in progress.
READ/WRITE
DATA BYTES
Twc OR DATA ACK POLLING
Acknowledge
7052 FM 03
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.
Retry Counter
The X76F128 contains a retry counter. The retry counter
allows 8 accesses with an invalid password before any
action is taken. The counter will increment with any com-
bination of incorrect passwords. If the retry counter over-
flows, all memory areas are cleared and the device is
locked by preventing any read or write array password
matches. The passwords are unaffected. If a correct
password is received prior to retry counter overflow, the
retry counter is reset and access is granted. In order to
reset the operation of a locked up device, a special reset
command must be used with a RESET PASSWORD.
The X76F128 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F128 will respond with an acknowledge
after the receipt of each subsequent eight-bit word.
RESET DEVICE Command
The RESET DEVICE command is used to clear the retry
counter and reactivate the device. When the RESET
DEVICE command is used prior to the retry counter
overflow, the retry counter is reset and no arrays or pass-
words are affected. If the retry counter has overflowed, all
memory areas are cleared and all commands are
blocked and the retry counter is disabled. Issuing a valid
RESET DEVICE command (with reset password) to the
device resets and re-enables the retry counter and re-
enables the other commands. Again, the passwords are
not affected.
Device Protocol
The X76F128 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
a receiver. The device controlling the transfer is a master
and the device being controlled is the slave. The master
will always initiate data transfers and provide the clock for
both transmit and receive operations. Therefore, the
X76F128 will be considered a slave in all applications.
Clock and Data Conventions
RESET PASSWORD Command
Data states on the SDA line can change only during SCL
LOW. SDA changes during SCL HIGH are reserved for
indicating start and stop conditions. Refer to Figure 2 and
Figure 3.
A RESET PASSWORD command will clear both arrays
and set all passwords to all zero.
3
X76F128
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
7052 FM 04
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
Start Condition
Stop Condition
7052 FM 05
Table 1. X76F128 Instruction Set
1st Byte
after
after Start Password
2nd Byte
1st Byte
after
Password
Password
Command Description
Read (Array 0)
used
Read 0
Read 1
Write 0
Write 1
Read 0
Read 1
Write 0
Write 1
Reset
1000 0000 High Address Low address
1000 1000 High Address Low address
1001 0000 High Address Low address
1001 1000 High Address Low address
Read (Array 1)
Sector Write (Array 0)
Sector Write (Array 1)
1010 0000
1010 1000
1011 0000
1011 1000
1100 0000
1110 0000
1110 1000
1111 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
not used
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
not used
Change Read 0 Password
Change Read 1 Password
Change Write 0 Password
Change Write 1 Password
Change Reset Password
RESET PASSWORD Command
RESET DEVICE Command
ACK Polling command (Ends Password operation)
Reserved
Reset
not used
not used
Reset
not used
not used
None
All the rest
7052 FM T04
Notes: Illegal command codes will be disregarded.The part will respond with a “no-ACK” to the illegal byte and then return to the standby mode.
All write/read operations require a password.
4
X76F128
PROGRAM OPERATIONS
Sector Programming
The sector program mode requires issuing the 8-bit write
command followed by the password, password Ack com-
mand, the address and then the data bytes transferred
as illustrated in figure 4. Up to 64 bytes may be trans-
ferred. After the last byte to be transferred is acknowl-
edged a stop condition is issued which starts the
nonvolatile write cycle.
Figure 4. Sector Programming
Write
Password
Write
Password
0
7
COMMAND
Wait tWC
OR
Repeated
SDA
S
ACK Polling
Command
If ACK, Then
Password Matches
ACK POLLING
COMMAND
Data 0
. . .
S
Data 63
Wait t
WC
S
Data ACK Polling
7052 FM 07
5
X76F128
ACK Polling
requires the master to perform an ACK polling with the
specific code of F0h. As with regular Acknowledge polling
the user can either time out for 10ms, and then issue the
ACK polling once, or continuously loop as described in the
flow.
Once a stop condition is issued to indicate the end of the
host’s write sequence, the X76F128 initiates the internal
nonvolatile write cycle. In order to take advantage of the
typical 5ms write cycle, ACK polling can begin
immediately. This involves issuing the start condition
followed by the new command code of 8 bits (1st byte of
the protocol.) If the X76F128 is still busy with the
nonvolatile write operation, it will issue a “no-ACK” in
response. If the nonvolatile write operation has
completed, an “ACK” will be returned and the host can
then proceed with the rest of the protocol.
Password ACK Polling Sequence
PASSWORD LOAD
COMPLETED
ENTER ACK POLLING
ISSUE START
Data ACK Polling Sequence
WRITE SEQUENCE
COMPLETED
ISSUE
ENTER ACK POLLING
PASSWORD
ACK COMMAND
ISSUE START
NO
ACK
RETURNED?
ISSUE NEW
COMMAND
CODE
YES
PROCEED
NO
ACK
7052 FM 09
RETURNED?
If the password that was inserted was correct, then an
“ACK” will be returned once the nonvolatile cycle is over,
in response to the ACK polling cycle immediately following
it.
YES
PROCEED
7052 FM 08
If the password that was inserted was incorrect, then a “no
ACK” will be returned even if the nonvolatile cycle is over.
Therefore, the user cannot be certain that the password is
incorrect until the 10ms write cycle time has elapsed.
After the password sequence, there is always a nonvola-
tile write cycle. This is done to discourage random
guesses of the password if the device is being tampered
with. In order to continue the transaction, the X76F128
Figure 5. Acknowledge Polling
SCL
SDA
8th clk.
of 8th
pwd. byte
8th
clk
‘ACK’
clk
‘ACK’
clk
8th bit
‘ACK’
START
condition
ACK or
no ACK
7052 FM 10
6
X76F128
READ OPERATIONS
Sequential Read
The host can read sequentially within an array after the
password acceptance sequence. The data output is
sequential, with the data from address n followed by the
data from n+1. The address counter for read operations
increments all address bits, allowing the entire memory
array contents to be serially read during one operation. At
the end of the address space (address 3FFFh for array 0,
3Fh for array 1), the counter “rolls over” to address 0 and
the X76F128 continues to output data for each acknowl-
edge received. Refer to figure 7 for the address, acknowl-
edge and data transfer sequence. An acknowledge must
follow each 8-bit data transfer. After the last bit has been
read, a stop condition is generated without a preceding
acknowledge.
Read operations are initiated in the same manner as write
operations but with a different command code.
Random Read
The master issues the start condition and a Read instruc-
tion and password, performs a Password Ack Polling, then
issues the word address. Once the password has been
acknowledged and first byte has been read, another start
can be issued followed by a new 8-bit address. Random
reads are allowed, but only the low order 8 bits can
change. This limits random reads to a 512 byte block.
Therefore, with a single password cycle only a 512 byte
block of array 0 may be accessed randomly. To randomly
access another block of array 0, a stop must be issued fol-
lowed by a new command/address/password sequence. A
random read of the array 1 can access all locations with-
out another password command sequence.
Figure 6. Random Read
Read
Password
Read
Password
7
COMMAND
0
Wait tWC
OR
Repeated
SDA
S
ACK Polling
Command
If ACK, then
Password Matches
ACK POLLING
COMMAND
S
S
S
Data Y
Data X
7052 FM 11
Figure 7. Sequential Read
Read
Read
Password
7
Password
0
Wait t
WC
COMMAND
OR
Repeated
ACK Polling
Command
SDA
S
If ACK, then
Password Matches
ACK POLLING
COMMAND
S
S
Data X
Data 0
7052 FM 12
7
X76F128
PASSWORDS
After this time, it cannot be determined if the password
has been loaded correctly, without trying the new pass-
word. To determine if the new password has been loaded
correctly the data ACK polling command is issued imme-
diately following the stop bit. If it returns an ACK, then the
two passes of the new password entry do not match. If it
returns a "no ACK" then the passwords match and a high
voltage cycle is in progress. The high voltage cycle is
complete when a subsequent data ACK command
returns an "ACK".
The sequence in Figure 8 shows how to change (pro-
gram) the passwords. The programming of passwords is
done twice prior to the nonvolatile write cycle in order to
verify that the new password is consistent. After the eight
bytes are entered in the second pass, a comparison
takes place. A mismatch will cause the part to reset and
enter into the standby mode.
Data ACK polling can be used to determine if a password
has been loaded correctly, however the data ACK com-
mand must be issued less than 2ms after the stop bit.
There is no way to read any of the passwords.
Figure 8. Change Passwords
Old
Password
Old
Password
COMMAND
7
Wait tWC
OR
Repeated
0
SDA
S
ACK Polling
Command
If ACK, then
Password Matches
New
Password
ACK POLLING
COMMAND
7
Two bytes of “0”
S
Data ACK
Polling
New
New
Password
0
Password
Password
0
7
If immediate ACK,
then New Password error
S
If immediate NACK,
followed by ACK after ~5ms
then New Password OK
7052 FM 13
RESPONSE TO RESET
The X76F128 returns a unique 32 bits response to reset
by implementing the following procedures:
• RST goes LOW
• Each subsequent clock forces next response to
reset bit onto SO pin.
• CS goes LOW
For the X76F128, the 32 bit sequence is 19h, 28h, AAh,
55h with each byte output LSB first. See Figure 11.
• RST goes HIGH
• SCK toggles Low-HIGH-Low
8
X76F128
Figure 9. Reset Password
Wait t
WC
If ACK, then
Device reset
OR
Repeated
Reset
Password
0
Reset
Password
7
ACK Polling
Command
ACK POLLING
COMMAND
Reset Password
COMMAND
SDA
S
S
S
7052 FM 14
Figure 10. Reset Device
Wait t
WC
If ACK, then
Device reset
OR
Repeated
Reset
Password
0
Reset
Password
7
ACK Polling
Command
ACK POLLING
COMMAND
Reset Device
COMMAND
SDA
S
S
S
7052 FM 15
Figure 11. Response to RESET (RST)
CS
RST
SCK
LSB
LSB
LSB
LSB
3
1
2
8
2
7
2
0
1
8
1
4
1
2
1
0
8
7
5
3
1
SO
"19"
"28"
"AA"
"SS"
7052 FM 16
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias ......................–65°Cto+135°C
Storage Temperature ...........................–65°Cto+150°C
Voltage on any Pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Respect to V ......................................–1V to +7V
SS
D.C. Output Current..................................................5mA
Lead Temperature
(Soldering, 10 seconds)................................. 300°C
9
X76F128
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Extended
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
X76F128
Limits
4.5V to 5.5V
2.7V to 3.6V
–20°C
X76F128 – 2.7
7052 FM T05
7052 FM T06
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
f
SCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz,
VCC Supply Current
(Read)
ICC1
SDA = Open
RST = CS = VSS
1
mA
f
SCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz,
VCC Supply Current
(Write)
(3)
SDA = Open
RST = CS = VSS
3
mA
ICC2
V
IL = VCC x 0.1, VIH = VCC x 0.9
fSCL = 400 KHz, fSDA = 400 KHz
SDA = VSCC = VCC
Other = GND or VCC–0.3V
VCC Supply Current
(Standby)
(1)
50
1
µA
µA
ISB1
V
VCC Supply Current
(Standby)
(1)
ISB2
ILI
V
V
IN = VSS to VCC
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
µA
µA
V
ILO
OUT = VSS to VCC
10
(2)
V
CC x 0.3
VCC = 5.5V
VCC = 5.5V
VCC = 3.0V
VCC = 3.0V
–0.5
VIL1
(2)
V
CC x 0.7 VCC + 0.5
CC x 0.1
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
V
V
V
V
VIH1
(2)
V
–0.5
VIL2
(2)
V
CC x 0.9 VCC + 0.5
0.4
VIH2
VOL
IOL = 3mA
7052 FM T07
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Test
Max.
Units
Conditions
I/O = 0V
IN = 0V
(3)
V
Output Capacitance (SDA)
8
pF
COUT
(3)
V
Input Capacitance (RST, SCL, CS)
6
pF
CIN
7052 FM T08
NOTES: (1) Must perform a stop command after a read command prior to measurement
(2) min. and V max. are for reference only and are not tested.
V
IL
IH
(3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
VCC x 0.1 to VCC x 0.9
Input Pulse Levels
5V
3V
Input Rise and Fall Times
Input and Output Timing Level
Output Load
10ns
1533Ω
1.3KΩ
V
CC x 0.5
OUTPUT
OUTPUT
100pF
100pF
100pF
7052 FM T09
7052 FM 17
10
X76F128
AC CHARACTERISTICS
AC Specifications (Over the recommended operating conditions)
(1)
Symbol
fSCL
Parameter
SCL Clock Frequency, X76F128
SCH Clock Frequency, X76F128–2.7
Min
0
Typ
Max
400
250
Units
KHz
fSCL
0
KHz
Pulse width of spikes which must be suppressed by
the input filter
(1)
50
0.1
1.3
100
0.3
ns
µs
µs
tIN
tAA
SCL LOW to SDA Data Out Valid
0.9
Time the bus must be free before a new transmit
can start
tBUF
tLOW
Clock LOW Time
1.3
0.6
0.6
0.6
100
0
µs
µs
µs
µs
ns
µs
µs
ns
ns
tHIGH
Clock HIGH Time
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
0.6
50
300
(2)
(2)
tR
300
300
20 + 0.1 x Cb
tF
SDA and SCL Fall Time
ns
ns
ns
kHz
ns
ns
µs
µs
µs
µs
ns
ns
20 + 0.1 x Cb
200
tSU:CS
tHD:CS
fSCL_RST
CS Setup Time
CS Hold Time
100
SCL Clock Frequency during Response to Reset
Device Select to RST active
400
200
500
2.25
1.25
1.25
1.25
0
tSR
tNOL
RST to SCL Non-Overlap
tRST
RST High Time
tSU:RST
tLOW_RST
tHIGH_RST
tRDV
Response to Reset Setup Time
Clock LOW during Response to Reset
Clock HIGH during Response to Reset
RST LOW to SDA Valid During Response to Reset
CLK LOW to SDA Valid During Response to Reset
Device Deselect to SDA high impedance
500
500
500
tCDV
0
0
ns
tDHZ
7052 FM T14
Notes: 1. Typical values are for T = 25˚C and V = 5.0V
A
CC
Notes: 2. C = Total Capacitance of one bus line in pf.
b
11
X76F128
RESET AC SPECIFICATIONS
Power Up Timing
(2)
Symbol
Parameter
Min.
Typ
Max.
Units
(1)
Time from Power Up to Read
Time from Power Up to Write
1
mS
tPUR
(1)
5
mS
tPUW
7052 FM T11
Notes: 1. Delays are measured from the time V is stable until the specified operation can be initiated.These parameters are periodically sampled
CC
and not 100% tested.
2. Typical values are for T = 25˚C and V = 5.0V
A
CC
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
(1)
Write Cycle Time
5
10
mS
tWC
7052 FM T12
Notes: 1.
t
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
WC
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
TIMING DIAGRAMS
Bus Timing
t
t
t
t
LOW
R
F
HIGH
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA IN
t
t
t
BUF
AA
DH
SDA OUT
7052 FM 18
Write Cycle Timing
SCL
8th bit of last byte
ACK
SDA
t
WC
Stop
Condition
Start
Condition
7052 FM 19
12
X76F128
CS Timing Diagram (Selecting/Deselecting the Part)
SCL
t
t
HD:CS
SU:CS
CS
from
master
7052 FM 20
RST Timing Diagram – Response to a Synchronous Reset
t
SR
CS
RST
CLK
t
RST
t
t
HIGH_RST
t
NOL
NOL
1st
clk
pulse
2nd
clk
pulse
3rd
clk
pulse
t
LOW_RST
t
SU:RST
t
t
CDV
RDV
I/O
DATA BIT (2)
DATA BIT (1)
CS
RST
CLK
t
DHZ
I/O
DATA BIT (N+1)
(N+2)
DATA BIT (N)
7052 FM 21
GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS
100
V
CCMAX
80
60
40
20
R
= -------------------------- = 1.8KΩ
MIN
I
R
OLMIN
MAX
t
R
R
= -----------------
C
MAX
BUS
R
MIN
20 40 60 80 100
Bus capacitance in pF
t
= maximum allowable SDA rise time
R
7052 FM 22
13
X76F128
PACKAGING INFORMATION
48-LEAD THIN QUAD FLAT PACK (TQFP) PACKAGE TYPE L
He
E
L1
PIN 1
D
Hd
GAGE PLANE 0.25
L
e
b
A2
7°±0°
MILLIMETERS
INCHES
DIM
C
A1
MIN
MAX
MIN
MAX
A
0.05
1.35
0.17
0.15
1.45
0.27
0.002
0.53
0.006
0.057
0.011
0.008
1
A
2
b
0.007
0.004
c
D
0.090 0.200
7.0 BSC
0.273 BSC
7.0 BSC
0.273 BSC
0.02 BSC
0.35 BSC
0.35 BSC
E
e
0.5 BSC
9.0 BSC
9.0 BSC
Hd
He
L
0.45
0.75
0.018
0.030
L
1
1.00TYP
0.039 TYP
NOTES:
1. GAGE PLANE DIMENSION IS IN MM.
2. LEAD COPLANARITY SHALL BE 0.10MM [0.004] MAXIMUM.
3. MOLD FLASH NOT INCLUDED IN DIMENSIONS
7052 FM 23
14
X76F128
8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X
0.465 ± 0.002
(11.81 ± 0.05)
0.088 (2.24) MIN EPOXY
FREE AREA (TYP.)
0.285 (7.24) MAX.
R. 0.039 (1.00) (4X)
0.069 (1.75) MIN EPOXY
FREE AREA (TYP.)
0.270 (6.86) MAX.
0.420 ± 0.002
(10.67 ± 0.05)
A
A
0.008 ± 0.001
(0.20 ± 0.03)
0.210 ± 0.002
(5.33 ± 0.05)
0.233 ± 0.002
(5.92 ± 0.05)
DIE
0.0235 (0.60) MAX.
SECTION A-A
GLOB SIZE
0.015 (0.38) MAX.
0.008 (0.20) MAX.
FR4 TAPE
COPPER, NICKEL PLATED, GOLD FLASH
0.174 ± 0.002
(4.42 ± 0.05)
0.146 ± 0.002
(3.71 ± 0.05)
R. 0.013 (0.33) (8x)
0.105 ± 0.002
(2.67 ± 0.05)
TYP.
(8x)
0.105 ± 0.002
(2.67 ± 0.05)
(8x)
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
3003 ILL 03.1
15
X76F128
SMART CARD TYPE Y
3.369 ± 0.002
(85.57 ± 0.05)
3° MAX.
DRAFT ANGLE
(ALL AROUND)
0.593 ± 0.002
(15.06 ± 0.05)
0.430 ± 0.002
(10.92 ± 0.05)
R.0.125
(3.18) (4x)
A
A
0.475 ± 0.010
(12.07 ± 0.25)
2.125 ± 0.002
(53.98 ± 0.05)
R. 0.030 (0.76) (4x)
0.31 ± 0.0005
(.079 ± 0.0127)
0.478 ± 0.002
(12.14 ± 0.05)
MOLD GATE DETAIL
SECTION A-A
SCALE:5x
NOTES:
1. ALL DIMENSIONS ARE IN INCHES AND (MILLIMETERS).
2. SPECIFIED DIMS ARE MEASURED AT BOTTOM OF CAVITY.
3. MATERIAL: WHITE PVC MOLDED PLASTIC WITH ANTI-STATIC ADDITIVE.
4. SURFACE FINISH SUITABLE FOR OFFSET PRINTING.
3003 ILL 02.1
16
X76F128
ORDERING INFORMATION
X76F128
X
X
–X
Device
V
Limits
CC
Blank = 5V ±10%
2.7 = 2.7V to 3.6V
Temperature Range
Blank = Commercial = 0°C to +70°C
E = Extended = –20°C to +85°C
Package
L = 48-Lead TQFP
H = Die in Waffle Packs
W = Die in Wafer Form
X = Smart Card Module
Y = Smart Card
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detec-
tion and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure
to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life sup-
port device or system, or to affect its safety or effectiveness.
17
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