X76F200S8I-2 [XICOR]
Flash, 256X8, PDSO8, PLASTIC, SOIC-8;
| 型号： | X76F200S8I-2 |
| 厂家： | 
XICOR INC. |
| 描述： | Flash, 256X8, PDSO8, PLASTIC, SOIC-8 时钟 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：490K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2K
256 x 8 Bit
X76F200
Secure SerialFlash
FEATURES
DESCRIPTION
• 64-bit password security
• One array (240 bytes) two passwords (16 bytes)
—Read password
—Write password
• Programmable passwords
• Retry counter register
—Allows 8 tries before clearing of the array
• 32-bit response to reset (RST input)
• 8 byte sector write mode
• 1MHz clock rate
The X76F200 is a password access security supervi-
sor, containing one 1920-bit Secure SerialFlash array.
Access to the memory array can be controlled by two
64-bit passwords. These passwords protect read and
write operations of the memory array.
The X76F200 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA).
• 2-wire serial interface
• Low power CMOS
—2.0 to 5.5V operation
—Standby current less than 1µA
—Active current less than 3 mA
• High reliability endurance:
—100,000 write cycles
• Data retention: 100 years
• Available in:
The X76F200 also features a synchronous response
to reset providing an automatic output of a hard-wired
32-bit data stream conforming to the industry standard
for memory cards.
The X76F200 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
—8-lead PDIP, SOIC,TSSOP, smart card and
smart card module
BLOCK DIAGRAM
Retry Counter
Data Transfer
Erase Logic
SCL
SDA
Array Access
Enable
Interface
Logic
240 Byte
EEPROM Array
Password Array
and Password
Verification Logic
RST
ISO Reset
Response Register
Characteristics subject to change without notice. 1 of 16
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X76F200
PIN DESCRIPTIONS
Serial Clock (SCL)
If the X76F200 is in a nonvolatile write cycle, a “no ACK”
(SDA = High) response will be issued in response to
loading of the command byte. If a stop is issued prior to
the nonvolatile write cycle, the write operation will be
terminated; the part will reset and enter into a standby
mode.
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
The basic sequence is illustrated in Figure 1.
SDA is an open drain serial data input/output pin. Dur-
ing a read cycle, data is shifted out on this pin. During
a write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
PIN NAMES
Symbol
SDA
Description
Serial Data Input/Output
Serial Clock Input
Reset Input
Reset (RST)
SCL
RST is a device reset pin. When RST is pulsed high
the X76F200 will output 32 bits of fixed data which con-
forms to the standard for “synchronous response to
reset”. The part must not be in a write cycle for the
response to reset to occur. See Figure 7. If power is
interrupted during the response to reset, it will abort,
and the part will return to standby state. The response
to reset is “mask programmable” only!
RST
V
Supply Voltage
Ground
CC
V
SS
NC
No Connect
PIN CONFIGURATION
Smart Card
PDIP
DEVICE OPERATION
RST
SCL
SDA
NC
V
CC
1
2
8
7
6
5
The X76F200 memory array consists of thirty 8-byte
sectors. Read or write access to the array always
begins at the first address of the sector. Read opera-
tions then can continue indefinitely. Write operations
must total 8 bytes.
NC
NC
3
4
V
SS
SOIC
There are two primary modes of operation for the
X76F200; protected READ and protected WRITE. Pro-
tected operations must be performed with one of two 8-
byte passwords.
V
V
CC
SS
1
8
V
GND
CC
RST
NC
SDA
NC
2
7
6
5
SCL
NC
RST
NC
3
4
The basic method of communication for the device is to
generate a start condition, then to transmit a com-
mand, followed by the correct password. All parts will
be shipped from the factory with all passwords equal to
‘0’. The user must perform ACK Polling to determine
the validity of the password, before starting a data
transfer (see Acknowledge polling.) The data transfer
occurs after the correct password is accepted and an
ACK polling has occurred.
SCL
NC
SDA
NC
TSSOP
RST
SCL
SDA
NC
V
CC
1
2
8
7
6
5
NC
NC
3
4
V
SS
To ensure the correct communication, RST must
remain LOW under all conditions except when running
a “Response to Reset sequence”.
After each transaction is completed, the X76F200 will
reset and enter into a standby mode. This will also be
the response if an unsuccessful attempt is made to
access a protected array.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
Characteristics subject to change without notice. 2 of 16
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X76F200
Figure 1. X76F200 Device Operation
Start Condition
All commands are preceeded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F200 continuously monitors the SDA
and SCL lines for the start condition, and will not
respond to any command until this condition is met.
Load Command/Address Byte
Load 8-Byte
Password
A start may be issued to terminate the input of a con-
trol byte or the input data to be written. This will reset
the device and leave it ready to begin a new read or
write command. Because of the push/pull output, a
start cannot be generated while the part is outputting
data. Starts are inhibited while a write is in progress.
Verify Password
Acceptance By
Use Of ACK Polling
Stop Condition
All communications must be terminated by a stop con-
dition. The stop condition is a LOW to HIGH transition
of SDA when SCL is HIGH. The stop condition is also
used to reset the device during a command or data
input sequence, and will leave the device in the
standby power mode. As with starts, stops are inhib-
ited when outputting data and while a write is in
progress.
Read/Write
Data Bytes
Retry Counter
The X76F200 contains a retry counter. The retry
counter allows 8 accesses with an invalid password
before any action is taken. The counter will increment
with any combination of incorrect passwords. If the
retry counter overflows, the memory area and both of
the passwords are cleared to “0”. If a correct password
is received prior to retry counter overflow, the retry
counter is reset and access is granted.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.
Device Protocol
The X76F200 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as a receiver. The device controlling the transfer
is a master and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive opera-
tions. Therefore, the X76F200 will be considered a
slave in all applications.
The X76F200 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F200 will respond with an acknowl-
edge after the receipt of each subsequent eight-bit
word.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figure 2 and Figure 3.
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X76F200
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
Start Condition
Stop Condition
Table 1. X76F200 Instruction Set
Command After Start
1 0 S S S S S 0
Command Description
Sector Write
Password Used
Write
4
3
2
1
0
1 0 S S S S S 1
Sector Read
Read
4
3
2
1
0
1 1 1 1 1 1 0 0
1 1 1 1 1 1 1 0
0 1 0 1 0 1 0 1
Change Write Password
Change Read Password
Write
Write
Password ACK Command
None
Illegal command codes will be disregarded. The part
will respond with a “no-ACK” to the illegal byte and
then return to the standby mode. All write/read opera-
tions require a password.
ACK Polling
Once a stop condition is issued to indicate the end of
the host’s write sequence, the X76F200 initiates the
internal nonvolatile write cycle. In order to take advan-
tage of the typical 5ms write cycle, ACK polling can
begin immediately. This involves issuing the start con-
dition, followed by the new command code of 8 bits
(1st byte of the protocol.) If the X76F200 is still busy
with the nonvolatile write operation, it will issue a “no-
ACK” in response. If the nonvolatile write operation has
completed, an “ACK” will be returned, and the host can
then proceed with the rest of the protocol.
PROGRAM OPERATIONS
Sector Write
The sector write mode requires issuing the 8-bit write
command, followed by the password and the data
bytes transferred (illustrated in Figure 4). The write
command byte contains the address of the sector to be
written. Data is written starting at the first address of a
sector, and eight bytes must be transferred. After the
last byte to be transferred is acknowledged a stop con-
dition is issued, which starts the nonvolatile write cycle.
If more or less than 8 bytes are transferred, the data in
the sector remains unchanged.
Characteristics subject to change without notice. 4 of 16
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X76F200
Data ACK Polling Sequence
Password ACK Polling Sequence
Password Load
Completed
Enter ACK Polling
Write Sequence
Completed
Enter ACK Polling
Issue START
Issue START
Issue Password
ACK Command
Issue New
Command Code
NO
ACK
Returned?
NO
ACK
Returned?
YES
YES
PROCEED
PROCEED
READ OPERATIONS
After the password sequence, there is always a nonvola-
tile write cycle. This is done to discourage random
guesses of the password if the device is being tampered
with. In order to continue the transaction, the X76F200
requires the master to perform a password ACK polling
sequence with the specific command code of 55h. As
with regular Acknowledge polling, the user can either
time out for 10ms, and then issue the ACK polling once,
or continuously loop as described in the flow.
Read operations are initiated in the same manner as
write operations, but with a different command code.
Sector Read
With sector read, a sector address is supplied with the
read command. Once the password has been
acknowledged, data may be read from the sector. An
acknowledge must follow each 8-bit data transfer. A
read operation always begins at the first byte in the
sector, but may stop at any time. Random accesses to
the array are not possible. Continuous reading from the
array will return data from successive sectors. After
reading the last sector in the array, the address is auto-
matically set to the first sector in the array, and data
can continue to be read out. After the last bit has been
read, a stop condition is generated without sending a
preceding acknowledge. (See Figure 6.)
If the password inserted was correct, then an “ACK”
will be returned once the nonvolatile cycle in response
to the password ACK polling sequence is over.
If the password inserted is incorrect, then a “no ACK”
will be returned even if the nonvolatile cycle is over.
Therefore, the user cannot be certain that the pass-
word is incorrect until the 10ms write cycle time has
elapsed. (See Figure 5.)
Characteristics subject to change without notice. 5 of 16
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X76F200
Figure 4. Sector Write Sequence (Password Required)
Write
Password
7
Write
Password
0
Host
Commands
Write
Command
Wait t
WC
OR
Password
S
SDA
X76F200
Response
ACK
Command
If ACK, Then
Password Matches
Host
Commands
Password ACK
Command
Wait t
Data ACK Polling
WC
P
S
X76F200
Response
Figure 5. Acknowledge Polling
8th clk.
of 8th
Pwd. Byte
8th
clk
‘ACK’
clk
SCL
‘ACK’
clk
8th Bit
SDA
‘ACK’
START
Condition
ACK or
No ACK
Figure 6. Sector Read Sequence (Password Required)
Read
Password
7
Read
Password
0
Host
Commands
Read
Command
Wait t
WC
OR
Password
SDA
S
X76F200
Response
ACK
Command
If ACK, Then
Password Matches
Host
Commands
Password ACK
Command
P
S
Data n
Data 0
X76F200
Response
Characteristics subject to change without notice. 6 of 16
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X76F200
PASSWORDS
After initiating a nonvolatile write cycle, the RST pin
must not be pulsed until the nonvolatile write cycle is
complete. If not, the ISO response will not be acti-
vated. If the RST is pulsed HIGH and the CLK is within
Passwords are changed by sending the “change read
password” or “change write password” commands in a
normal sector write operation. A full eight bytes con-
taining the new password must be sent, following suc-
cessful transmission of the current write password and
a valid password ACK response. The user can use a
repeated ACK Polling command to check that a new
password has been written correctly. An ACK indicates
that the new password is valid.
the RST pulse (meet the t
spec.) in the middle of
NOL
an ISO transaction, it will output the 32-bit sequence
again (starting at bit 0). Otherwise, this aborts the ISO
operation and the part returns to standby state. If the
RST is pulsed HIGH and the CLK is outside the RST
pulse (in the middle of an ISO transaction), this aborts
the ISO operation and the part returns to standby state.
There is no way to read any of the passwords.
If power is interrupted during the Response to Reset, it
will be aborted and the part returned to the standby
state. A Response to Reset is not available during a
nonvolatile write cycle.
RESPONSE TO RESET (DEFAULT = 19 20 AA 55)
The ISO Response to reset is controlled by the RST
and CLK pins. When RST is pulsed high during a clock
pulse, the device will output 32 bits of data, one bit per
clock, and it resets to the standby state. This conforms
to the ISO standard for “synchronous response to
reset”. The part must not be in a write cycle for the
response to reset to occur.
Figure 7. Response to RESET (RST)
RST
SCK
0
0
0
0
1
0
0
1
1
1 0
LSB
0
0
0
0
0
0
0
1
0
1
0
1
1
1
0
1 0
1 0
1
0
SO
MSB
MSB LSB
MSB
LSB
MSB
LSB
3
2
Byte
0
1
Characteristics subject to change without notice. 7 of 16
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X76F200
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... –65°C to +135°C
Storage temperature ........................–65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
respect to V .........................................–1V to +7V
SS
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
X76F200
Limits
4.5V to 5.5V
2.0V to 5.5V
–40°C
X76F200 – 2
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
= V x 0.1/V x 0.9 Levels @ 400 kHz,
I
V
supply current
(read)
1
mA
f
SCL
CC1
CC
CC
CC
SDA = Open
RST = V
SS
(3)
I
V
supply current
3
mA
f
= V x 0.1/V x 0.9 Levels @ 400 kHz,
CC2
CC
SCL CC CC
(write)
SDA = Open
RST = V
SS
(1)
(1)
I
I
V
supply current
1
1
µA
µA
V
= V x 0.1, V = V x 0.9
SB1
CC
IL
CC
IH
CC
(standby)
f
= 400 kHz, f
= 400 kHz
SCL
SDA
V
supply current
V
= V
= V
SB2
CC
SDA
SCC CC
(standby)
Other = GND or V –0.3V
CC
I
Input leakage current
Output leakage current
Input LOW voltage
Input HIGH voltage
Output LOW voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
(2)
V
–0.5
V
x 0.1
CC
IL
(2)
V
V
x 0.9 V + 0.5
CC CC
V
IH
V
0.4
V
I
= 3mA
OL
OL
CAPACITANCE T = +25°C, F = 1MHZ, V
= 5V
A
CC
Symbol
Test
Max.
Unit
pF
Conditions
(3)
C
Output Capacitance (SDA)
8
6
V
= 0V
= 0V
OUT
I/O
(3)
C
Input Capacitance (RST, SCL)
pF
V
IN
IN
Notes: (1) Must perform a stop command after a read command prior to measurement
(2) V min. and V max. are for reference only and are not tested.
IL
IH
(3) This parameter is periodically sampled and not 100% tested.
Characteristics subject to change without notice. 8 of 16
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X76F200
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
5V
3V
Input rise and fall times
Input and output timing level
Output load
10ns
1.53KΩ
1.3KΩ
V
x 0.5
CC
Output
Output
100pF
100pF
100pF
AC CHARACTERISTICS (T = -40°C to +85°C, V
= +2.0V to +5.5V, unless otherwise specified.)
A
CC
Symbol
Parameter
Min.
Max.
Unit
MHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
ns
ns
ns
µs
ns
f
SCL clock frequency
SCL LOW to SDA data out valid
0
1
SCL
t
0.1
0.9
AA(2)
t
Time the bus must be free before a new transmission can start
Start condition hold time
1.2
BUF
t
t
0.6
HD:STA
t
Clock LOW period
1.2
LOW
t
Clock HIGH period
0.6
HIGH
Start Condition setup time (for a repeated start condition)
Data In hold time
0.6
SU:STA
HD:DAT
t
10
t
Data In setup time
100
SU:DAT
(1)
(1)
t
SDA and SCL rise time
20+0.1 x C
300
300
R
b
b
t
SDA and SCL fall time
20+0.1 x C
F
t
Stop condition setup time
0.6
0
SU:STO
t
Data out hold time
DH
t
RST to SCL non-overlap
500
0
NOL
RDV
CDV
t
t
RST LOW to SDA valid during response to reset
CLK LOW to SDA valid during response to reset
RST high time
450
450
0
t
1.5
500
RST
t
RST setup time
SU:RST
Notes: (1) C = total capacitance of one bus line in pF
b
(2) t = 1.1µs Max below V = 2.0V.
AA
CC
RESET AC SPECIFICATIONS
Power Up Timing
Symbol
Parameter
Min.
Typ.(2)
Max.
Unit
(1)
t
Time from power up to read
Time from power up to write
1
5
ms
ms
PUR
(1)
t
PUW
Notes: (1) Delays are measured from the time V
is stable until the specified operation can be initiated. These parameters are periodically
CC
sampled and not 100% tested.
(2) Typical values are for T = 25°C and V = 5.0V
A
CC
Characteristics subject to change without notice. 9 of 16
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X76F200
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min.
Typ.(1)
Max.
Unit
(1)
t
Write cycle time
5
10
ms
WC
Note: (1) t
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
WC
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Bus Timing
t
t
t
R
t
HIGH
LOW
F
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA IN
t
t
t
BUF
AA
DH
SDA OUT
Write Cycle Timing
SCL
8th Bit of Last Byte
ACK
SDA
t
WC
Stop
Condition
Start
Condition
RST Timing Diagram—Response to a Synchronous Reset
RST
t
RST
t
t
HIGH_RST
t
NOL
NOL
nd
2
rd
3
1st
clk
pulse
CLK
I/O
clk
clk
Pulse
Pulse
t
LOW_RST
t
SU:RST
t
t
CDV
RDV
Data Bit (2)
Data Bit (1)
Characteristics subject to change without notice. 10 of 16
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X76F200
Guidelines for Calculating Typical Values of Bus Pull Up Resistors
100
V
CCMAX
80
60
40
20
R
= -------------------------- = 1 . 8 KΩ
MIN
R
MAX
I
OLMIN
t
R
R
= -----------------
MAX
R
C
MIN
BUS
20 40 60 80 100
t
= maximum allowable SDA rise time
R
Bus Capacitance in pF
Characteristics subject to change without notice. 11 of 16
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X76F200
PACKAGING INFORMATION
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
Pin 1 Index
Pin 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) Ref.
Half Shoulder Width On
All End Pins Optional
0.145 (3.68)
0.128 (3.25)
Seating
Plane
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.150 (3.81)
0.125 (3.18)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
.073 (1.84)
Max.
0°
Typ. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 12 of 16
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X76F200
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" Typical
X 45°
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 13 of 16
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X76F200
PACKAGING INFORMATION
8-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.114 (2.9)
.122 (3.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
(7.72)
(4.16)
Detail A (20X)
(1.78)
(0.42)
.031 (.80)
.041 (1.05)
(0.65)
All Measurements Are Typical
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 14 of 16
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X76F200
PACKAGING INFORMATION
8 Contact Module
6 Contact Module
11.4
8
0.15
0.2
1.215
1.3
1.3
2.54
2.54
35mm TAPE
35mm TAPE
1.422
Reject
Punch
Position
8.82
23.02
35
NOTE: ALL MEASUREMENTS IN MILLIMETERS
Characteristics subject to change without notice. 15 of 16
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X76F200
Ordering Information
X76F200
X
X
–X
Device
V
Limits
CC
Blank = 5V 10%
2.0 = 2.0V to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial= –40°C to +85°C
Package
S8 = 8-Lead SOIC
P = 8-Lead PDIP
V8 = 8-Lead TSSOP
H = Die in Waffle Packs
W = Die in Wafer Form
X = Smart Card Module
Part Mark Convention
8-Lead SOIC/PDIP
8-Lead TSSOP
Blank = 8-Lead SOIC
X76F200 X
XX
EYWW
XXX
D = 2.0 to 5.5V, 0 to +70°C
E =
2.0 to 5.5V, -40 to +85°C
Blank = 4.5 to 5.5V, 0 to +70°C
I = 4.5 to 5.5V, -40 to +85°C
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 16 of 16
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