X84129ZI-2.5 [XICOR]
EEPROM, 16KX8, Serial, CMOS, PBGA8, XBGA-8;
| 型号： | X84129ZI-2.5 |
| 厂家： | 
XICOR INC. |
| 描述： | EEPROM, 16KX8, Serial, CMOS, PBGA8, XBGA-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总15页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTE
A V A I L A B L E
AN95 • AN103 • AN107
128K
MPS™ EEPROM
X84129
µPort Saver EEPROM
DESCRIPTION
FEATURES
• Up to 10MHz data transfer rate at 5V operator
• 25ns Read Access Time
• Direct interface to microprocessors and micro-
controllers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low power CMOS
The µPort Saver memories need no serial ports or
special hardware and connect to the processor mem-
ory bus. Replacing bytewide data memory, the µPort
Saver uses bytewide memory control functions, takes
a fraction of the board space and consumes much less
power. Replacing serial memories, the µPort Saver
provides all the serial benefits, such as low cost, low
power, low voltage, and small package size, while
releasing I/Os for more important uses.
—2.5V–5.5V version
—Standby current less than 1µA
—Active current less than 1mA
• Byte or page write capable
—32-byte page write mode
• Typical nonvolatile write cycle time: 2ms
• High reliability
—100,000 endurance cycles
—Guaranteed data retention: 100 years
• Small packages options
The µPort Saver memory outputs data within 25ns of
an active read signal. This is less than the read access
time of most hosts and provides “no-wait-state” opera-
tion. This prevents bottlenecks on the bus. With rates
to 10MHz, the µPort Saver supplies data faster than
required by most host read cycle specifications. This
eliminates the need for software NOPs.
The µPort Saver memories communicate over one line
of the data bus using a sequence of standard bus read
and write operations. This “bit serial” interface allows
the µPort Saver to work well in 8-bit, 16-bit, 32-bit, and
64-bit systems.
—8-lead XBGA package
—14-lead SOIC package
—28-lead TSSOP package
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
BLOCK DIAGRAM
Internal Block Diagram
MPS
System Connection
H.V. Generation
Timing & Control
WP
A
µP
µC
15
A
D
0
DSP
ASIC
RISC
CE
I/O
OE
7
Command
Decode
and
Control
Logic
EEPROM
Array
X
DEC
D
0
16K x 8
P0/CS
P1/CLK
P2/DI
OE
Ports
Saved
WE
WE
P3/DO
Y Decode
Data Register
Characteristics subject to change without notice. 1 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
PIN CONFIGURATIONS
14-Lead SOIC
28-Lead TSSOP
28
8-Lead XBGA: Top View
V
14
1
2
3
4
5
NC
NC
NC
CE
I/O
NC
NC
CC
NC
NC
CE
CE
CE
I/O
NC
NC
NC
WP
1
2
3
4
5
6
7
8
9
10
27
26
25
24
V
I/O
1 8
13
12
11
10
9
CC
NC
NC
NC
NC
OE
2
7
NC
NC
CE
V
V
CC
X84129
3
4
6
5
SS
NC
NC
NC
WE
OE
23
22
21
20
19
18
17
16
15
X84129
NC
WP
WP
6
7
WE
NC
OE
WE
NC
NC
NC
V
8
SS
X84129Z
V
NC
11
12
13
14
SS
NC
NC
PIN NAMES
Write Enable (WE)
The Write Enable input must be LOW to write either
data or command sequences to the device.
Pin
I/O
Description
Data Input/Output
Data In/Data Out (I/O)
CE
OE
WE
WP
Chip Enable Input
Output Enable Input
Write Enable Input
Write Protect Input
Supply Voltage
Ground
Data and command sequences are serially written to
or serially read from the device through the I/O pin.
Write Protect (WP)
V
CC
When the Write Protect input is LOW, nonvolatile writes
to the device are disabled. When WP is HIGH, all func-
tions, including nonvolatile writes, operate normally. If a
nonvolatile write cycle is in progress, WP going LOW
will have no effect on the cycle already underway, but
will inhibit any additional nonvolatile write cycles.
V
SS
NC
No Connect
PACKAGE SELECTION GUIDE
84129
8-Lead XBGA
14-Lead SOIC
28-Lead TSSOP
DEVICE OPERATION
The X84129 are serial EEPROMs designed to inter-
face directly with most microprocessor buses. Stan-
dard CE, OE, and WE signals control the read and
write operations, and a single l/O line is used to send
and receive data and commands serially.
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese-
lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
device is in the standby power mode.
Data Timing
Data input on the l/O line is latched on the rising edge
of either WE or CE, whichever occurs first. Data output
on the l/O line is active whenever both OE and CE are
LOW. Care should be taken to ensure that WE and OE
are never both LOW while CE is LOW.
Output Enable (OE)
The Output Enable input must be LOW to enable the
output buffer and to read data from the device on the I/
O line.
Characteristics subject to change without notice. 2 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
Read Sequence
be read sequentially by continuing to issue read
cycles. When the highest address in the array is
reached, the address counter rolls over to address
$0000 and reading may be continued indefinitely.
A read sequence consists of sending a 16-bit address
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and
CE LOW, OE HIGH) to the part without a read cycle
between the write cycles. The address is sent serially,
most significant bit first, over the I/O line. Note that this
sequence is fully static, with no special timing restric-
tions, and the processor is free to perform other tasks
on the bus whenever the device CE pin is HIGH. Once
the 16 address bits are sent, a byte of data can be read
on the I/O line by issuing 8 separate read cycles (OE
and CE LOW, WE HIGH). At this point, writing a ‘1’ will
terminate the read sequence and enter the low power
standby state, otherwise the device will await further
reads in the sequential read mode.
Reset Sequence
The reset sequence resets the device and sets an
internal write enable latch. A reset sequence can be
sent at any time by performing a read/write “0”/read
operation (see Figs. 1 and 2). This breaks the multiple
read or write cycle sequences that are normally used
to read from or write to the part. The reset sequence
can be used at any time to interrupt or end a sequential
read or page load. As soon as the write “0” cycle is
complete, the part is reset (unless a nonvolatile write
cycle is in progress). The second read cycle in this
sequence, and any further read cycles, will read a
HIGH on the l/O pin until a valid read sequence (which
includes the address) is issued. The reset sequence
must be issued at the beginning of both read and write
sequences to be sure the device initiates these opera-
tions properly.
Sequential Read
The byte address is automatically incremented to the
next higher address after each byte of data is read.
The data stored in the memory at the next address can
Figure 1. Read Sequence
CE
OE
WE
"0"
A10
A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
A15 A14 A13 A12 A11
I/O (IN)
D7 D6 D5 D4 D3 D2 D1 D0
I/O (OUT)
RESET
When Accessing: X84129 Array: A15–A14=0
Load Address
Read Data
Characteristics subject to change without notice. 3 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
Figure 2. Write Sequence
CE
OE
WE
"0"
A10
I/O (IN)
A15 A14 A13 A12 A11
A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
"1"
"0"
I/O (OUT)
RESET
When Accessing: X84129 Array: A15–A14=0
Load Address
Load Data
START
Nonvolatile
Write
Write Sequence
A nonvolatile write cycle will not start if a partial or
incomplete write sequence is issued. The internal write
enable latch is reset when the nonvolatile write cycle is
completed and after an invalid write to prevent inad-
vertent writes. Note that this sequence is fully static,
with no special timing restrictions. The processor is
free to perform other tasks on the bus whenever the
chip enable pin (CE) is HIGH.
A nonvolatile write sequence consists of sending a
reset sequence, a 16-bit address, up to 32 bytes of
data, and then a special “start nonvolatile write cycle”
command sequence.
The reset sequence is issued first (as described in the
Reset Sequence section) to set an internal write
enable latch. The address is written serially by issuing
16 separate write cycles (WE and CE LOW, OE HIGH)
to the part without any read cycles between the writes.
The address is sent serially, most significant bit first, on
the l/O pin. Up to 32 bytes of data are written by issu-
ing a multiple of 8 write cycles. Again, no read cycles
are allowed between writes.
Nonvolatile Write Status
The status of a nonvolatile write cycle can be deter-
mined at any time by simply reading the state of the l/O
pin on the device. This pin is read when OE and CE
are LOW and WE is HIGH. During a nonvolatile write
cycle the l/O pin is LOW. When the nonvolatile write
cycle is complete, the l/O pin goes HIGH. A reset
sequence can also be issued during a nonvolatile write
cycle with the same result: I/O is LOW as long as a
nonvolatile write cycle is in progress, and l/O is HIGH
when the nonvolatile write cycle is done.
The nonvolatile write cycle is initiated by issuing a spe-
cial read/write “1”/read sequence. The first read cycle
ends the page load, then the write “1” followed by a
read starts the nonvolatile write cycle. The device rec-
ognizes 32-byte pages.
When sending data to the part, attempts to exceed the
upper address of the page will result in the address
counter “wrapping-around” to the first address on the
page, where data loading can continue. For this rea-
son, sending more than 256 consecutive data bits will
result in overwriting previous data.
Characteristics subject to change without notice. 4 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
Low Power Operation
Write Protection
The device enters an idle state, which draws minimal
current when:
The following circuitry has been included to prevent
inadvertent nonvolatile writes:
– an illegal sequence is entered. The following are the
more common illegal sequences:
– The internal Write Enable latch is reset upon power-up.
– A reset sequence must be issued to set the internal
write enable latch before starting a write sequence.
• Read/Write/Write—any time
– A special “start nonvolatile write” command
sequence is required to start a nonvolatile write
cycle.
• Read/Write ‘1’—When writing the address or writing
data.
• Write ‘1’—when reading data
– The internal Write Enable latch is reset automatically
at the end of a nonvolatile write cycle.
• Read/Read/Write ‘1’—after data is written to
device, but before entering the NV write sequence.
– The internal Write Enable latch is reset and remains
reset as long as the WP pin is LOW, which blocks all
nonvolatile write cycles.
– the device powers-up;
– a nonvolatile write operation completes.
– The internal Write Enable latch resets on an invalid
write operation.
While a sequential read is in progress, the device
remains in an active state. This state draws more cur-
rent than the idle state, but not as much as during a
read itself.To go back to the lowest power condition, an
invalid condition is created by writing a ‘1’ after the last
bit of a read operation.
Characteristics subject to change without notice. 5 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ....................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions (above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Terminal voltage with respect to V ..........–1V to +7V
SS
DC output current................................................. 5mA
Lead temperature (soldering, 10 seconds).........300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
Limits
X84129-2.5
2.5V to 5.5V
–40°C
D.C. OPERATING CHARACTERISTICS (V
= 5V ±10%)
CC
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
I
V
V
V
supply current (read)
1
mA
OE = V , WE = V , I/O = Open, CE clocking
@ 10MHz
CC1
CC
CC
CC
IL
IH
I
supply current (write)
2
mA
I
during nonvolatile write cycle all inputs
CC2
CC
at CMOS levels
CE = V , Other Inputs = V or V
SS
I
standby current
1
µA
µA
µA
V
SB1
CC
CC
I
Input leakage current
Output leakage current
Input LOW voltage
10
10
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
(1)
lL
V
–0.5
V
x 0.3
CC
(1)
V
Input HIGH voltage
Output LOW voltage
Output HIGH voltage
V
V
x 0.7
V
+ 0.5
V
IH
CC
CC
V
0.4
V
I = 2.1mA
OL
OL
V
– 0.8
V
I
= –1mA
OH
OH
CC
Note: (1) V Min. and V Max. are for reference only and are not tested.
IL
IH
Characteristics subject to change without notice. 6 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
D.C. OPERATING CHARACTERISTICS (V
= 2.5V to 5.5V)
CC
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
I
V
supply current
500
µA
OE = V , WE = V , I/O = Open, CE clocking
@ 5MHz
CC1
CC
IL
IH
(Read)
I
V
supply current
2
mA
I
during nonvolatile write cycle all inputs at
CC2
CC
CC
(Write)
CMOS levels
CE = V , Other inputs = V or V
SS
I
V
standby current
1
µA
µA
µA
V
SB1
CC
CC
CC
I
Input leakage current
Output leakage current
Input LOW voltage
10
10
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
(1)
lL
V
–0.5
V
x 0.3
CC
(1)
V
Input HIGH voltage
Output LOW voltage
Output HIGH voltage
V
V
x 0.7
V
+ 0.5
V
IH
CC
CC
V
0.4
V
I
I
= 1mA, V = 3V
OL CC
OL
V
– 0.4
= 5V
V
= –400µA, V = 3V
OH CC
OH
CC
CAPACITANCE T = +25°C, F = 1MHZ, V
A
CC
Symbol
Parameter
Max.
Unit
pF
Test Conditions
(2)
I/O
C
Input/Output capacitance
Input capacitance
8
6
V
= 0V
= 0V
I/O
(2)
IN
C
pF
V
IN
Note: (2) Periodically sampled, but not 100% tested.
POWER-UP TIMING
Symbol
Parameter
Power-up to read operation
Power-up to write operation
Max.
Unit
(3)
PUR
t
2
5
ms
ms
(3)
PUW
t
Note: (3) Time delays required from the time the V is stable until the specific operation can be initiated. Periodically sampled, but not 100% tested.
CC
A.C. CONDITIONS OF TEST
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
Input rise and fall times
Input and output timing levels
5ns
V
x 0.5
CC
Characteristics subject to change without notice. 7 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
EQUIVALENT A.C. LOAD CIRCUITS
2V
5V
3V
2.8KΩ
Output
5.6KΩ
2.06KΩ
2.39KΩ
Output
4.58KΩ
Output
3.03KΩ
30pF
30pF
30pF
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW to
HIGH
Will change
from LOW to
HIGH
May change
Will change
from HIGH to from HIGH to
LOW
LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Characteristics subject to change without notice. 8 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits–X84129†
V
= 2.5V – 5.5V
Max.
CC
Symbol
Parameter
Min.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Read cycle time
CE access time
OE access time
OE pulse width
200
RC
t
50
50
CE
t
OE
t
60
60
70
120
0
OEL
t
OE High recovery time
CE LOW time
OEH
t
LOW
t
CE HIGH time
HIGH
(4)
t
CE LOW to output in low Z
CE HIGH to output in high Z
OE LOW to output in low Z
OE HIGH to output in high Z
Output hold from CE or OE HIGH
WE HIGH setup time
LZ
(4)
HZ
t
0
30
30
(4)
OLZ
t
0
(4)
OHZ
t
0
t
0
OH
t
25
25
WES
t
WE HIGH hold time
WEH
Note: (4) Periodically sampled, but not 100% tested. t
and t
are measured from the point where CE or OE goes HIGH (whichever
OHZ
HZ
occurs first) to the time when I/O is no longer being driven into a 5pF load.
Contact factory for 10MHz X84129 availability
†
Read Cycle
t
RC
t
t
HIGH
LOW
t
CE
CE
WE
OE
t
WES
t
OEL
t
OEH
t
OE
t
WEH
t
OHZ
I/O
HIGH Z
Data
t
OH
t
t
OLZ
LZ
t
HZ
Characteristics subject to change without notice. 9 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
Write Cycle Limits–X84129
V
= 2.5V – 5.5V
CC
Symbol
Parameter
Nonvolatile write cycle time
Min.
Max.
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(5)
NVWC
t
5
t
Write cycle time
WE pulse width
200
40
150
0
WC
t
WP
t
WE HIGH recovery time
Write setup time
Write hold time
WPH
t
CS
t
0
CH
t
CE pulse width
40
150
25
25
20
5
CP
t
CE HIGH recovery time
OE HIGH setup time
OE HIGH hold time
Data setup time
CPH
t
OES
t
OEH
(6)
t
DS
(6)
DH
t
Data hold time
(7)
(7)
t
WP HIGH setup
WP HIGH hold
100
100
WPSU
WPHD
t
Notes: (5) t
is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the “start nonvolatile write
NVWC
cycle” sequence until the self-timed, internal nonvolatile write cycle is completed.
(6) Data is latched into the X84129 on the rising edge of CE or WE, whichever occurs first.
(7) Periodically sampled, but not 100% tested.
CE Controlled Write Cycle
t
CPH
t
CP
CE
t
t
OEH
OES
OE
WE
WP
I/O
t
CS
t
CH
t
WP
t
WPH
t
t
WPSU
WPHD
Data
t
t
DS
DH
HIGH Z
t
WC
Characteristics subject to change without notice. 10 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
WE Controlled Write Cycle
t
CPH
t
CP
CE
t
OES
t
OE
WE
WP
I/O
CS
t
CH
t
OEH
t
WPH
t
WP
t
WPHD
t
WPSU
t
t
DS
DH
HIGH Z
Data
t
WC
Characteristics subject to change without notice. 11 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
PACKAGING INFORMATION
8-Lead XBGA
8-Lead XBGA Package
X84129: Bottom View
Complete Part Number
Top Mark
1200±30
XAAG
XADF
X84129Z - 2.5
X84129ZI - 2.5
8-Lead XBGA: Top View
V
CC
I/O
CE
PIN 1
V
I/O
1 8
CC
7
6
2
3
4
NC
CE
V
NC
SS
WE
OE
5
WP
V
WE
SS
.078 in.
OE
WP
1982±30
1833±30
180±30
350±20
NOTE: ALL DIMENSIONS IN µM (to convert into inches, 1µm = 3.94 x 10-5 inch)
ALL DIMENSIONS ARE TYPICAL VALUES
Characteristics subject to change without notice. 12 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
PACKAGING INFORMATION
14-Lead Plastic Small Outline Gullwing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"Typical
0° – 8°
0.250"
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
0.030"Typical
14 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 13 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
PACKAGING INFORMATION
28-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.377 (9.60)
.385 (9.80)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
(7.72)
(4.16)
0° – 8°
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
(0.42)
Detail A (20X)
(0.65)
All Measurements are Typical
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 14 of 15
REV 1.1.2 9/8/00
www.xicor.com
X84129
Ordering Information
X84129
X
X
–X
V
Range
CC
Device
2.5 = 2.5V to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Packages
X84129
S14 = 14-Lead SOIC
V28 = 28-Lead TSSOP
Z = 8-Lead XBGA
Part Mark Convention
8-Lead XBGA Package
Complete Part Number
Top Mark
XAAG
XADF
X84129Z-2.5
X84129ZI-2.5
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 15 of 15
REV 1.1.2 9/8/00
www.xicor.com
相关型号：
©2020 ICPDF网 联系我们和版权申明