X9118TXXXI [XICOR]
Digital Potentiometer, 1 Func, 100000ohm, 2-wire Serial Control Interface, 1024 Positions, CMOS, XBGA;
| 型号： | X9118TXXXI |
| 厂家： | 
XICOR INC. |
| 描述： | Digital Potentiometer, 1 Func, 100000ohm, 2-wire Serial Control Interface, 1024 Positions, CMOS, XBGA |
| 文件： | 总22页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTES AND DEVELOPMENT SYSTEM
A V A I L A B L E
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
Dual Supply / Low Power / 1024-tap / 2-Wire bus
X9118
Preliminary Information
Single Digitally-Controlled (XDCP™) Potentiometer
FEATURES
DESCRIPTION
• 1024 Resistor Taps – 10-Bit Resolution
• 2-Wire Serial Interface for write, read, and trans-
fer operations of the potentiometer
• Wiper Resistance, 40Ω Typical @ 5V
• Four Non-Volatile Data Registers for Each
Potentiometer
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads SavedWiper Position on
Power Up.
The X9118 integrates a single digitally controlled
potentiometer (XDCP) on
integrated circuit.
a
monolithic CMOS
The digital controlled potentiometer is implemented
using 1023 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface.The potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and a
four non-volatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the
contents of the default data register (DR0) to the WCR.
• Standby Current < 3µA Max
• System V : - 2.7V to 5.5V Operation
CC
• Analog V+/V-: -5V to +5V
• 100KΩ End to End Resistance
• Endurance: 100, 000 Data changes per bit per
register
• 100 yr. Data Retention
• 14-Lead TSSOP, xx-Lead XBGA
• Low power CMOS
The XDCP can be used as
a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
V
R
V+
CC
H
Write
Address
Data
Status
Power On Recall
100KΩ
Read
1024-taps
Transfer
Bus
Interface &
Control
Wiper Counter
Register (WCR)
2-Wire
Bus
Interface
POT
Wiper
Data Registers
(DR0-DR3)
Control
R
R
V-
V
NC
NC
W
L
SS
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X9118 – Preliminary Information
DETAILED FUNCTIONAL DIAGRAM
V
CC
V+
Power On
Recall
DR0 DR1
R
H
SCL
SDA
A1
Wiper
Counter
Register
(WCR)
Interface
and
Control
100KΩ
1024-taps
Data
R
DR2 DR3
L
Circuitry
A0
Control
R
W
WP
V
V-
SS
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
• Provide a control variable (I, V, or R) in feedback
circuits
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X9118 – Preliminary Information
PIN CONFIGURATION
TSSOP
XBGA
X9118
V+
NC
14
13
12
11
10
1
2
3
4
5
6
7
V
CC
R
R
R
L
A0
SCL
WP
H
W
X9118
NC
A1
V-
SDA
9
8
V
SS
PIN ASSIGNMENTS
Pin
Pin
(XBGA)
(TSSOP)
Symbol
V+
Function
1
2
Analog Supply Voltage
No Connect
NC
3
A0
Device Address for 2-wire bus
Serial Clock for 2-wire bus
Hardware Write Protect
4
SCL
WP
5
6
SDA
Serial Data Input/Output for 2-wire bus
System Ground
7
V
SS
8
V-
Analog Supply Voltage
9
A1
Device Address for 2-wire bus
No Connect
10
11
12
13
14
NC
R
Wiper terminal of the Potentiometer
High terminal of the Potentiometer
Low terminal of the Potentiometer
System Supply Voltage
W
R
H
R
L
V
CC
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X9118 – Preliminary Information
PIN DESCRIPTIONS
ANALOG SUPPLY VOLTAGES (V+ AND V-)
Bus Interface Pins
These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper
switches while the V- supply is used to bias the
switches and the internal P+ substrate of the integrated
circuit. Both of these supplies set the voltage limits of
the potentiometer.
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin
for a 2-wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.
Other Pins
NO CONNECT
No connect pins should be left open. These pins are
used for Xicor manufacturing and testing purposes.
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor.
For selecting typical values, refer to the guidelines for
calculating typical values on the bus pull-up resistors
graph.
PRINCIPLES OF OPERATION
The X9118 is an integrated microcircuit incorporating a
resistor array and their its registers and counters and
the
serial
interface
logic
providing
direct
communication between the host and the digitally
controlled potentiometer. This section provides detail
description of the following:
SERIAL CLOCK (SCL)
This input is used by 2-wire master to supply 2-wire
serial clock to the X9118.
– Resistor Array Description
DEVICE ADDRESS (A1–A0)
– Serial Interface Description
– Instruction and Register Description
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9118. A maximum of 4 XDCP devices may
occupy the 2-wire serial bus.
Resistor Array Description
The X9118 is comprised of a resistor array. The array
contains 1023, in effect, discrete resistive segments
that are connected in series (see Figure 1). The
physical ends of each array are equivalent to the fixed
HARDWARE WRITE PROTECT INPUT (WP)
terminals of a mechanical potentiometer (R and R
H
L
inputs).
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
At both ends of each array and between each resistor
segment is a CMOS switch (transmission gate)
Potentiometer Pins
connected to the wiper (R ) output. Within each
W
individual array only one switch may be turned on at a
time. These switches are controlled by the Wiper
Counter Register (WCR). The 10-bits of the WCR
(WCR[9:0]) are decoded to select, and enable, one of
1024 switches.
R , R
H
L
The R and R pins are equivalent to the terminal
connections on a mechanical potentiometer.
H
L
R
W
The WCR may be written directly. The Data Registers
and the WCR can be read and written by the host
system.
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (V
) AND SUPPLY GROUND (V )
SS
CC
The V
pin is the system or digital supply voltage.
CC
The V pin is the system ground.
SS
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X9118 – Preliminary Information
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
R
Serial
Bus
Input
H
From Interface
Circuitry
C
O
U
N
T
Register 0
(DR0)
Register 1
(DR1)
10
10
Parallel
Bus
Input
E
R
Register 2
(DR2)
Register 3
(DR3)
Wiper
D
E
C
O
D
E
Counter
Register
(WCR)
If WCR = 000[HEX] then R = R
W
L
If WCR = 3FF[HEX] then R = R
W
H
R
R
L
W
Serial Interface Description
STOP CONDITION
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 3.
SERIAL INTERFACE – 2-WIRE
The X9118 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9118 will be considered a
slave device in all applications.
ACKNOWLEDGE
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 3.
The X9118 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9118 will respond with a final acknowledge.
See Figure 2.
START CONDITION
All commands to the X9118 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9118 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is met.
See Figure 3.
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X9118 – Preliminary Information
Figure 2. Acknowledge Response from Receiver
SCL from
1
8
9
Master
Data Output
from Transmitter
Data Output
from Receiver
START
ACKNOWLEDGE
ACKNOWLEDGE POLLING
FLOW 1. ACK Polling Sequence
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9118
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9118 is still busy with the write operation no ACK
will be returned. If the X9118 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
Issue STOP
ACK
No
Returned?
Yes
Further
Operation?
No
Yes
Issue
Instruction
Issue STOP
Proceed
Proceed
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X9118 – Preliminary Information
Instruction and Register Description
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A1-A0 inputs can
DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)
be actively driven by CMOS input signals or tied to V
CC
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier. The ID[3:0] bits is the device id for the
X9118; this is fixed as 0101[B] (refer to Table 1).
or V . The R/W bit is the LSB and is used to set the
SS
device for read or write operations.
INSTRUCTION BYTE AND REGISTER SELECTION
The next byte sent to the X9118 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[2:0]). The RB and RA bits point to one of the
four registers.The format is shown below in Table 2.
The A[1:0] bits in the ID byte are the internal slave
address. The physical device address is defined by the
state of the A1-A0 input pins. The slave address is
externally specified by the user. The X9118 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9118 to successfully continue the command
Table 3 provides a complete summary of the
instruction set opcodes.
Table 1. Identification Byte Format
Internal Slave
Address
Device Type
Identifier
Read or
Write Bit
ID3
0
ID2
1
ID1
0
ID0
1
0
A1
A0
R/W
(MSB)
(LSB)
Table 2. Instruction Byte Format
Register
Selection
Instruction
Opcode
I2
I1
I0
0
RB
RA
0
0
(MSB)
(LSB)
Register Selected
RB
0
RA
DR0
DR1
DR2
DR3
0
1
0
1
0
1
1
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X9118 – Preliminary Information
Table 3. Instruction Set
Instruction Set
Instruction
R/W
I
I
I
0
RB RA
0
0
Operation
2
1
0
Read Wiper Counter
Register
1
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
Read the contents of the Wiper Counter
Register
Write Wiper Counter
Register
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write new value to the Wiper Counter
Register
Read Data Register
1/0 1/0
1/0 1/0
1/0 1/0
Read the contents of the Data Register
pointed to RB-RA.
Write Data Register
Write new value to the Data Register
pointed to RB-RA.
XFR Data Register to
Wiper Counter Register
Transfer the contents of the Data Register
pointed to by RB-RA to the Wiper Counter
Register
XFR Wiper Counter
Register to Data Regis-
ter
0
1
1
1
0
1/0 1/0
0
0
Transfer the contents of the Wiper Counter
Register to the Data Register
pointed to by RB-RA.
Note: (1) 1/o = data is one or zero.
Instruction and Register Description
DEVICE ADDRESSING
with the value in DR0 upon power-up, this may be
different from the value present at power-down. Power-
up guidelines are recommended to ensure proper
loadings of the DR0 value into the WCR .
WIPER COUNTER REGISTER (WCR)
DATA REGISTERS (DR)
The X9118 contains a Wiper Counter Register (see
Table 4) for the XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of 1024
switches along its resistor array. The contents of the
WCR can be altered in one of three ways: (1) it may be
written directly by the host via the write Wiper Counter
Register instruction (serial load); (2) it may be written
indirectly by transferring the contents of one of four
associated Data Registers via the XFR Data register;
(3) it is loaded with the contents of its Data Register
zero (R0) upon power-up.
The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four data registers and the Wiper Counter Register. All
operations changing data in one of the Data Registers
is a nonvolatile operation and will take a maximum of
10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9118 is powered-
down. Although the register is automatically loaded
Bit 9–Bit 0 are used to store one of the 1024 wiper
position (0 ~1023).
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X9118 – Preliminary Information
Table 4. Wiper Control Register, WCR (10-bit), WCR9–WCR0: Used to store the current wiper position (Volatile, V)
WCR9
V
WCR8
V
WCR7
V
WCR6
V
WCR5
V
WCR4
V
WCR3
V
WCR2
V
WCR1
V
WCR0
V
(MSB)
(LSB)
Table 5. Data Register, DR (10-bit), Bit 9–Bit 0: Used to store wiper positions or data (Non-Volatile, NV)
Bit 9
NV
Bit 8
NV
Bit 7
NV
Bit 6
NV
Bit 5
NV
Bit 4
NV
Bit 3
NV
Bit 2
NV
Bit 1
NV
Bit 0
NV
MSB
LSB
Four of the six instructions are four bytes in length.
These instructions are:
Two instructions (see Figure 4) require a two-byte
sequence to complete. These instructions transfer data
between the host and the X9118; either between the
host and one of the Data Registers or directly between
the host and the Wiper Counter Register. These
instructions are:
– Read Wiper Counter Register – read the current
wiper position of the potentiometer,
– Write Wiper Counter Register – change current
wiper position of the potentiometer,
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the Wiper Counter Register.
– Read Data Register – read the contents of the
selected Data Register;
– Write Data Register – write a new value to the
selected Data Register.
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specified Data Register.
The basic sequence of the four byte instructions is
illustrated in Figure 3. These four-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a data register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
See Instruction format for more details.
Other
POWER UP AND DOWN REQUIREMENTS
wiper to this action will be delayed by t
. A transfer
WRL
At all times, the V+ voltage must be greater than or
equal to the voltage at R or R , and the voltage at R
from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
H
L
H
or R must be greater than or equal to the voltage at
minimum of t
to complete. The transfer can occur
L
WR
V-. During power up and power down, V , V+, and V-
between the potentiometer and one of its associated
registers.
CC
must reach their final values with 1msec of each
other.
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
0
1
0
1
0
0
0
0
0
S
T
A
R
T
ID3 ID2 ID1 ID0
Device ID
I2
I0
0
A1 A0 R/W
A
C
K
I1
RB RA
A
C
K
S
T
O
P
Internal
Address
Instruction
Opcode
Register
Address
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X9118 – Preliminary Information
Figure 4. Four-Byte Instruction Sequence (Write or Read for WCR or Data Registers)
SCL
0
0
1
0
1
0
0
X
X
0
X
0
X X
SDA
X
X X
A
C
K
A
C
K
S
T
A0
ID3 ID2ID1ID0 0 A1
R/W
0 RB RA 0
A
C
K
W W
W
C
R
7
W
C
R
6
W W W
W
C
R
2
W
C
R
1
W
C
R
0
I0
I2 I1
S
T
A
C
K
C
R
9
C
R
8
C
R
5
C
R
4
C
R
3
O
P
A
R
Instruction
Opcode
Internal
Address
Register
Address
Device ID
T
Wiper or Data
Position
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by Slave on SDA)
Wiper Position
(Sent by Slave on SDA)
S
T
A
R
T
S
A
C
K
S
M
A
C
K
M
A
C
K
S
T
O
P
A
C
K
W
C
R
8
W
C
R
9
W W W W W W W W
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
0
1
0
1
0
A 1 A 0
1
0
0
0
0
0
0
0
X X X X X X
Write Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by Master on SDA)
Wiper Position
(Sent by Master on SDA)
S
T
A
R
T
S
A
C
K
S
S
S S
A
C
K
A
C
K
A
C
K
T
O
P
W W
W W W W W W W W
C
R
9
C
R
8
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
0
1
0
1
0
A 1 A 0
1
0
1
0
0
0
0
0
X X X X X X
Read Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by Slave on SDA)
wiper position or data
S
T
A
R
T
(Sent by Slave on SDA)
S
S
A
C
K
M
A
C
K
M
A
C
K
S
T
O
P
A
C
K
W W
W W W W W W W W
C
R
9
C
R
8
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
0
1
0
1
0
A 1 A 0
1
0
1
0
RB RA
0
0
X X X X X X
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X9118 – Preliminary Information
Write Data Register (DR)
Device Type
Identifier
Device
Instruction
Opcode
Register
Wiper Position or Data
Wiper Position or Data
Addresses
Addresses
(Sent by Master on SDA)
(Sent by Master on SDA)
S
T
A
R
T
S
A
C
K
S
A
C
K
S
A
C
K
S
A
C
K
S
T
O
P
W W
W W W W W W W W
C
R
9
C
R
8
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
0
1
0
1
0 A 1 A 0
1
1
0
0 RB RA 0
0
X X X X X X
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Identifier
Device
Instruction
Opcode
Register
S
T
A
R
T
Addresses
Addresses
S
A
C
K
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
0
A 1 A 0
1
1
1
0
RB RA
0
0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
Identifier
Device
Instruction
Opcode
Register
S
T
A
R
T
Addresses
Addresses
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
0
A 1 A 0
1
1
0
0
RB RA
0
0
Notes: (1) “A1 ~ A0”: stand for the device addresses sent by the master.
(2) WCRx refers to wiper position data in the Wiper Counter Register
Characteristics subject to change without notice. 11 of 22
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X9118 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... –65°C to +135°C
Storage temperature......................... –65°C to +150°C
Voltage on SCL, SDA, or any address input
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
with respect to V ................................. –1V to +7V
SS
∆V = | (VH–VL) | ......................................................5V
Voltage on V+ (referenced to V )(4)......................10V
SS
Voltage on V- (referenced to V
)
(4) ..................... -10V
SS
(V+) – (V-)..............................................................12V
Any Voltage on R / R ............................................V+
H
L
Any Voltage on R / R ..............................................V-
L
H
Lead temperature (soldering, 10 seconds)........ 300°C
I
(10 seconds).................................................. 6mA
W
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
–40°C
Max.
+70°C
+85°C
Device
X9118
Supply Voltage (V ) Limits(4)
CC
5V 10%
X9118-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended industrial (2.7V) operation conditions unless otherwise stated.)
Limits
Symbol
R
Parameter
End to End Resistance
End to End Resistance Tolerance
Power Rating
Min.
Typ.
Max. Units
Test Conditions
100
kΩ
TOTAL
20
50
%
mW
mA
Ω
25°C, each pot
I
Wiper Current
3
500
100
+5.5
+5.5
-4.5
-2.7
V+
W
R
R
Wiper Resistance
150
40
Wiper Current = 3mA, V = 3V
CC
W
Wiper Resistance
Ω
I
=
3mA, V = 5V
CC
X9118(4)
X9118-2.7(4)
W
W
Vv+
Voltage on V+ pin
+4.5
+2.7
-5.5
-5.5
V-
V
Vv-
Voltage on V- pin
V
X9118
X9118-2.7
V
Voltage on any R or R Pin
V
V
= 0V
SS
TERM
H
L
Noise
-120
0.1
dBV
Ref: 1V
Resolution
%
Absolute Linearity(1)
1
MI(3)
R
– R
,
w(n)(actual)
w(n)(expected)
where n=8 to 1006
(5)
1.5
0.5
MI(3)
MI(3)
R
– R
w(n)(actual) w(n)(expected)
Relative Linearity(2)
R
– [R
+ MI], where
w(m + 1)
w(m)
m=8 to 1006
1
MI(3)
ppm/°C
ppm/°C
pF
R
w(m + 1)
– [R
+ MI](5)
w(m)
Temperature Coefficient of R
300
TOTAL
Ratiometric Temp. Coefficient
Potentiometer Capacitancies
20
C /C /C
W
10/10/25
See Macro model
H
L
Characteristics subject to change without notice. 12 of 22
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X9118 – Preliminary Information
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 1023 or (R – R ) / 1023, single pot
H
L
(4) V , V+, V- must reach their final values within 1 msec of each other.
CC
(5) n = 0, 1, 2, …,1023; m =0, 1, 2, …, 1022.
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
= 400KHz; V = +5.5V;
SDA = Open; (for 2-wire, Active, Read and
Volatile Write States only)
I
V
supply current
(active)
3
mA
f
SCL
CC1
CC
CC
I
V
supply current
5
3
mA
f
= 400KHz; V = +5.5V;
CC2
CC
SCL CC
(nonvolatile write)
SDA = Open; (for 2-wire, Active,
Non-volatile Write State only)
I
V
current
µA
V
= +5.5V; V = V or V ; SDA = V
;
SB
CC
CC
IN
SS
CC
CC
(standby)
(for 2-wire, Standby State only)
I
Input leakage current
10
10
µA
µA
V
V
= V to V
SS CC
LI
IN
I
Output leakage
current
= V to V
OUT SS CC
LO
V
Input HIGH voltage
Input LOW voltage
Output LOW voltage
Output HIGH voltage
V
x 0.7
V + 1
CC
V
V
V
IH
CC
V
–1
V
x 0.3
IL
CC
V
0.4
I
= 3mA
OL
OL
OH
V
ENDURANCE AND DATA RETENTION
Parameter
Minimum Endurance
Data Retention
Min.
100,000
100
Units
Data changes per bit per register
years
CAPACITANCE
Symbol
Test
Input/Output capacitance (SI)
Input capacitance (SCL, WP, A2, A1 and A0)
Max.
Units
pF
Test Conditions
= 0V
(6)
C
8
6
V
OUT
IN/OUT
(6)
C
pF
V
= 0V
IN
IN
POWER-UP TIMING
Symbol
Parameter
Power-up Rate
Min.
0.2
Max.
50
Units
V/ms
ms
(6)
t V
V
CC
r
CC
(7)
t
Power-up to Initiation of read operation
Power-up to Initiation of write operation
1
PUR
(7)
t
50
ms
PUW
Notes: (6) This parameter is not 100% tested
(7) t and t are the delays required from the time the (last) power supply (Vcc-) is stable until the specific instruction can be
PUR
PUW
issued.These parameters are periodically sampled and not 100% tested.
Characteristics subject to change without notice. 13 of 22
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X9118 – Preliminary Information
A.C. TEST CONDITIONS
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
Input rise and fall times
Input and output timing level
10ns
V
x 0.5
CC
EQUIVALENT A.C. LOAD CIRCUIT
5V
3V
SPICE Macromodel
1533Ω
867Ω
R
TOTAL
C
R
R
L
H
SDA OUTPUT
SDA OUTPUT
C
C
L
W
L
10pF
10pF
100pF
25pF
100pF
R
W
AC TIMINGHIGH-VOLTAGE WRITE CYCLE TIMING
Symbol Parameter
Min.
Max.
Units
f
t
t
t
t
t
t
t
t
t
t
t
t
Clock Frequency
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCL
Clock Cycle Time
2500
600
1300
600
600
600
100
0
CYC
Clock High Time
HIGH
LOW
SU:STA
HD:STA
SU:STO
SU:DAT
HD:DAT
R
Clock Low Time
Start Setup Time
Start Hold Time
Stop Setup Time
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
300
300
F
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
250
0
AA
DH
T
Noise Suppression Time Constant at SCL and SDA inputs
Bus Free Time (Prior to Any Transmission)
A0, A1 Setup Time
50
1300
0
I
t
t
t
BUF
SU:WPA
HD:WPA
A0, A1 Hold Time
0
Characteristics subject to change without notice. 14 of 22
REV 1.1.4 11/10/00
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X9118 – Preliminary Information
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Units
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min.
Max.
10
Units
µs
t
Wiper response time after the third (last) power supply is stable
5
5
WRPO
t
Wiper response time after instruction issued (all load
instructions)
10
µs
WRL
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Characteristics subject to change without notice. 15 of 22
REV 1.1.4 11/10/00
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X9118 – Preliminary Information
TIMING DIAGRAMS
Start and Stop Timing
(START)
(STOP)
t
t
F
R
SCL
t
t
t
SU:STO
SU:STA
HD:STA
t
t
F
R
SDA
Input Timing
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
Output Timing
SCL
SDA
t
t
DH
AA
Characteristics subject to change without notice. 16 of 22
REV 1.1.4 11/10/00
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X9118 – Preliminary Information
XDCP Timing (for All Load Instructions)
(STOP)
SCL
SDA
LSB
t
WRL
R
W
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(Any Instruction)
...
SDA
...
t
t
SU:WPA
HD:WPA
WP
A0, A1
.
Characteristics subject to change without notice. 17 of 22
REV 1.1.4 11/10/00
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X9118 – Preliminary Information
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
O
V
V (REG)
O
317
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj
O
2
1
S
O
2
1
2
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
V
S
O
100KΩ
–
+
V
O
TL072
R
R
1
2
10KΩ
10KΩ
+12V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
10KΩ
-12V
RL = {R /(R +R )} V (min)
L
1
1
2
O
Characteristics subject to change without notice. 18 of 22
REV 1.1.4 11/10/00
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X9118 – Preliminary Information
Application Circuits (Continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
R
2
O
1
3
–
+
R
V
O
V
S
R
2
R
4
R = R = R = R = 10kΩ
1
2
3
4
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
3
Z
IN
V
= G V
S
O
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
}
A
B
frequency ∝ R , R , C
1
2
amplitude ∝ R , R
A
B
Characteristics subject to change without notice. 19 of 22
REV 1.1.4 11/10/00
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X9118 – Preliminary Information
XX-ball BGA (X9118xxxxxxx)
a
a
l
j
m
k
b
b
f
Top View (Bump Side Down)
Side View (Bump Side Down)
Bottom View (Bump Side Up)
Note: Drawing not to scale
d
= Die Orientation mark
c
e
Millimeters
Nom.
Inches
Symbol
Min
Max
Min
Nom.
Max
Package Body Dimension X
Package Body Dimension Y
Package Height
a
b
c
d
e
f
Package Body Thickness
Ball Height
Ball Diameter
Total Ball Count
g
h
i
Ball Count X Axis
Ball Count Y Axis
Pins Pitch XAxis
j
Pins Pitch Y Axis
k
Edge to Ball Center (Corner)
Distance Along X
l
Edge to Ball Center (Corner)
Distance Along Y
m
Characteristics subject to change without notice. 20 of 22
REV 1.1.4 11/10/00
www.xicor.com
X9118 – Preliminary Information
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8 °
Seating Plane
.019 (.50)
.029 (.75)
DetailA (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 21 of 22
REV 1.1.4 11/10/00
www.xicor.com
X9118 – Preliminary Information
ORDERING INFORMATION
X9118
Y
P
T
V
V
Limits
CC
Device
Blank = 5V 10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
V14 = 14-Lead TSSOP
xxx = xxx-Lead XBGA
Potentiometer Organization
Pot
T =
100KΩ
PART MARK CONVENTION
xx Lead XBGA
X9118xxxx-2.7
X9118xxxx xx
X9118 xxxx
Top Mark
X9118xxxxx I-2.7
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 22 of 22
REV 1.1.4 11/10/00
www.xicor.com
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