X9221AWSI [XICOR]
Digital Potentiometer, 2 Func, 10000ohm, 2-wire Serial Control Interface, 64 Positions, CMOS, PDSO20, PLASTIC, SOIC-20;
| 型号： | X9221AWSI |
| 厂家： | 
XICOR INC. |
| 描述： | Digital Potentiometer, 2 Func, 10000ohm, 2-wire Serial Control Interface, 64 Positions, CMOS, PDSO20, PLASTIC, SOIC-20 光电二极管 |
| 文件： | 总15页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTE
A V A I L A B L E
AN20 • AN42–53 • AN71 • AN73 • AN88 • AN91–92 • AN99 • AN115 • AN120 • AN124 • AN133 • AN134
64 Taps, 2-Wire Serial Bus
X9221A
Dual Digitally Controlled Potentiometer (XDCP™)
FEATURES
DESCRIPTION
• Two XDCPs in one package
• 2-wire serial interface
• Register oriented format, 8 registers total
—Directly write wiper position
—Read wiper position
—Store as many as four positions per pot
• Instruction format
—Quick transfer of register contents to resistor
array
• Direct write cell
—Endurance–100,000 writes per bit per register
• Resistor array values
—2KΩ, 10KΩ, 50KΩ
• Resolution: 64 taps each pot
• 20-lead plastic DIP and 20-lead SOIC packages
The X9221A integrates two digitally controlled potenti-
ometers (XDCP) on a monolithic CMOS integrated
microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 2 non-
volatile Data Registers (DR0:DR1) that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array through the switches. Power up recalls the con-
tents of DR0 to the WCR.
The XDCP can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.
BLOCK DIAGRAM
Pot 0
V
V
CC
SS
R0
R2
V
/R
R1
R3
H0 H0
Wiper
Counter
Register
(WCR)
V
V
/R
L0 L0
/R
W0 W0
SCL
SDA
Interface
and
Control
Circuitry
A0
A1
A2
A3
8
Data
V
/R
H1 H1
R0
R2
R1
R3
Wiper
Counter
Register
(WCR)
Register
Array
Pot 1
V
V
/R
L1 L1
/R
W1 W1
Characteristics subject to change without notice. 1 of 15
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X9221A
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
PIN NAMES
Symbol
Description
Serial Clock
SCL
SDA
Serial Data
Address
The SCL input is used to clock data into and out of the
X9221A.
A0–A3
V
V
/R –V /R
,
Potentiometers
(terminal equivalent)
H0 H0 H1 H1
/R –V /R
L0 H0 L1 L0
Serial Data (SDA)
V
/R –V /R
Potentiometers
(wiper equivalent)
W0 W0 W1 W1
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical val-
ues, refer to the guidelines for calculating typical val-
ues on the bus pull-up resistors graph.
RES
Reserved (Do not connect)
PRINCIPLES OF OPERATION
The X9221A is a highly integrated microcircuit incor-
porating two resistor arrays, their associated registers
and counters and the serial interface logic providing
direct communication between the host and the XDCP
potentiometers.
Address
The Address inputs are used to set the least signifi-
cant 4 bits of the 8-bit slave address. A match in the
slave address serial data stream must be made with
the Address input in order to initiate communication
with the X9221A
Serial Interface
The X9221A supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro-
vide the clock for both transmit and receive operations.
Therefore, the X9221A will be considered a slave
device in all applications.
Potentiometer Pins
V /R (V /R –V /R ), V /R (V /R –V /R )
H
H
H0 H0 H1 H1
L
L
L0 L0 L1 L1
The V /R and V /R inputs are equivalent to the ter-
H
H
L
L
minal connections on either end of a mechanical
potentiometer.
V /R (V /R –V /R )
W0 W0 W1 W1
Clock and Data Conventions
W
W
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Data states on the SDA line can change only during
SCL LOW periods (t
). SDA state changes during
LOW
SCL HIGH are reserved for indicating start and stop
conditions.
PIN CONFIGURATION
Start Condition
DIP/SOIC
All commands to the X9221A are preceded by the
start condition, which is a HIGH to LOW transition of
V
/R
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
W0 W0
SDA while SCL is HIGH (t
). The X9221A continu-
V
/R
RES
RES
RES
A1
L0 L0
HIGH
ously monitors the SDA and SCL lines for the start
condition, and will not respond to any command until
this condition is met.
V
/R
H0 L0
A0
A2
X9221A
V
/R
A3
W1 W1
Stop Condition
V
/R
SCL
RES
RES
RES
L1 L1
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
V
/R
H1 H1
SDA
V
SS
Characteristics subject to change without notice. 2 of 15
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X9221A
Acknowledge
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9221A compares the
serial data stream with the address input state; a suc-
cessful compare of all four address bits is required for
the X9221A to respond with an acknowledge.
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and dur-
ing this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data. See Figure 7.
Acknowledge Polling
The disabling of the inputs, during the internal nonvola-
tile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the non-
volatile write command the X9221A initiates the inter-
nal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9221A is
still busy with the write operation no ACK will be
returned. If the X9221A has completed the write opera-
tion an ACK will be returned and the master can then
proceed with the next operation.
The X9221A will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the com-
mand byte. If the command is followed by a data byte
the X9221A will respond with a final acknowledge.
Array Description
The X9221A is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
Flow 1. ACK Polling Sequence
potentiometer (V /R and V /R inputs).
H
H
L
L
At both ends of each array and between each resistor
segment is a FET switch connected to the wiper (V /
Nonvolatile Write
Command Completed
Enter ACK Polling
W
R ) output. Within each individual array only one
W
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six least significant bits of the WCR are decoded to
select, and enable, one of sixty-four switches.
Issue
START
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
Issue Slave
Issue STOP
Address
NO
ACK
Returned?
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most signifi-
cant four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9221A this
is fixed as 0101[B].
YES
NO
Further
Operation?
YES
Figure 1. Slave Address
Issue
Instruction
Device Type
Identifier
Issue STOP
Proceed
0
1
0
1
A3
A2
A1
A0
Proceed
Device Address
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X9221A
Instruction Structure
the wiper to this action will be delayed t
. A trans-
STPWV
fer from WCR’s current wiper position to a data regis-
ter is a write to nonvolatile memory and takes a
The next byte sent to the X9221A contains the instruc-
tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of two pots and when applicable they
point to one of four associated registers. The format is
shown below in Figure 2.
minimum of t
to complete. The transfer can occur
WR
between either potentiometer and their associated
registers or it may occur between both of the potenti-
ometers and one of their associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9221A; either between the host and
one of the data registers or directly between the host
and the WCR. These instructions are: Read WCR,
read the current wiper position of the selected pot;
Write WCR, change current wiper position of the
selected pot; Read Data Register, read the contents of
the selected nonvolatile register; Write Data Register,
write a new value to the selected data register. The
sequence of operations is shown in Figure 4.
Figure 2. Instruction Byte Format
t
Potentiometer
Select
I3
I2
I1
I0
0
P0
R1
R0
Instructions
Register
Select
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9221A has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
The four high order bits define the instruction. The
sixth bit (P0) selects which one of the two potentiome-
ters is to be affected by the instruction. The last two
bits (R1 and R0) select one of the four registers that is
to be acted upon when a register oriented instruction
is issued.
(t
) while SDA is HIGH, the selected wiper will
HIGH
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a data register to a WCR is
essentially a write to a static RAM. The response of
move one resistor segment towards the V /R termi-
nal. Similarly, for each SCL clock pulse while SDA is
LOW, the selected wiper will move one resistor seg-
H
H
ment towards the V /R terminal. A detailed illustration
L
L
of the sequence and timing for this operation are
shown in Figures 5 and 6 respectively.
Figure 3. Two-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
I3 I2
I1 I0
0
P0 R1 R0
S
T
O
P
A
C
K
A
C
K
Characteristics subject to change without notice. 4 of 15
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X9221A
Figure 4. Three-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
I3 I2
I1 I0
0
P0 R1 R0
0
0
D5 D4 D3 D2 D1 D0
S
T
A
C
K
A
C
K
A
C
K
O
P
Figure 5. Increment/Decrement Command Sequined
e
SCL
SDA
X
X
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0
0
P0 R1 R0
A
C
K
I
I
I
D
E
C
1
D
E
C
n
S
T
N
C
1
N
C
2
N
C
n
O
P
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
Issued
t
CLWV
SCL
SDA
Voltage Out
V
/R
W
W
Characteristics subject to change without notice. 5 of 15
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X9221A
Table 1. Instruction Set
Instruction Format
Instruction
Read WCR
I
I
I
I
0
P
R
R
Operation
1/0 N/A(7) N/A Read the contents of the Wiper Counter Register
pointed to by P
3
2
1
0
0
1
0
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
Write WCR
0
0
0
0
0
1/0
1/0
1/0
1/0
1/0
N/A N/A Write new value to the Wiper Counter Register
pointed to by P
0
Read Data Register
Write Data Register
1/0
1/0
1/0
1/0
1/0
1/0 Read the contents of the Register pointed to by
P and R –R
0
1
0
1/0 Write new value to the Register pointed to by
P and R –R
0
1
0
XFR Data Register
to WCR
1/0 Transfer the contents of the Register pointed to
by P and R –R to its associated WCR
0
1
0
XFR WCR to Data
Register
1/0 Transfer the contents of the WCR pointed to by
P to the Register pointed to by R –R
0
1
0
Global XFR Data
Register to WCR
N/A N/A
N/A N/A
1/0 Transfer the contents of the Data Registers
pointed to by R –R of both pots to their
1
0
respective WCR
Global XFR WCR
to Data Register
1
0
0
0
0
1
0
0
1/0
1/0 Transfer the contents of all WCRs to their
respective data Registers pointed to by R –R
of both pots
1
0
Increment/
Decrement Wiper
0
1/0
N/A N/A Enable Increment/decrement of the WCR
pointed to by P
0
Note: (7) N/A = Not applicable or don’t care; that is, a data register is not involved in the operation and need not be addressed (typical)
Figure 7. Acknowledge Response from Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
Acknowledge
Characteristics subject to change without notice. 6 of 15
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X9221A
DETAILED OPERATION
The WCR is a volatile register; that is, its contents are
lost when the X9221A is powered-down. Although the
register is automatically loaded with the value in R0
upon power-up, it should be noted this may be different
from the value present at power-down.
Both XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
is comprised of a resistor array, a wiper counter regis-
ter and four data registers. A detailed discussion of the
register organization and array operation follows.
Data Registers
Each potentiometer has four nonvolatile data registers.
These can be read or written directly by the host and
data can be transferred between any of the four data
registers and the WCR. It should be noted all opera-
tions changing data in one of these registers is a non-
volatile operation and will take a maximum of 10ms.
Wiper Counter Register
The X9221A contains two wiper counter registers
(WCR), one for each XDCP potentiometer. The WCR
can be envisioned as a 6-bit parallel and serial load
counter with its outputs decoded to select one of sixty-
four switches along its resistor array. The contents of
the WCR can be altered in four ways: it may be written
directly by the host via the Write WCR instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated data registers
via the XFR Data Register instruction (parallel load); it
can be modified one step at a time by the Increment/
Decrement instruction; finally, it is loaded with the con-
tents of its data register zero (R0) upon power-up.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
Figure 8. Detailed Potentiometer Block Diagram
Serial Data Path
Serial
Bus
Input
V /R
H
H
From Interface
Circuitry
Register 0
Register 2
Register 1
Register 3
Parallel
Bus
Input
8
6
C
o
u
n
t
e
r
Wiper
Counter
Register
D
e
c
o
d
e
INC/DEC
Logic
If WCR = 00[H] then V /R = V /R
L
W
W
L
UP/DN
UP/DN
If WCR = 3F[H] then V /R = V /R
H
W
W
H
V /R
L
Modified SCL
L
CLK
V
/R
W
W
Characteristics subject to change without notice. 7 of 15
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X9221A
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ....................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Voltage on SCK, SCL or any address
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
indicated in the operational sections of this specifica-
tion) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
input with respect to V .........................–1V to +7V
SS
Voltage on any V /R , V /R or V /R
H
H
W
W
L
L
referenced to V ...................................+6V / –4.3V
SS
∆V = |V /R –V /R |........................................... 10.3V
H
H
L
L
Lead temperature (soldering, 10 seconds).........300°C
(10 seconds) ................................................. 6mA
I
W
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
Limits
X9221A
5V 10ꢀ
–40°C
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to End Resistance
Power Rating
Min.
Typ.
Max.
+20
50
Unit
ꢀ
Test Conditions
25°C, each pot
R
–20
TOTAL
mW
mA
Ω
I
Wiper Current
–3
+3
W
R
Wiper Resistance
40
130
+5
Wiper Current = 1mA
W
V
Voltage on any V /R , V /R or
–3.0
V
TERM
H
H
W
W
V /R Pin
L
L
Noise
≤120
dBV
ꢀ
Ref: 1V
Resolution
1.6
See Note 5
Absolute Linearity(1)
Relative Linearity(2)
–1
+1
MI(3)
MI(3)
V
V
–V
w(n)(actual) w(n)(expected)
–0.2
+0.2
–[V
]
w(n + 1)
w(n) + MI
Temperature Coefficient
300
ppm/°C See Note 5
ppm/°C See Note 5
Radiometric Temperature Coefficient
Potentiometer Capacitances
20
C /C /C
W
10/10/25
pF
See circuit #3
H
L
Characteristics subject to change without notice. 8 of 15
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X9221A
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
Min. Typ. Max. Unit
Test Conditions
l
Supply Current (Active)
3
mA
µA
µA
µA
V
f
= 100kHz, SDA = Open, Other Inputs = V
SS
CC
SCL
I
V
Current (Standby)
200
500
10
SCL = SDA = V , Addr. = V
CC SS
SB
CC
I
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
V
V
= V to V
SS CC
LI
IN
I
10
= V to V
OUT SS CC
LO
V
2
V
+ 1
CC
IH
V
–1
0.8
0.4
V
IL
V
Output LOW Voltage
V
I
= 3mA
OL
OL
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a poten-
tiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (V /R –V /R )/63, single pot
H
H
L
L
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
years
CAPACITANCE
Symbol
Parameter
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3 and SCL)
Max.
Unit
pF
Test Conditions
(5)
C
8
6
V
= 0V
= 0V
I/O
I/O
(5)
C
pF
V
IN
IN
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
Unit
ms
(6)
t
Power-up to initiation of read operation
Power-up to initiation of write operation
1
5
PUR
(6)
t
ms
PUW
t V
V
Power-up ramp rate
0.2
50
V/msec
R CC
CC
Notes: (5) This parameter is periodically sampled and not 100ꢀ tested.
(6) t and t are the delays required from the time V is stable until the specified operation can be initiated. These parameters
PUR
PUW
CC
are periodically sampled and not 100ꢀ tested.
Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V , then the potentiometer pins. It is suggested that V
CC
CC
reach 90ꢀ of its final value before power is applied to the potentiometer pins. The V
ramp rate specification
CC
should be met, and any glitches or slope changes in the V
should not reverse polarity by more than 0.5V.
line should be held to <100mV if possible. Also, V
CC
CC
Characteristics subject to change without notice. 9 of 15
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X9221A
A.C. CONDITIONS OF TEST
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
Input rise and fall times
Input and output timing levels
10ns
V
x 0.5
CC
SYMBOL TABLE
Circuit #3 SPICE Macro Model
Macro Model
WAVEFORM
INPUTS
OUTPUTS
R
H
TOTAL
Must be
steady
Will be
steady
R
R
H
L
C
C
L
10pF
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
C
W
10pF
25pF
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
R
W
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
N/A
Center Line
is High
Impedance
120
V
I
CC MAX
R
R
=
=1.8KΩ
MIN
Equivalent A.C. Test Circuit
100
80
OL MIN
t
R
=
MAX
5V
C
BUS
Max.
Resistance
60
40
20
0
1533Ω
SDA Output
Min.
100pF
Resistance
20 40 60 80
120
100
0
Bus Capacitance (pF)
Characteristics subject to change without notice. 10 of 15
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X9221A
A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated)
Limits
Reference
Figure
Symbol
Parameter
Min.
0
Max.
Unit
kHz
ns
f
SCL clock frequency
Clock LOW period
100
10
10
SCL
t
4700
4000
LOW
t
Clock HIGH period
ns
10
HIGH
t
SCL and SDA rise time
SCL and SDA fall time
1000
300
ns
10
R
t
ns
10
F
T
Noise suppression time constant (glitch filter)
Start condition setup time (for a repeated start condition)
Start condition hold time
100
ns
10
i
t
4700
4000
250
0
ns
10 & 12
10 & 12
10
SU:STA
HD:STA
SU:DAT
HD:DAT
t
t
ns
Data in setup time
ns
t
Data in hold time
ns
10
t
SCL LOW to SDA data out valid
Data out hold time
300
300
4700
4700
3500
ns
11
AA
DH
t
ns
11
t
Stop condition setup time
ns
10 & 12
10
SU:STO
t
Bus free time prior to new transmission
Write cycle time (nonvolatile write operation)
Wiper response time from stop generation
Wiper response from SCL LOW
ns
BUF
t
10
ms
µs
13
WR
t
1000
500
13
STPWV
t
µs
6
CLWV
Characteristics subject to change without notice. 11 of 15
REV 1.1.3 8/21/02
www.xicor.com
X9221A
TIMING DIAGRAMS
Figure 10. Input Bus Timing
t
t
R
t
LOW
t
F
HIGH
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA
(Data in)
t
BUF
Figure 11. Output Bus Timing
SCL
t
t
DH
AA
SDA
(ACK)
SDA
OUT
SDA
SDA
OUT
OUT
Figure 12. Start Stop Timing
START Condition
STOP Condition
SCL
t
t
t
HD:STA
SU:STO
SU:STA
SDA
(Data in)
Figure 13. Write Cycle and Wiper Response Timing
SCL
Clock 8
Clock 9
STOP
START
t
WR
SDA
ACK
SDA
IN
t
STPWV
Wiper
Output
Characteristics subject to change without notice. 12 of 15
REV 1.1.3 8/21/02
www.xicor.com
X9221A
PACKAGING INFORMATION
20-Lead Plastic Dual In-Line Package Type P
1.060 (26.92)
0.980 (24.89)
0.280 (7.11)
0.240 (6.096)
Pin 1 Index
Pin 1
—
0.900 (23.66)
Ref.
0.005 (0.127)
0.195 (4.95)
0.115 (2.92)
Seating
Plane
––
(3.81) 0.150
0.015 (0.38)
(2.92) 0.1150
0.10 (BSC)
(2.54)
0.022 (0.559)
0.014 (0.356)
0.070 (1.778)
0.045 (1.143)
0.300
(7.62) (BSC)
0°
15°
0.014 (0.356)
0.008 (0.2032)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 13 of 15
REV 1.1.3 8/21/02
www.xicor.com
X9221A
PACKAGING INFORMATION
20-Lead Plastic Small Outline Gull Wing Package Type S
0.393 (10.00)
0.420 (10.65)
0.290 (7.37)
0.299 (7.60)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.496 (12.60)
0.508 (12.90)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0.420"
0°–8°
0.007 (0.18)
0.011 (0.28)
0.015 (0.40)
0.050 (1.27)
0.030" Typical
20 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 14 of 15
REV 1.1.3 8/21/02
www.xicor.com
X9221A
Ordering Information
X9221A
Y
P
T
V
Device
V
Limits
CC
Blank = 5V 10ꢀ
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
P = 20-Lead Plastic DIP
S = 20-Lead SOIC
Potentiometer Organization
Pot 0 Pot 1
Y = 2K
2K
W = 10K 10K
U = 50K 50K
©Xicor, Inc. 2002 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 15 of 15
REV 1.1.3 8/21/02
www.xicor.com
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