X9241MPI [XICOR]
Quad E2POT⑩ Nonvolatile Digital Potentiometer; 四E2POT⑩非易失性数字电位计型号: | X9241MPI |
厂家: | XICOR INC. |
描述: | Quad E2POT⑩ Nonvolatile Digital Potentiometer |
文件: | 总16页 (文件大小:79K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
APPLICATION NOTES AND DEVELOPMENT SYSTEM
A V A I L A B L E
AN20 • AN42–48 • AN50–53 • AN73 • XK9241
Terminal Voltage ±5V, 64 Taps
X9241
Quad E2POT™ Nonvolatile Digital Potentiometer
FEATURES
DESCRIPTION
2
2
• Four E POTs in One Package
• Two-Wire Serial Interface
• Register Oriented Format
—Directly Write Wiper Position
—Read Wiper Position
The X9241 integrates four nonvolatile E POT digitally
controlled potentiometers on a monolithic CMOS micro-
circuit.
The X9241 contains four resistor arrays, each com-
posed of 63 resistive elements. Between each element
and at either end are tap points accessible to the wiper
elements. The position of the wiper element on the array
is controlled by the user through the two-wire serial bus
interface.
—Store as Many as Four Positions per Pot
• Instruction Format
—Quick Transfer of Register Contents to
Resistor Array
—Cascade Resistor Arrays
• Low Power CMOS
Eachresistorarrayhasassociatedwithitawipercounter
register and four 8-bit data registers that can be directly
written and read by the user. The contents of the wiper
counter register control the position of the wiper on the
resistor array.
• Direct Write Cell
—Endurance - 100,000 Data Changes per Register
—Register Data Retention - 100 years
2
• 16 Bytes of E PROM memory
• 3 Resistor Array Values
—2KΩ to 50KΩ Mask Programmable
—Cascadable For Values of 500Ω to 200KΩ
• Resolution: 64 Taps each Pot
• 20-Lead Plastic DIP, 20-Lead TSSOP and
20-Lead SOIC Packages
Thedataregistermaybereadorwrittenbytheuser. The
contents of the data registers can be transferred to the
wiper counter register to position the wiper. The current
wiper position can be transferred to any one of its
associated data registers.
The arrays may be cascaded to form resistive elements
with 127, 190 or 253 taps.
FUNCTIONAL DIAGRAM
VH2
R0 R1
WIPER
R0 R1
R2 R3
VH0
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT 2
COUNTER
REGISTER
VL2
VW2
(WCR)
VL0
VW0
R2 R3
SCL
SDA
A0
A1
INTERFACE
AND
CONTROL
CIRCUITRY
8
A2
A3
DATA
VH1
VH3
R0 R1
R2 R3
R0 R1
R2 R3
WIPER
COUNTER
REGISTER
(WCR)
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT 3
RESISTOR
ARRAY
POT 1
VL1
VW1
VL3
VW3
3864 ILL F07.1
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
3864-2.7 7/1/96 T0/C3/D3 NS
Characteristics subject to change without notice
1
X9241
PIN DESCRIPTIONS
PIN NAMES
Symbol
Description
Serial Clock
Host Interface Pins
Serial Clock (SCL)
SCL
SDA
Serial Data
Address
The SCL input is used to clock data into and out of the
X9241.
A0–A3
V
H0
–V V –V
L3
Potentiometers
H3, L0
(terminal equivalent)
Serial Data (SDA)
V
–V
Potentiometers
W0
W3
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs. An open drain output requires the use
of a pull-up resistor. For selecting typical values, refer
to the guidelines for calculating typical values on the
bus pull-up resistors graph.
(wiper equivalent)
3864 PGM T01
PRINCIPLES OF OPERATION
TheX9241isahighlyintegratedmicrocircuitincorporat-
ing four resistor arrays, their associated registers and
counters and the serial interface logic providing direct
Address
2
communicationbetweenthehostandtheE POTpoten-
The Address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with the
X9241.
tiometers.
Serial Interface
The X9241 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
ontothebusasatransmitterandthereceivingdeviceas
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. There-
fore, the X9241 will be considered a slave device in all
applications.
Potentiometer Pins
V (V – V ), V (V – V )
H
H0
H3
L
L0
L3
The VH and VL inputs are equivalent to the terminal
connections on either end of a mechanical potentiom-
eter.
V
W
(V – V
)
W3
W0
Clock and Data Conventions
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Data states on the SDA line can change only during
SCL LOW periods (t
). SDA state changes during
LOW
SCL HIGH are reserved for indicating start and stop
conditions.
PIN CONFIGURATION
DIP/SOIC/TSSOP
Start Condition
All commands to the X9241 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
VW0
VL0
VH0
A0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
VW3
VL3
VH3
A1
while SCL is HIGH (t
). The X9241 continuously
HIGH
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condition
is met.
A2
X9241
VW1
VL1
VH1
SDA
A3
Stop Condition
SCL
VW2
VL2
VH2
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
V
SS
3864 ILL F01A.2
2
X9241
Acknowledge
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9241 compares the
serial data stream with the address input state; a suc-
cessful compare of all four address bits is required for
the X9241 to respond with an acknowledge.
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data. See Figure 7.
Acknowledge Polling
The disabling of the inputs, during the internal non-
volatile write operation, can be used to take advantage
2
of the typical 5ms E PROM write cycle time. Once the
The X9241 will respond with an acknowledge after
recognitionofastartconditionanditsslaveaddressand
once again after successful receipt of the command
byte. If the command is followed by a data byte the
X9241 will respond with a final acknowledge.
stop condition is issued to indicate the end of the
nonvolatile write command the X9241 initiates the inter-
nalwritecycle.ACKpollingcanbeinitiatedimmediately.
This involves issuing the start condition followed by the
device slave address. If the X9241 is still busy with the
writeoperationnoACKwillbereturned. IftheX9241has
completed the write operation an ACK will be returned
and the master can then proceed with the next
operation.
Array Description
The X9241 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connectedinseries.Thephysicalendsofeacharrayare
equivalent to the fixed terminals of a mechanical poten-
Flow 1. ACK Polling Sequence
tiometer (V and V inputs).
H
L
NONVOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
At both ends of each array and between each resistor
segment is a FET switch connected to the wiper (V )
W
output. Withineachindividualarrayonlyoneswitchmay
be turned on at a time. These switches are controlled by
the Wiper Counter Register (WCR). The six least signifi-
cant bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
ISSUE
START
ISSUE SLAVE
ISSUE STOP
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
ADDRESS
ACK
NO
RETURNED?
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9241 this is
fixed as 0101[B].
YES
NO
FURTHER
OPERATION?
YES
Figure 1. Slave Address
DEVICE TYPE
IDENTIFIER
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
0
1
0
1
A3
A2
A1
A0
PROCEED
DEVICE ADDRESS
3864 ILL F01
3864 FHD F08
3
X9241
Instruction Structure
action will be delayed t
. A transfer from WCR
STPWV
current wiper position, to a data register is a write to
nonvolatile memory and takes a minimum of t to
The next byte sent to the X9241 contains the instruction
and register pointer information. The four most signifi-
cant bits are the instruction. The next four bits point to
one of four pots and when applicable they point to one
of four associated registers. The format is shown below
in Figure 2.
WR
complete. The transfer can occur between one of the
four potentiometers and one of its associated registers;
or it may occur globally, wherein the transfer occurs
between all four of the potentiometers and one of their
associated registers.
Figure 2. Instruction Byte Format
Four instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9241; either between the host and one of
the data registers or directly between the host and the
WCR. These instructions are: Read WCR, read the
current wiper position of the selected pot; Write WCR,
change current wiper position of the selected pot; Read
Data Register, read the contents of the selected non-
volatile register; Write Data Register, write a new value
to the selected data register. The sequence of opera-
tions is shown in Figure 4.
POTENTIOMETER
SELECT
I3
I2
I1
I0
P1
P0
R1
R0
INSTRUCTIONS
REGISTER
SELECT
3864 ILL F09.1
The Increment/Decrement command is different from
the other commands. Once the command is issued and
the X9241 has responded with an acknowledge, the
master can clock the selected wiper up and/or down in
one segment steps; thereby, providing a fine tuning
The four high order bits define the instruction. The next
two bits (P1 and P0) select which one of the four
potentiometers is to be affected by the instruction. The
last two bits (R1 and R0) select one of the four registers
that is to be acted upon when a register oriented instruc-
tion is issued.
capability to the host. For each SCL clock pulse (t
)
HIGH
while SDA is HIGH, the selected wiper will move one
Fourofthenineinstructionsendwiththetransmissionof
the instruction byte. The basic sequence is illustrated in
Figure 3. These two-byte instructions exchange data
between the WCR and one of the data registers. A
transfer from a data register to a WCR is essentially a
write to a static RAM. The response of the wiper to this
resistor segment towards the V terminal. Similarly, for
each SCL clock pulse while SDA is LOW, the selected
H
wiper will move one resistor segment towards the V
L
terminal. A detailed illustration of the sequence and
timing for this operation are shown in Figures 5 and 6
respectively.
Figure 3. Two-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0
P1 P0 R1 R0
A
C
K
S
T
O
P
3864 ILL F10
4
X9241
Figure 4. Three-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0
P1 P0 R1 R0
A
C
K
DW D5 D4 D3 D2
A
C
K
S
T
O
P
CM
D1 D0
3864 ILL F11
Figure 5. Increment/Decrement Command Sequence
SCL
SDA
X
X
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0
P1 P0 R1 R0
A
C
K
I
I
D
E
C
1
S
T
I
D
E
C
n
N
C
1
N
C
2
N
C
n
O
P
3864 FHD F12
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
ISSUED
t
CLWV
SCL
SDA
VOLTAGE OUT
V
W
3864 ILL F13
5
X9241
Table 1. Instruction Set
Instruction Format
Instruction
Read WCR
I3
I2
I1
I0
P1
P0
R1
(8)
Ro
N/A Read the contents of the Wiper Counter
Register pointed to by P –P
Operation
(7)
1
1
1
1
1
0
0
1
1/0
1/0 N/A
1
0
Write WCR
0
0
1
1
1
1
0
0
0
1
0
1
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
N/A N/A Write new value to the Wiper Counter
Register pointed to by P –P
1
0
Read Data
Register
1/0
1/0
1/0
1/0
1/0
1/0
Read the contents of the Register
pointed to by P –P and R –R
1
0
1
0
Write Data
Register
Write new value to the Register
pointed to by P –P and R –R
1
0
1
0
XFR Data Reg-
ister to WCR
Transfer the contents of the Register
pointed to by P –P and R –R
1
0
1
0
to its associated WCR
Transfer the contents of the WCR
pointed to by P –P to the Register
XFR WCR to
Data Register
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1
0
pointed to by R –R
1
0
Global XFR Data
Register to WCR
N/A N/A
N/A N/A
Transfer the contents of all four Data
Registers pointed to by R –R to their
1
0
respective WCR
Global XFR WCR
to Data Register
Transfer the contents of all WCRs
to their respective data Registers
pointed to by R –R
1
0
Increment/Decre-
ment Wiper
1/0
1/0
N/A N/A Enable Increment/decrement of the
WCR pointed to by P –P
1
0
3864 PGM T02.1
Notes: (7) 1/0 = data is one or zero
(8) N/A = Not applicable or don't care; that is, a data register is not involved in the operation and need not be addressed (typical)
Figure 7. Acknowledge Response from Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
3864 ILL F14
6
X9241
DETAILED OPERATION
The WCR is a volatile register; that is, its contents are
lost when the X9241 is powered-down. Although the
register is automatically loaded with the value in R0
upon power-up, it should be noted this may be different
from the value present at power-down.
2
All four E POT potentiometers share the serial interface
and share a common architecture. Each potentiometer
is comprised of a resistor array, a wiper counter register
and four data registers. A detailed discussion of the
register organization and array operation follows.
Data Registers
Each potentiometer has four nonvolatile data registers.
These can be read or written directly by the host and
data can be transferred between any of the four data
registers and the WCR. It should be noted all operations
changing data in one of these registers is a nonvolatile
operation and will take a maximum of 10ms.
Wiper Counter Register
TheX9241containsfourwipercounterregisters(WCR),
2
one for each E POT potentiometer. The WCR can be
envisionedasa6-bitparallelandserialloadcounterwith
its outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can be
altered in four ways: it may be written directly by the host
via the Write WCR instruction (serial load); it may be
written indirectly by transferring the contents of one of
fourassociateddataregistersviatheXFRDataRegister
instruction (parallel load); it can be modified one step at
a time by the Increment/ Decrement instruction; finally,
itisloadedwiththecontentsofitsdataregisterzero(R0)
upon power-up.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
Figure 8. Detailed Potentiometer Block Diagram
SERIAL DATA PATH
V
SERIAL
BUS
INPUT
H
FROM INTERFACE
CIRCUITRY
REGISTER 0
REGISTER 2
REGISTER 1
PARALLEL
BUS
INPUT
8
6
C
O
U
N
T
WIPER
COUNTER
REGISTER
REGISTER 3
E
R
D
E
C
O
D
E
2
INC/DEC
LOGIC
IF WCR = 00[H] THEN VW = VL
IF WCR = 3F[H] THEN VW = VH
UP/DN
UP/DN
V
V
L
MODIFIED SCL
CLK
DW
CASCADE
CONTROL
W
LOGIC
CM
3864 ILL F15
7
X9241
Cascade Mode
DW bit of the WCR is set to “0” the wiper is enabled;
when set to “1” the wiper is disabled. If the wiper is
disabled, the wiper terminal will be electrically isolated
and float.
The X9241 provides a mechanism for cascading the
arrays. That is, the sixty-three resistor elements of one
array may be cascaded (linked) with the resistor ele-
ments of an adjacent array.
When operating in cascade mode VH, VL and the wiper
terminals of the cascaded arrays must be electrically
connected externally. All but one of the wipers must be
disabled. The user can alter the wiper position by writing
directly to the WCR or indirectly by transferring the
contentsofthedataregisterstotheWCRorbyusingthe
Increment/Decrement command.
Cascade Control Bits
The data byte, for the three-byte commands, contains 6
bits (LSBs) for defining the wiper position plus two high
orderbits,CM(CascadeMode)andDW(DisableWiper).
The state of CM enables or disables (normal operation)
cascade mode. When the CM bit of the WCR is set to “0”
the potentiometer is in the normal operation mode.
WhentheCMbitoftheWCRissetto“1”thepotentiometer
is cascaded with its adjacent higher order potentiometer.
For example; if bit 7 of WCR2 is set to “1”, pot 2 will be
cascaded to pot 3.
When using the Increment/Decrement command the
wiper position will automatically transition between
arrays. The current position of the wiper can be deter-
mined by reading the WCR registers; if the DW bit is “0”,
the wiper in that array is active. If the current wiper
position is to be maintained, a global XFR WCR to Data
Register command must be issued before power-down.
ThestateofDWenablesordisablesthewiper.Whenthe
Figure 9. Cascading Arrays
VL0
VH0
POT 0
WCR0
VW0
VL1
POT 1
WCR1
VH1
VW1
VL2
POT 2
WCR2
VH2
VW2
VL3
POT 3
WCR3
VH3
EXTERNAL
=
VW3
CONNECTION
3864 ILL F16.1
8
X9241
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on SCK, SCL or any Address Input
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecificationis
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
with Respect to V ................................... –1V to +7V
SS
Voltage on any V or V Referenced to V ......... ±8V
H
L
SS
∆V = |V –V |......................................................... 16V
H
L
Lead Temperature (Soldering, 10 seconds)...... 300°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Limits
Temperature
Min.
Max.
X9241
5V ±10%
Commercial
Industrial
Military
0°C
+70°C
+85°C
3864 PGM T04.1
–40°C
–55°C
+125°C
3864 PGM T03
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to End Resistance
Power Rating
Min.
Typ.
Max.
+20
50
Units
%
Test Conditions
25°C, each pot
R
TOTAL
–20
mW
mA
Ω
I
Wiper Current
–1
–5
+1
W
R
W
Wiper Resistance
40
100
+5
Wiper Current = ± 1mA
V
TERM
Voltage on any V or
V
H
or V Pin
L
Noise
≤120
dB/
Ref: 1V
(4)
Resolution
1.6
0.4
+1
%
(1)
(3)
Absolute Linearity
Relative Linearity
–1
MI
MI
V – V
w(n)(actual) w(n)(expected)
(2)
(3)
–0.2
+0.2
V
– [V
]
w(n + 1)
w(n) + MI
Temperature Coefficient
±300
ppm/°C
3864 PGM T05.2
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
l
Supply Current (Active)
3
mA
f
= 100KHz, SDA = Open,
CC
SCL
Other Inputs = V
SS
I
I
I
V
Current (Standby)
200
500
10
µA
µA
µA
V
SCL=SDA=V , Addr. = V
CC SS
SB
CC
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
V
V
= V to V
SS CC
LI
IN
10
= V to V
SS CC
LO
OUT
V
V
V
2
V
+ 1
CC
IH
–1
0.8
0.4
V
IL
Output LOW Voltage
V
I
OL
= 3mA
OL
3864 PGM T06.3
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper
position when used as a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (V – V )/63, single pot
H
L
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
9
X9241
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum Endurance
Data Retention
100,000
100
Data Changes per Register
Years
3864 PGM T07.2
CAPACITANCE
Symbol
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3 and SCL)
Max.
Units
Test Conditions
= 0V
(5)
C
I/O
8
6
pF
pF
V
I/O
(5)
C
IN
V
IN
= 0V
3864 PGM T08
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(6)
t
t
Power-up to Initiation of Read Operation
Power-up to Initiation of Write Operation
1
5
ms
ms
PUR
(6)
PUW
3864 PGM T09
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. TEST CIRCUIT
Input Pulse Levels
V
CC
x 0.1 to V x 0.9
CC
5V
Input Rise and
Fall Times
10ns
1533Ω
Input and Output
Timing Levels
SDA OUTPUT
V
x 0.5
CC
3864 PGM T10
100pF
Notes: (5) This parameter is periodically sampled and not 100%
tested.
(6) t
and t
are the delays required from the time
PUW
PUR
3864 ILL F02.1
VCC is stable until the specified operation can be
initiated. These parameters are periodically sampled
and not 100% tested.
Guidelines for Calculating
SYMBOL TABLE
Typical Values of Bus Pull-Up Resistors
120
WAVEFORM
INPUTS
OUTPUTS
V
CC MAX
R
=
=1.8KΩ
MIN
I
100
80
OL MIN
Must be
steady
Will be
steady
t
R
R
=
MAX
C
BUS
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
MAX.
60
40
20
0
RESISTANCE
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
MIN.
RESISTANCE
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
20 40 60 80
120
100
0
BUS CAPACITANCE (pF)
N/A
Center Line
is High
Impedance
3864 ILL F17
10
X9241
A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated)
Limits
Reference
Symbol
fSCL
tLOW
tHIGH
tR
Parameter
SCL Clock Frequency
Min.
0
Max.
Units
KHz
ns
Figure
10
100
Clock LOW Period
4700
4000
10
Clock HIGH Period
ns
10
SCL and SDA Rise Time
SCL and SDA Fall Time
1000
300
ns
10
tF
ns
10
Ti
Noise Suppression Time Constant
(Glitch Filter)
100
ns
10
tSU:STA
Start Condition Setup Time (for a Repeated
Start Condition)
4700
ns
10 & 12
tHD:STA
tSU:DAT
tHD:DAT
tAA
Start Condition Hold Time
4000
250
0
ns
ns
10 & 12
10
Data in Setup Time
Data in Hold Time
ns
10
SCL LOW to SDA Data Out Valid
Data Out Hold Time
300
300
4700
4700
3500
ns
11
tDH
ns
11
tSU:STO
tBUF
Stop Condition Setup Time
ns
10 & 12
10
Bus Free Time Prior to New Transmission
Write Cycle Time (Nonvolatile Write Operation)
Wiper Response Time From Stop Generation
Wiper Response From SCL LOW
VCC Power-up Rate
ns
tWR
10
500
1000
50
ms
µs
13
tSTPWV
tCLWV
tR VCC
13
µs
6
0.2
mV/µs
3864 PGM T11.3
Figure 10. Input Bus Timing
t
t
t
t
HIGH
LOW
F
R
SCL
t
t
t
t
t
SU:STA
HD:STA
HD:DAT
SU:DAT
SU:STO
SDA
(DATA IN)
t
BUF
3864 ILL F03
11
X9241
Figure 11. Output Bus Timing
SCL
t
t
AA
DH
SDA
SDA
(ACK)
SDA
SDA
OUT
OUT
OUT
3864 ILL F04
Figure 12. Start Stop Timing
START CONDITION
STOP CONDITION
SCL
t
t
t
HD:STA
SU:STO
SU:STA
SDA
DATA IN
3864 ILL F05
Figure 13. Write Cycle and Wiper Response Timing
SCL
CLOCK 8
CLOCK 9
ACK
STOP
START
t
WR
SDA
SDA
IN
t
STPWV
WIPER
OUTPUT
3864 ILL F06
12
X9241
PACKAGING INFORMATION
20-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.060 (26.92)
0.980 (24.89)
0.280 (7.11)
0.240 (6.096)
PIN 1 INDEX
PIN 1
—
0.900 (23.66)
REF.
0.005 (0.127)
0.195 (4.95)
0.115 (2.92)
SEATING
PLANE
––
(3.81) 0.150
(2.92) 0.1150
0.015 (0.38)
0.10 (BSC)
(2.54)
0.022 (0.559)
0.014 (0.356)
0.070 (1.778)
0.045 (1.143)
0.300
(7.62) (BSC)
0°
0.014 (0.356)
0.008 (0.2032)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F18.1
13
X9241
PACKAGING INFORMATION
20-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.290 (7.37)
0.299 (7.60)
0.393 (10.00)
0.420 (10.65)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.50)
0.496 (12.60)
0.508 (12.90)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0° – 8°
0.420"
0.007 (0.18)
0.011 (0.28)
0.015 (0.40)
0.050 (1.27)
0.030" Typical
20 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F23
14
X9241
PACKAGING INFORMATION
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.252 (6.4)
.300 (6.6)
.047 (1.20)
.0075 (.19)
.002 (.05)
.0118 (.30)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F45
15
X9241
ORDERING INFORMATION
X9241
Y
P
T
V
V
Limits
Device
CC
Blank = 5V ±10%
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 20-Lead Plastic DIP
S = 20-Lead SOIC
V = 20-Lead TSSOP
Potentiometer Organization
Pot 0 Pot 1 Pot 2 Pot 3
Y = 2K
2K
2K
2K
W = 10K 10K 10K 10K
U = 50K 50K 50K 50K
M = 2K 10K 10K 50K
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
16
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