X9250US24I-2.7T2 [XICOR]
Digital Potentiometer, 4 Func, 50000ohm, 3-wire Serial Control Interface, 256 Positions, CMOS, PDSO24, PLASTIC, SOIC-24;
| 型号： | X9250US24I-2.7T2 |
| 厂家： | 
XICOR INC. |
| 描述： | Digital Potentiometer, 4 Func, 50000ohm, 3-wire Serial Control Interface, 256 Positions, CMOS, PDSO24, PLASTIC, SOIC-24 光电二极管 |
| 文件： | 总21页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTE
A V A I L A B L E
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Noise/Low Power/SPI Bus/256 Taps
X9250
Quad Digitally Controlled Potentiometers (XDCP™)
FEATURES
DESCRIPTION
• Four potentiometers in one package
• 256 resistor taps/pot–0.4% resolution
• SPI serial interface
The X9250 integrates
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
4
digitally controlled
• Wiper resistance, 40Ω typical @ V
= 5V
CC
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to
the wiper terminal through switches. The position of
the wiper on the array is controlled by the user through
the SPI bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and 4 nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power
up recalls the contents of DR0 to the WCR.
• Four nonvolatile data registers for each pot
• Nonvolatile storage of wiper position
• Standby current < 5µA max (total package)
• Power supplies
—V
= 2.7V to 5.5V
CC
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• 100KΩ, 50KΩ total pot resistance
• High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention – 100 years
• 24-lead SOIC, 24-lead TSSOP, 24-lead CSP (Chip
Scale Package)
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
• Dual supply version of X9251
BLOCK DIAGRAM
V
V
V+
V-
CC
Pot 0
SS
R
R
R
R
V /R
H0 H0
R
R
R
R
0
2
1
3
0
2
1
3
Wiper
V
/R
Wiper
Counter
Register
(WCR)
H2 H2
Resistor
Array
Pot 2
Counter
Register
(WCR)
V
/R
L0 L0
HOLD
V
/R
L2 L2
CS
SCK
SO
V
V
/R
W0 W0
V
/R
W2 W2
Interface
and
Control
SI
8
Circuitry
A0
A1
/R
W1 W1
Data
V
V
/R
W3 W3
WP
R
R
R
R
0
2
1
3
R
R
R
R
V
/R
Wiper
Counter
Register
(WCR)
0
2
1
3
H1 H1
/R
Wiper
Counter
Register
(WCR)
H3 H3
Resistor
Array
Pot1
Resistor
Array
Pot 3
V
/R
L1 L1
V
/R
L3 H3
Characteristics subject to change without notice. 1 of 21
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X9250
PIN DESCRIPTIONS
Serial Output (SO)
V /R (V /R –V /R
)
W
W
W0 W0 W3 W3
The wiper pins are equivalent to the wiper terminal of
a mechanical potentiometer.
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
Hardware Write Protect Input (WP)
Serial Input
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9250.
PIN CONFIGURATION
SOIC/TSSOP
Chip Select (CS)
When CS is HIGH, the X9250 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9250, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
S0
A0
1
2
24
23
22
21
20
19
18
17
16
15
HOLD
SCK
V
/R
3
V
V
V
/R
W3 W3
L2 L2
V
/R
4
/R
H3 H3
H2 L2
/R
5
V
/R
W2 W2
L3 L3
V–
V+
6
X9250
V
7
V
V
V
CC
SS
V
/R
/R
8
L0 L0
Hold (HOLD)
W1 W1
/R
V
/R
9
H1 H1
H0 H0
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
V
/R
10
V
/R
W0 W0
L1 L1
CS
11
12
14
13
A1
SI
WP
CSP
2
1
3
4
A
R
R
L1
CS
W0
1
A
B
C
D
E
F
R
R
SI
W1
Device Address (A –A )
L0 WP
0
1
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9250. A maximum of 4 devices may occupy the
SPI serial bus.
V
R
H0
R V
H1 SS
CC
R
R
V+
R
V-
H2
H3
SO HOLDR
L3
W2
L2
R
A SCK R
0
W3
Potentiometer Pins
Top View–Bumps Down
V /R (V /R –V /R ), V /R (V /R –V /R )
H
H
H0 H0 H3 H3
L
L
L0 L0 L3 L3
The R and R pins are equivalent to the terminal
H
L
connections on a mechanical potentiometer.
Characteristics subject to change without notice. 2 of 21
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X9250
PIN NAMES
Wiper Counter Register (WCR)
The X9250 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of 256 switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by the
host via the write Wiper Counter Register instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated Data Registers
via the XFR Data Register or Global XFR Data
Register instructions (parallel load); it can be modified
one step at a time by the increment/decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon power-up.
Symbol
Description
Serial Clock
SCK
SI, SO
Serial Data
A -A
Device Address
0
1
V
V
/R
/R
V
/R
,
Potentiometer Pins
(terminal equivalent)
H0 H0– H3 H3
V /R
L0 L0– L3 L3
V
/R
V
/R
Potentiometer Pins
(wiper equivalent)
W0 W0– W3 W3
WP
Hardware Write Protection
Analog Supplies
V+,V-
V
System Supply Voltage
System Ground
CC
V
SS
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9250 is powered-
down. Although the register is automatically loaded
with the value in R0 upon power-up, this may be
different from the value present at power-down.
NC
No Connection
DEVICE DESCRIPTION
Serial Interface
Data Registers
The X9250 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Array Description
The X9250 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
Data Register Detail
potentiometer (V /R and V /R inputs).
H
H
L
L
(MSB)
D7
(LSB)
D0
D6
D5
D4
NV
D3
NV
D2
NV
D1
NV
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
NV
NV NV
NV
(V /R ) output. Within each individual array only one
W
W
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8 bits of the WCR are decoded
to select, and enable, one of 256 switches.
Characteristics subject to change without notice. 3 of 21
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X9250
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
V /R
H H
Serial
Bus
Input
From Interface
Circuitry
C
o
u
n
t
Register 0
Register 2
Register 1
8
8
Parallel
Bus
Input
e
r
Wiper
Counter
Register
(WCR)
D
e
c
o
d
e
Register 3
Inc/Dec
Logic
If WCR = 00[H] then V /R = V /R
L
W
W
L
UP/DN
UP/DN
If WCR = FF[H] then V /R = V /R
H
W
W
H
V /R
L
L
Modified SCK
CLK
V
/R
W
W
Write in Process
Figure 2. Identification Byte Format
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
Device Type
Identifier
0
1
0
1
0
0
A1
A0
Device Address
INSTRUCTIONS
Instruction Byte
The next byte sent to the X9250 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
Identification (ID) Byte
The first byte sent to the X9250 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9250 this is fixed as 0101[B] (refer to Figure 2).
Figure 3. Instruction Byte Format
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A -A input pins.
Register
Select
0
1
The X9250 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9250 to successfully
I3
I2
I1
I0
R1 R0
P1
P0
continue the command sequence. The A –A inputs
0
1
can be actively driven by CMOS input signals or tied to
or V
Instructions
Pot Select
V
.
SS
CC
The remaining two bits in the slave byte must be set to 0.
Characteristics subject to change without notice. 4 of 21
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X9250
The four high order bits of the instruction byte specify
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9250; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register.These instructions are:
the operation. The next two bits (R and R ) select one
1
0
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
(P1 and P ) selects which one of the four
0
potentiometers is to be affected by the instruction.
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– Write Wiper Counter Register—change current wiper
position of the selected pot,
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
– Global XFR Data Register to Wiper Counter Register—
This transfers the contents of all specified Data Reg-
isters to the associated Wiper Counter Registers.
The sequence of these operations is shown in Figure 5
and Figure 6.
– Global XFR Wiper Counter Register to Data Register—
This transfers the contents of all Wiper Counter Reg-
isters to the specified associated Data Registers.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position.The response of the wiper
(t
) while SI is HIGH, the selected wiper will move
HIGH
one resistor segment towards the V /R terminal.
H
H
Similarly, for each SCK clock pulse while SI is LOW, the
selected wiper will move one resistor segment towards
to this action will be delayed by t
. A transfer from
WRL
the WCR (current wiper position), to a Data Register is
a write to nonvolatile memory and takes a minimum of
the V /R terminal. A detailed illustration of the sequence
L
L
and timing for this operation are shown in Figure 7 and
Figure 8.
t
to complete.The transfer can occur between one of
WR
the four potentiometers and one of its associated
registers; or it may occur globally, where the transfer
occurs between all potentiometers and one associated
register.
Characteristics subject to change without notice. 5 of 21
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X9250
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
Don’t Care
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
S0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
P1
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0
0
0
P0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Characteristics subject to change without notice. 6 of 21
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X9250
Figure 8. Increment/Decrement Timing Limits
t
WRID
SCK
SI
Voltage Out
V
/R
W
W
INC/DEC CMD Issued
Table 1. Instruction Set
Instruction
Read Wiper Counter
Register
Instruction Set
I
I
I
I
R
R
P
P
Operation
Read the contents of the Wiper Counter
Register pointed to by P -P
3
2
1
0
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
P
P
1
0
1
0
Write Wiper Counter
Register
0
0
P
P
P
P
P
P
P
P
Write new value to the Wiper Counter
Register pointed to by P -P
1
1
1
1
0
0
0
0
1
0
Read Data Register
R
R
Read the contents of the Data Register
pointed to by P -P and R –R
1
1
1
0
0
0
1
0
1
0
Write Data Register
R
R
R
R
Write new value to the Data Register pointed
to by P -P and R –R
1
0
1
0
XFR Data Register to
Wiper Counter Register
Transfer the contents of the Data Register
pointed to by R –R to the Wiper Counter
1
0
Register pointed to by P -P
1
0
XFR Wiper Counter
Register to Data Register
1
0
1
1
0
0
1
0
0
0
1
0
R
R
R
R
R
R
P
P
Transfer the contents of the Wiper Counter
Register pointed to by P -P to the Register
1
1
1
0
0
0
1
0
1
0
pointed to by R –R
1
0
Global XFR Data Register
to Wiper Counter Register
0
0
Transfer the contents of the Data Registers
pointed to by R –R of all four pots to their
1
0
respective Wiper Counter Register
Global XFR Wiper Counter
Register to Data Register
0
0
Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R –R of all four pots
1
0
Increment/Decrement
Wiper Counter Register
0
0
0
1
1
0
0
1
0
0
P
P
Enable Increment/decrement of the Wiper
Counter Register pointed to by P -P
1
0
1
0
Read Status (WIP bit)
0
0
0
1
Read the status of the internal write cycle,
by checking the WIP bit.
Characteristics subject to change without notice. 7 of 21
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X9250
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register(WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by X9250 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W W W
P P P P P P P P
A A
P P
0
1
0
1
0
0
1
0
0
1
0
0
1
0
1
0
7
6 5 4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
Data Byte
(sent by Host on SI)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W W W
P P P P P P P P
A A
P P
0
1
0
1
0
0
1
0
1
0
0
0
1
0
1
0
7
6 5 4 3 2 1 0
Read Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
Data Byte
(sent by X9250 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W W W
P P P P P P P P
A A
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1 0 1 1
1
0
7
6 5 4 3 2 1 0
Write Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
Data Byte
(sent by host on SI)
opcode
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
W W W W W W W W
P P P P P P P P
7 6 5 4 3 2 1 0
A A
1 0
R
1
R
0
P
1
P
0
0 1 0 1 0 0
1 1 0 0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction DR and WCR
CS
Falling
Edge
CS
Rising
Edge
opcode
addresses
A A
1 0
R
1
R
0
P
1
P
0
0 1 0 1 0 0
1 1 0 1
Characteristics subject to change without notice. 8 of 21
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X9250
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
CS
Falling
Edge
CS
Rising
Edge
opcode
addresses
HIGH-VOLTAGE
WRITE CYCLE
A A
1 0
R
1
R
0
P
1
P
0
0 1 0 1 0 0
1 1 1 0
Increment/Decrement Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
increment/decrement
(sent by master on SI)
CS
Falling
Edge
CS
Rising
Edge
A A
1
P P
X X
0
1
0
1
0
0
0
0
1
0
I/D I/D
.
.
.
. I/D I/D
0
1 0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
A A
1
R R
1 0
0
1
0
1
0
0
0
0
0
1
0 0
0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A A
1 0
R R
0 0
1 0
0 1 0 1 0 0
1 0 0 0
Read Status
device type
identifier
device
addresses
instruction
opcode
Data Byte
(sent by X9250 on SO)
CS
CS
Falling
Edge
Rising
Edge
W
I
P
A A
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
Characteristics subject to change without notice. 9 of 21
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X9250
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias........................ –65 to +135°C
Storage temperature............................. –65 to +150°C
Voltage on SCK, SCL or any address input
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
with respect to V ................................. –1V to +7V
SS
Voltage on V+ (referenced to V ).........................10V
SS
Voltage on V- (referenced to V ) ........................ -10V
SS
(V+) – (V-)..............................................................12V
Any V /R ...............................................................V+
H
H
Any V /R .................................................................V-
L
L
Lead temperature (soldering, 10 seconds)........ 300°C
I
(10 seconds)................................................ 15mA
W
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Device
X9250
Supply Voltage (V ) Limits
CC
5V 10%
–40°C
X9250-2.7
2.7V to 5.5V
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to end resistance tolerance
Power rating
Min.
Typ.
Max.
20
Unit
%
Test Conditions
25°C, each pot
50
mW
mA
Ω
I
Wiper current
7.5
W
R
Wiper resistance
150
250
+5.5
+5.5
-4.5
-2.7
V+
Wiper current = 1mA
W
Vv+
Voltage on V+ pin
Voltage on V- pin
X9250
+4.5
+2.7
-5.5
-5.5
V-
V
X9250-2.7
X9250
Vv-
V
X9250-2.7
V
Voltage on any V /R or V /R pin
V
dBV
TERM
H
H
L
L
Noise
Resolution (4)
-120
0.6
Ref: 1kHz
%
Absolute linearity (1)
Relative linearity (2)
1
MI(3)
MI(3)
V
V
–V
w(n)(actual) w(n)(expected)
0.6
–[V
]
w(n + 1)
w(n) + MI
Temperature coefficient of R
300
ppm/°C
ppm/°C
TOTAL
Ratiometric Temperature
Coefficient
20
C /C /C
W
Potentiometer Capacitances
10/10/25
pF
See Circuit #3
H
L
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/255 or (V /R –V /R )/255, single pot
H
H
L
L
(4) Individual array resolutions.
Characteristics subject to change without notice. 10 of 21
REV 1.2 4/13/04
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X9250
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
I
V
supply current
400
µA
f = 2MHz, SO = Open,
SCK
Other Inputs = V
SS
CC1
CC
(active)
I
V
supply current
1
mA
f
= 2MHz, SO = Open,
CC2
CC
SCK
(nonvolatile write)
Other Inputs = V
SS
I
V
current (standby)
5
µA
µA
µA
V
SCK = SI = V , Addr. = V
SS SS
SB
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
10
10
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
+ 0.1
CC
IH
CC
V
–0.5
V
x 0.3
V
IL
CC
V
0.4
V
I
= 3mA
OL
OL
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
Years
CAPACITANCE
Symbol
Test
Max.
Unit
pF
Test Conditions
= 0V
(5)
C
Output capacitance (SO)
8
6
V
OUT
OUT
(5)
C
Input capacitance (A0, A1, SI, and SCK, CS)
pF
V
= 0V
IN
IN
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
Unit
ms
(6)
t
Power-up to initiation of read operation
Power-up to initiation of write operation
1
5
PUR
(6)
t
ms
PUW
(7)
t V
V power up ramp rate
CC
0.2
50
V/msec
R
CC
POWER UP AND DOWN REQUIREMENT
The are no restrictions on the sequencing of the bias supplies V , V+, and V- provided that all three supplies reach
CC
their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than
V+ and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach
their final value.The V ramp rate spec is always in effect.
CC
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) t
and t
are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the specific instruction can
PUR
PUW CC
be issued.These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
A.C. TEST CONDITIONS
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
Input rise and fall times
Input and output timing level
10ns
V
x 0.5
CC
Characteristics subject to change without notice. 11 of 21
REV 1.2 4/13/04
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X9250
Circuit #3 SPICE Macro Model
EQUIVALENT A.C. LOAD CIRCUIT
5V
2.7V
R
TOTAL
R
R
L
1533Ω
H
C
L
C
H
C
W
10pF
SDA Output
10pF
25pF
100pF
100pF
R
W
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
f
SSI/SPI clock frequency
SSI/SPI clock cycle time
SSI/SPI clock high time
SSI/SPI clock low time
Lead time
2.0
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
SCK
CYC
t
500
200
200
250
250
50
t
WH
t
WL
t
LEAD
t
Lag time
LAG
t
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable Time
SU
t
75
H
t
2
RI
t
2
FI
t
0
0
500
100
DIS
t
SO output valid time
V
t
SO output hold time
HO
t
SO output rise time
50
50
RO
t
SO output fall time
FO
t
HOLD time
400
100
100
HOLD
t
HOLD setup time
HSU
t
HOLD hold time
HH
t
HOLD low to output in high Z
HOLD high to output in low Z
Noise suppression time constant at SI, SCK, HOLD and CS inputs
CS deselect time
100
100
TBD
HZ
t
LZ
T
I
t
2
0
0
CS
t
WP, A0 and A1 setup time
WP, A0 and A1 hold time
WPASU
t
WPAH
Characteristics subject to change without notice. 12 of 21
REV 1.2 4/13/04
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X9250
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Unit
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Unit
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
10
10
40
µs
µs
µs
WRPO
t
WRL
t
Wiper response time from an active SCL/SCK edge (increment/decrement instruc-
tion)
WRID
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
Characteristics subject to change without notice. 13 of 21
REV 1.2 4/13/04
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X9250
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
Hold Timing
CS
t
t
HH
HSU
SCK
SO
...
t
t
FO
RO
t
t
LZ
HZ
SI
t
HOLD
HOLD
XDCP Timing (for all Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
VWx
High Impedance
SO
Characteristics subject to change without notice. 14 of 21
REV 1.2 4/13/04
www.xicor.com
X9250
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
VWx
...
t
WRID
...
...
ADDR
Inc/Dec
SI
Inc/Dec
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
Characteristics subject to change without notice. 15 of 21
REV 1.2 4/13/04
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X9250
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
V
/R
W
W
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
O
2
1
S
O
2
1
adj
2
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
V
S
O
100KΩ
–
+
V
O
TL072
R
R
1
2
10KΩ
10KΩ
+12V
V
V
= {R /(R +R ) V (max)
1 1 2 O
UL
LL
10KΩ
-12V
= {R /(R +R ) V (min)
1
1
2
O
Characteristics subject to change without notice. 16 of 21
REV 1.2 4/13/04
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X9250
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
R
2
O
1
3
–
+
R
V
O
V
S
R
2
R
4
R = R = R = R = 10kΩ
1
2
3
4
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
3
Z
IN
V
= G V
S
O
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
C
R
R
1
2
–
+
–
+
R
}
}
A
B
R
frequency ∝ R , R , C
1
2
amplitude ∝ R , R
A
B
Characteristics subject to change without notice. 17 of 21
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X9250
PACKAGING INFORMATION
24-Bump Chip Scale Package (CSP B24)
Package Outline Drawing
a
d
f
A4
B4
C4
D4
E4
F4
A3
A2 A1
B2 B1
C2 C1
D2 D1
E2 E1
B3
C3
D3
E3
F3
j
b
F2 F1
k
m
e
l
Top View (Sample Marking)
Bottom View (Bumped Side)
Side View
e
c
Side View
Package Dimensions
Ball Matrix:
Millimeters
4
3
2
1
Symbol
Min
Nominal
2.801
4.579
0.677
0.457
0.240
0.330
0.5
Max
R
R
R
W0
A
B
C
D
E
F
A1
SI
CS
WP
L1
Package Width
a
b
c
d
e
f
2.771
4.549
0.644
0.444
0.220
0.310
2.831
4.609
0.710
0.470
0.260
0.350
R
W1
L0
Package Length
R
R
VSS
VCC
V+
H1
H0
Package Height
R
V-
RH2
HOLD
SCK
H3
Body Thickness
R
R
SO
A0
W2
L3
Ball Height
R
R
L2
W3
Ball Diameter
Ball Pitch – Width
Ball Pitch – Length
Ball to Edge Spacing – Width
Ball to Edge Spacing – Length
j
k
l
0.5
0.626
1.015
0.651
1.040
0.676
1.065
m
Characteristics subject to change without notice. 18 of 21
REV 1.2 4/13/04
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X9250
PACKAGING INFORMATION
24-Lead Plastic, TSSOP, Package Code V24
.026 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
(7.72)
(4.16)
0°–8°
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
(0.42)
Detail A (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 19 of 21
REV 1.2 4/13/04
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X9250
PACKAGING INFORMATION
24-Lead Plastic, SOIC, Package Code S24
0.393 (10.00)
0.420 (10.65)
0.290 (7.37)
0.299 (7.60)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" Typical
24 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 20 of 21
REV 1.2 4/13/04
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X9250
Ordering Information
X9250
Y
P
T
V
V
Limits
CC
Device
Blank = 5V 10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial =0°C to +70°C
I = Industrial = –40°C to +85°C
Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
B24 = 24-Lead CSP
Potentiometer Organization
T = 100KΩ
U= 50KΩ
S & V Package Marking
Line #1
Line #2
Line #3
Line #4
(Blank)
(Part Number)
(Date Code) (*)
(Blank)
= F 2.7V 0 to 70°C
G 2.7V -40 to +85°C
I
5V
-40 to +85°C
LIMITED WARRANTY
©Xicor, Inc. 2003 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS ANDTRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 21 of 21
REV 1.2 4/13/04
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