X9251TS24-2.7T1 [XICOR]
Digital Potentiometer, 4 Func, 100000ohm, 3-wire Serial Control Interface, 256 Positions, CMOS, PDSO24, PLASTIC, SOIC-24;
| 型号： | X9251TS24-2.7T1 |
| 厂家： | 
XICOR INC. |
| 描述： | Digital Potentiometer, 4 Func, 100000ohm, 3-wire Serial Control Interface, 256 Positions, CMOS, PDSO24, PLASTIC, SOIC-24 光电二极管 |
| 文件： | 总25页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTES AND DEVELOPMENT SYSTEM
A V A I L A B L E
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
Single Supply / Low Power / 256-tap / SPI bus
X9251
Quad Digitally-Controlled (XDCPTM) Potentiometer
FEATURES
DESCRIPTION
• Four potentiometers in one package
• 256 resistor taps–0.4% resolution
• SPI Serial Interface for write, read, and transfer
operations of the potentiometer
The X9251 integrates four digitally controlled potentio-
meters (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are imple-
mented with a combination of resistor elements and
CMOS switches. The position of the wipers are
controlled by the user through the SPI bus interface.
Each potentiometer has associated with it a volatile
Wiper Counter Register (WCR) and four non-volatile
Data Registers that can be directly written to and read
by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls
the content of the default Data Registers of each DCP
(DR00, DR10, DR20, and DR30) to the corresponding
WCR.
• Wiper resistance: 100Ω typical @ V
= 5V
CC
• 4 Non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper positions
• Standby current < 5µA max
• V : 2.7V to 5.5V Operation
CC
• 50KΩ, 100KΩ versions of total resistance
• 100 yr. data retention
• Single supply version of X9250
• Endurance: 100,000 data changes per bit per
register
• 24-lead SOIC, 24-lead TSSOP, 24-lead CSP
(Chip Scale Package)
The XDCP can be used as
a three-terminal
• Low power CMOS
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
R
R
H3
R
R
V
H1
H2
H0
CC
HOLD
DCP1
DCP3
DCP2
DCP0
WCR1
DR10
DR11
DR12
DR13
WCR3
DR30
DR31
DR32
DR33
WCR2
DR20
DR21
DR22
DR23
WCR0
DR00
DR01
DR02
DR03
A1
A0
SO
SI
SPI
Interface
POWER UP,
INTERFACE
CONTROL
AND
STATUS
SCK
CS
V
R
R
L3
R
R
SS
R
R
R
W3
WP
R
W0
L1
L2
L0
W1
W2
Characteristics subject to change without notice. 1 of 25
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X9251
ORDERING INFO
Operating
Temperature
Range
Ordering
Number
Potentiomenter
Organization
V
CC
Limits
Package
X9251US24
X9251US24-2.7
X9251US24I
50kΩ
50kΩ
24-lead SOIC
24-lead SOIC
24-lead SOIC
24-lead SOIC
24-lead TSSOP
24-lead TSSOP
24-lead TSSOP
24-lead TSSOP
24-lead CSP
24-lead CSP
24-lead CSP
24-lead CSP
24-lead SOIC
24-lead SOIC
24-lead SOIC
24-lead SOIC
24-lead TSSOP
24-lead TSSOP
24-lead TSSOP
24-lead TSSOP
24-lead CSP
24-lead CSP
24-lead CSP
24-lead CSP
0°C to 70°C
0°C to 70°C
5V 10ꢀ
2.7 to 5.5V
5V 10ꢀ
50kΩ
-40°C to +85°C
-40°C to +85°C
0°C to 70°C
X9251US24I-2.7
X9251UV24
50kΩ
2.7 to 5.5V
5V 10ꢀ
50kΩ
X9251UV24-2.7
X9251UV24I
50kΩ
0°C to 70°C
2.7 to 5.5V
5V 10ꢀ
50kΩ
-40°C to +85°C
-40°C to +85°C
0°C to 70°C
X9251UV24I-2.7
X9251UB24
50kΩ
2.7 to 5.5V
5V 10ꢀ
50kΩ
X9251UB24-2.7
X9251UB24I
50kΩ
0°C to 70°C
2.7 to 5.5V
5V 10ꢀ
50kΩ
-40°C to +85°C
-40°C to +85°C
0°C to 70°C
X9251UB24I-2.7
X9251TS24
50kΩ
2.7 to 5.5V
5V 10ꢀ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
X9251TS24-2.7
X9251TS24I
0°C to 70°C
2.7 to 5.5V
5V 10ꢀ
-40°C to +85°C
-40°C to +85°C
0°C to 70°C
X9251TS24I-2.7
X9251TV24
2.7 to 5.5V
5V 10ꢀ
X9251TV24-2.7
X9251TV24I
0°C to 70°C
2.7 to 5.5V
5V 10ꢀ
-40°C to +85°C
-40°C to +85°C
0°C to 70°C
X9251TV24I-2.7
X9251TB24
2.7 to 5.5V
5V 10ꢀ
X9251TB24-2.7
X9251TB24I
0°C to 70°C
2.7 to 5.5V
5V 10ꢀ
-40°C to +85°C
-40°C to +85°C
X9251TB24I-2.7
2.7 to 5.5V
Characteristics subject to change without notice. 2 of 25
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X9251
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable dc reference voltages for
comparators and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Trim out the offset voltage error in a voltage amplifier
circuit
• Control the gain in audio and home entertainment
systems
• Set the output voltage of a voltage regulator
• Provide the variable DC bias for tuners in RF wireless
systems
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the operating points in temperature control
systems
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Control the operating point for sensors in industrial
systems
• Vary the frequency and duty cycle of timer ICs
• Trim offset and gain errors in artificial intelligent
systems
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
Characteristics subject to change without notice. 3 of 25
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X9251
PIN CONFIGURATION
CSP
1
2
3
4
SOIC/TSSOP
HOLD
SCK
A
SO
A0
R
CS
R
R
1
2
24
23
22
21
20
19
18
17
16
1
W0
L0
L1
A
B
R
WP
SI
R
R
W3
W1
3
L2
R
R
H3
4
H2
V
R
R
V
SS
R
R
5
CC
H0
H1
H2
L3
W2
C
D
NC
NC
6
X9251
R
V
R
V
7
NC
NC
CC
H3
SS
R
R
8
W1
L0
R
R
H0
9
R
R
HOLD
SCK
R
W2
SO
H1
L3
E
F
R
R
W0
10
11
12
15
14
L1
A1
SI
CS
A
0
R
L2
W3
WP
13
Top View–Bumps Down
PIN ASSIGNMENTS
Pin
Pin
(SOIC)
(CSP)
Symbol
SO
Function
1
2
E2
Serial Data Output for SPI bus
Device Address for SPI bus. (See Note 1)
Wiper Terminal of DCP3
High Terminal of DCP3
F2
A0
3
F1
R
W3
4
D2
E1
R
H3
5
R
Low Terminal of DCP3
L3
7
C1
B1
V
System Supply Voltage
CC
8
R
Low Terminal of DCP0
L0
H0
W0
9
C2
A1
R
High Terminal of DCP0
10
11
12
13
14
15
16
17
18
20
21
22
23
24
6, 19
R
Wiper Terminal of DCP0
SPI bus. Chip Select active low input
Hardware Write Protect – active low
Serial Data Input for SPI bus
Device Address for SPI bus. (See Note 1)
Low Terminal of DCP1
A2
CS
WP
SI
B2
B3
A3
A1
A4
R
L1
H1
W1
C3
B4
R
High Terminal of DCP1
R
Wiper Terminal of DCP1
System Ground
C4
E4
V
SS
R
Wiper Terminal of DCP2
High Terminal of DCP2
W2
D3
F4
R
H2
R
Low Terminal of DCP2
L2
F3
SCK
HOLD
NC
Serial Clock for SPI bus
E3
Device select. Pauses the SPI serial bus.
No Connect
D1, D4
Note 1: A0–A1 device address pins must be tied to a logic level.
Characteristics subject to change without notice. 4 of 25
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X9251
PIN DESCRIPTIONS
Bus Interface Pins
SERIAL OUTPUT (SO)
Potentiometer Pins
R , R
H
L
The R and R pins are equivalent to the terminal
H
L
connections on a mechanical potentiometer. Since
there are 4 potentiometers, there are 4 sets of R and
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
H
R such that R and R are the terminals of DCP0
L
H0
L0
and so on.
SERIAL INPUT (SI)
R
W
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the device
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are
4
potentiometers, there are 4 sets of R such that R
W
W0
is the terminals of DCP0 and so on.
SERIAL CLOCK (SCK)
Supply Pins
The SCK input is used to clock data into and out of the
X9251.
SYSTEM SUPPLY VOLTAGE (V
) AND SUPPLY GROUND (V )
SS
CC
The V pin is the system supply voltage. The V pin
CC
SS
HOLD (HOLD)
is the system ground.
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Other Pins
NO CONNECT
No connect pins should be left floating. This pins are
used for Xicor manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents non-volatile writes to
the Data Registers.
DEVICE ADDRESS (A1–A0)
The address inputs are used to set the two least
significant bits of the slave address. A match in the
slave address serial data stream must be made with
the address input in order to initiate communication
with the X9251. Device pins A1-A0 must be tie to a
logic level which specify the internal address of the
device, see Figures 2, 3, 4, 5 and 6.
CHIP SELECT (CS)
When CS is HIGH, the X9251 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device is in the standby
state. CS LOW enables the X9251, placing it in the
active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Characteristics subject to change without notice. 5 of 25
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X9251
PRINCIPLES OF OPERATION
The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).
The X9251 is an integrated circuit incorporating four
DCPs and their associated registers and counters, and
a serial interface providing direct communication
between a host and the potentiometers.
Power Up and Down Recommendations.
There are no restrictions on the power-up or power-
down conditions of V and the voltages applied to the
CC
DCP Description
potentiometer pins provided that V
is always more
CC
Each DCP is implemented with a combination of
resistor elements and CMOS switches. The physical
ends of each DCP are equivalent to the fixed terminals
positive than or equal to V , V , and V , i.e., V ≥ V ,
H
L
W
CC
H
V , V . The V
ramp rate specification is always in
L
W
CC
effect.
of a mechanical potentiometer (R and R pins). The
H
L
RW pin is an intermediate node, equivalent to the
wiper terminal of a mechanical potentiometer.
Figure 1. Detailed Potentiometer Block Diagram
One of Four Potentiometers
R
H
#: 0, 1, 2, or 3
SERIAL
BUS
INPUT
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
DR#1
8
8
PARALLEL
BUS
INPUT
COUNTER
- - -
DECODE
DCP
CORE
R
W
WIPER
DR#2
DR#3
COUNTER
REGISTER
(WCR#)
INC/DEC
LOGIC
IF WCR = 00[H] then R is closet to R
W
L
UP/DN
IF WCR = FF[H] then R is closet to R
UP/DN
CLK
W
H
MODIFIED SCK
R
L
Characteristics subject to change without notice. 6 of 25
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X9251
Wiper Counter Register (WCR)
Data Registers (DR)
The X9251 contains four Wiper Counter Registers, one
for each potentiometer. The Wiper Counter Register
can be envisioned as a 8-bit parallel and serial load
counter with its outputs decoded to select one of 256
wiper positions along its resistor array. The contents of
the WCR can be altered in four ways: it may be written
directly by the host via the Write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step
at a time by the Increment/Decrement instruction (see
Instruction section for more details). Finally, it is loaded
with the contents of its Data Register zero (DR#0)
upon power-up. (See Figure 1.)
Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a non-volatile operation and takes a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper
positions or data (0~255).
Status Register (SR)
This 1-bit Status Register is used to store the system
status.
The wiper counter register is a volatile register; that is,
its contents are lost when the X9251 is powered-down.
Although the register is automatically loaded with the
value in DR#0 upon power-up, this may be different
from the value present at power-down. Power-up
guidelines are recommended to ensure proper
loadings of the DR#0 value into the WCR#.
WIP:Write In Progress status bit, read only.
– When WIP=1, indicates that high-voltage write cycle
is in progress.
– When WIP=0, indicates that no high-voltage write
cycle is in progress.
Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile).
WCR7
(MSB)
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
(LSB)
Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Non-volatile).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(MSB)
(LSB)
Characteristics subject to change without notice. 7 of 25
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X9251
SERIAL INTERFACE
The least significant four bits of the Identification Byte
are the Slave Address bits, AD[3:0]. For the X9251, A3
is 0, A2 is 0, A1 is the logic value at the input pin A1,
and A0 is the logic value at the input pin A0. Only the
device which Slave Address matches the incoming
bits sent by the master executes the instruction. The
A1 and A0 inputs can be actively driven by CMOS
The X9251 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in, on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
input signals or tied to V
or V
.
CC
SS
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
INSTRUCTION BYTE
The next byte sent to the X9251 contains the
instruction and register pointer information. The four
most significant bits are used provide the instruction
opcode (I[3:0]). The RB and RA bits point to one of the
four Data Registers of each associated XDCP. The
least two significant bits point to one of four Wiper
Counter Registers or DCPs.The format is shown below
in Table 4.
IDENTIFICATION BYTE
The first byte sent to the X9251 from the host, following
a CS going HIGH to LOW, is called the Identification
Byte. The most significant four bits of the Identification
Byte are a Device Type Identifier, ID[3:0]. For the
X9251, this is fixed as 0101 (refer to Table 3).
Table 3. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
1
A3
0
A2
0
A1
A0
Pin A1
Pin A0
Logic Value Logic Value
(MSB)
(LSB)
Table 4. Instruction Byte Format
Register
Selection
Instruction
Opcode
DCP Selection
(WCR Selection)
I3
I2
I1
I0
RB
RA
P1
P0
(MSB)
(LSB)
Data Register Selection
Register
DR#0
RB
0
RA
0
DR#1
0
1
DR#2
1
0
DR#3
1
1
#: 0, 1, 2, or 3
Characteristics subject to change without notice. 8 of 25
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X9251
Table 5. Instruction Set
Instruction Set
Instruction
I3 I2 I1 I0 RB RA P1 P0
Operation
Read Wiper Counter
Register
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
1/0 1/0 Read the contents of the Wiper Counter
Register pointed to by P1-P0
Write Wiper Counter
Register
0
0
1/0 1/0 Write new value to the Wiper Counter
Register pointed to by P1-P0
Read Data Register
1/0 1/0 1/0 1/0 Read the contents of the Data Register
pointed to by P1-P0 and RB-RA
Write Data Register
1/0 1/0 1/0 1/0 Write new value to the Data Register
pointed to by P1-P0 and RB-RA
XFR Data Register to
Wiper Counter Register
1/0 1/0 1/0 1/0 Transfer the contents of the Data Register
pointed to by P1-P0 and RB-RA to its
associated Wiper Counter Register
XFR Wiper Counter
Register to Data Register
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter
Register pointed to by P1-P0 to the Data
Register pointed to by RB-RA
Global XFR Data Registers
to Wiper Counter Registers
1/0 1/0
1/0 1/0
0
0
0
0
Transfer the contents of the Data Registers
pointed to by RB-RA of all four pots to their
respective Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register
Transfer the contents of both Wiper Counter
Registers to their respective data Registers
pointed to by RB-RA of all four pots
Increment/Decrement
Wiper Counter Register
0
0
1/0 1/0 Enable Increment/decrement of the Control
Latch pointed to by P1-P0
Note: 1/0 = data is one or zero
Characteristics subject to change without notice. 9 of 25
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X9251
Instructions
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
Four of the nine instructions are three bytes in length.
These instructions are:
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Read Wiper Counter Register – read the current
wiper position of the selected potentiometer,
– Write Wiper Counter Register – change current
wiper position of the selected potentiometer,
– Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified
Data Registers to the associated Wiper Counter
Registers.
– Read Data Register – read the contents of the
selected Data Register,
– Write Data Register – write a new value to the
selected Data Register,
– Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
– Read Status – this command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (see
Figures 6 and 7). The Increment/Decrement command
is different from the other commands. Once the
command is issued and the X9251 has responded with
an Acknowledge, the master can clock the selected
wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each
wiper to this action is delayed by t
. A transfer from
WRL
the WCR (current wiper position), to a Data Register is
a write to non-volatile memory and takes a minimum of
t
to complete. The transfer can occur between one
SCK clock pulse (t
) while SI is HIGH, the selected
WR
HIGH
of the four potentiometer’s WCR, and one of its
associated registers, DRs; or it may occur globally,
where the transfer occurs between all potentiometers
and one associated register. The Read Status Register
instruction is the only unique format (see Figure 5).
wiper moves one wiper position towards the R
terminal. Similarly, for each SCK clock pulse while SI is
LOW, the selected wiper moves one wiper position
H
towards the R terminal. A detailed illustration of the
L
sequence and timing for this operation are shown. See
Instruction format for more details.
Four instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9251; either between the host and one
of the data registers or directly between the host and
the Wiper Counter Register.These instructions are:
Characteristics subject to change without notice. 10 of 25
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X9251
Figure 2. Two-Byte Instruction Sequence
CS
SCK
SI
0
0
0
0
0
1
0
1
A1 A0
ID3 ID2 ID1 ID0
Device ID
RB RA
P0
I3
I2
I1 I0
P1
Register
Address
Instruction
Opcode
DCP/WCR
Address
Internal
Address
Figure 3. Three-Byte Instruction Sequence SPI Interface; Write Case
CS
SCK
SI
0
0
0
0
0
1
0
1
ID3 ID2 ID1 ID0
P1
P0
A1 A0
RB RA
I3 I2
I0
D7 D6 D5 D4 D3 D2 D1 D0
Data for WCR[7:0] or DR[7:0]
I1
Internal
Address
Instruction
Opcode
Register
Address
DCP/WCR
Address
Device ID
Figure 4. Three-Byte Instruction Sequence SPI Interface, Read Case
CS
SCK
SI
0
0
0
0
0
1
0
1
X
X
X
X
X
X
X
X
ID3 ID2 ID1 ID0
Device ID
A1 A0
I2 I1
RB RA P1 P0
I3
I0
Don’t Care
Internal
Address
DCP/WCR
Instruction
Opcode
Register
Address
Address
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
or
Data Register Bit [7:0]
Characteristics subject to change without notice. 11 of 25
REV 1.4 4/13/04
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X9251
Figure 5. Three-Byte Instruction Sequence (Read Status Register)
CS
SCK
SI
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
0
ID3 ID2 ID1 ID0
I3
A1 A0
I2 I1 I0 RB RA
P1 P0
WIP
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Status
Bit
Device ID
Figure 6. Increment/Decrement Instruction Sequence
CS
SCK
SI
0
0
0
0
0
1
0
1
ID3 ID2 ID1 ID0
Device ID
I2 I3
I0
P1
RB RA P0
A1 A0
I1
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Internal
Address
Instruction
Opcode
Pot/WCR
Address
Register
Address
Figure 7. Increment/Decrement Timing Spec
t
WRID
SCK
SI
VOLTAGE OUT
R
W
INC/DEC CMD ISSUED
Characteristics subject to change without notice. 12 of 25
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X9251
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Wiper Position
(Sent by X9251 on SO)
CS
Falling
Edge
CS
Rising
Edge
W
C
R
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0
0 A1 A0 1
0
0
1
0
0
0
0
5
4
3
2
1
0
6
Write Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Data Byte
(Sent by Host on SI)
CS
Falling
Edge
CS
Rising
Edge
W
C
R
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0
0 A1 A0 1
0
1
0
0
0
0
0
5
4 3 2 1 0
6
Read Data Register (DR)
Device Type
CS
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by X9271 on SO)
CS
Rising
Edge
Identifier
Falling
Edge
D
D D D D D D D
0
1
0
1
0
0 A1 A0 1
0
1
1 RB RA P1 P0
6
5 4 3 2 1 0
7
Write Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by Host on SI)
CS
CS
Falling
Edge
Rising
Edge
D
7
D D D D D D D
6 5 4 3 2 1 0
0
1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR
Addresses
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0 A1 A0 0 0 0 1 RB RA 0 0
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Characteristics subject to change without notice. 13 of 25
REV 1.4 4/13/04
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X9251
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR
Addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1 0 0 A1 A0 1 0 0 0 RB RA 0 0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction DR and WCR
Opcode Addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
0 0 A1 A0 1 1 1 0 RB RA
0
0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0 0 A1 A0 1 1 0 1 RB RA
0
0
Increment/Decrement Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
X X
Increment/Decrement
(Sent by Master on SI)
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0 A1 A0 0
0
1
0
0
0
I/D I/D
.
.
.
. I/D I/D
Read Status Register (SR)
Device Type
Identifier
Device
Addresses
0 A1 A0 0
Instruction
Opcode
WCR
Addresses
Data Byte
(Sent by X9251 on SO)
WIP
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Characteristics subject to change without notice. 14 of 25
REV 1.4 4/13/04
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X9251
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ....................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Voltage on SCK, any address input, V
CC
with respect to V ..................................–1V to +7V
SS
∆V = | (V –VL) | ................................................... 5.5V
H
Lead temperature (soldering, 10 seconds).........300°C
I
(10 seconds) ................................................. 6mA
W
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
0°C
Max.
+70°C
+85°C
Device
X9251
Supply Voltage (V
)
(4) Limits
CC
Commercial
Industrial
5V 10ꢀ
–40°C
X9251-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.)
Parameter
Limits
Symbol
Min.
Typ.
Max. Units
Test Conditions
T version
R
End to End Resistance
End to End Resistance
End to End Resistance Tolerance
Power Rating
100
50
kΩ
kΩ
TOTAL
R
U version
TOTAL
20
50
ꢀ
mW
mA
Ω
25°C, each pot
I
Wiper Current
3
W
R
Wiper Resistance
300
V(V
)
W
CC
I
I
=
@ V
@ V
= 3V
= 5V
W
CC
R
TOTAL
150
Ω
V(V
)
CC
TOTAL
=
W
CC
R
V
Voltage on any R or R Pin
V
V
V
V
= 0V
TERM
H
L
SS
CC
SS
Noise
-120
0.4
dBV/ Hz Ref: 1V
Resolution
ꢀ
(5)
Absolute Linearity (1)
-1
+1
+0.6
MI(3)
R
– R
w(n)(actual) w(n)(expected)
Relative Linearity (2)
-0.6
MI(3)
R
– [R
]
(5)
w(n + 1)
w(n) + MI
Temperature Coefficient of R
300
ppm/°C
TOTAL
Ratiometric Temp. Coefficient
Potentiometer Capacitances
-20
+20 ppm/°C
pF See Macro model
C /C /C
W
10/10/25
H
L
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (R – R ) / 255, single pot
H
L
(4) During power up V > V , V , and V .
CC
H
L
W
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254.
Characteristics subject to change without notice. 15 of 25
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X9251
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
= 2.5 MHz, SO = Open, V =6V
I
I
I
V
supply current
(active)
400
µA
f
SCK
CC1
CC2
SB
CC
CC
Other Inputs = V
SS
V
supply current
(non-volatile write)
1
5
3
mA
f
= 2.5MHz, SO = Open, V =6V
SCK CC
CC
Other Inputs = V
SS
V
current (standby)
µA
SCK = SI = V , Addr. = V
,
CC
SS
SS
CS = V
= 6V
CC
I
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V
CC
LO
OUT
SS
V
V
V
V
V
V
x 0.7
V
+ 1
CC
IH
CC
–1
V
x 0.3
V
IL
CC
Output LOW voltage
Output HIGH voltage
Output HIGH voltage
0.4
V
I
I
I
= 3mA
OL
OH
OH
OL
OH
OH
V
V
- 0.8
V
= -1mA, V ≥ +3V
CC
CC
- 0.4
V
= -0.4mA, V ≤ +3V
CC
CC
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
Units
100,000
100
Data changes per bit per register
years
CAPACITANCE
Symbol
Test
Max.
Units
pF
Test Conditions
(6)
C
Input / Output capacitance (SI)
Output capacitance (SO)
8
8
6
V
V
V
= 0V
= 0V
IN/OUT
OUT
OUT
(6)
C
C
pF
OUT
(6)
Input capacitance (A0, A1, CS, WP, HOLD, and SCK)
pF
= 0V
IN
IN
POWER-UP TIMING
Symbol
Parameter
V Power-up rate
CC
Min.
Max.
50
Units
(6)
t V
0.2
V/ms
ms
r
CC
(7)
t
t
Power-up to initiation of read operation
Power-up to initiation of write operation
1
PUR
(7)
50
ms
PUW
A.C. TEST CONDITIONS
Input Pulse Levels
Input rise and fall times
Input and output timing level
V
x 0.1 to V x 0.9
CC
CC
10ns
V
x 0.5
CC
Notes: (6) This parameter is not 100ꢀ tested
(7) t and t are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be
PUR
PUW
CC
issued.These parameters are periodically sampled and not 100ꢀ tested.
Characteristics subject to change without notice. 16 of 25
REV 1.4 4/13/04
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X9251
EQUIVALENT A.C. LOAD CIRCUIT
V
CC
SPICE Macromodel
2kΩ
R
TOTAL
R
R
L
H
SO pin
C
C
W
C
L
L
10pF
2kΩ
10pF
25pF
10pF
R
W
AC TIMING
Symbol
Parameter
Min.
Max.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SPI clock frequency
SPI clock cycle rime
SPI clock high rime
SPI clock low time
Lead time
2
SCK
CYC
WH
WL
LEAD
LAG
SU
500
200
200
250
250
50
Lag time
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
50
H
2
RI
2
FI
0
0
250
200
DIS
V
SO output valid time
SO output hold time
HO
RO
FO
SO output rise time
100
100
SO output fall time
HOLD time
400
100
100
HOLD
HSU
HH
HZ
HOLD setup time
HOLD hold time
HOLD low to output in high Z
HOLD high to output in low Z
100
100
10
LZ
T
Noise suppression time constant at SI, SCK, HOLD and CS inputs
I
t
t
t
CS deselect time
WP, A0 setup time
WP, A0 hold time
2
0
0
CS
WPASU
WPAH
Characteristics subject to change without notice. 17 of 25
REV 1.4 4/13/04
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X9251
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Units
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Units
t
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
5
5
10
10
µs
µs
WRPO
WRL
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
.
Characteristics subject to change without notice. 18 of 25
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X9251
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
Hold Timing
CS
t
t
HH
HSU
SCK
...
t
t
FO
RO
SO
t
t
LZ
HZ
SI
t
HOLD
HOLD
Characteristics subject to change without notice. 19 of 25
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X9251
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
LSB
MSB
SI
VWx
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
Characteristics subject to change without notice. 20 of 25
REV 1.4 4/13/04
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X9251
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
O
2
1
S
O
2
1
adj 2
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
V
S
O
100KΩ
–
+
V
O
TL072
R
R
1
2
10KΩ
10KΩ
+12V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
10KΩ
-12V
RL = {R /(R +R )} V (min)
L
1
1
2
O
Characteristics subject to change without notice. 21 of 25
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X9251
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
R
2
O
1
3
–
+
R
V
O
V
S
R
2
R
4
R = R = R = R = 10kΩ
1
2
3
4
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
3
Z
IN
V
= G V
S
O
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
A
}
B
frequency ∝ R , R , C
1
2
amplitude ∝ R , R
A
B
Characteristics subject to change without notice. 22 of 25
REV 1.4 4/13/04
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X9251
PACKAGING INFORMATION
24-Bump Chip Scale Package (CSP B24)
Package Outline Drawing
a
d
A4
A4
A4
A3
A3
A3
A2 A1
A2 A1
A2 A1
b
k
A4
A4
A4
A3
A3
A3
A2 A1
A2 A1
A2 A1
f
m
e
l
j
Bottom View (Bumped Side)
Top View (Marking Side)
Side View
e
e
Side View
Ball Matrix
4
3
2
1
R
R
W0
A
B
C
D
E
F
A1
SI
CS
WP
L1
R
R
W1
L0
R
R
VSS
VCC
NC
H1
H2
H0
R
R
NC
H3
R
R
HOLD SO
SCK A0
W2
L3
R
R
L2
W3
Millimeters
Nom.
2.785
4.537
0.677
0.457
0.240
0.330
0.5
Inches
Nom.
Symbol
Min
Max
2.815
4.567
0.710
0.470
0.260
0.350
Min
Max
Package Width
A
B
C
D
E
F
J
2.755
4.507
0.644
0.444
0.220
0.310
Package Length
Package Height
Body Thickness
Ball Height
Ball Diameter
Ball Pitch – Width
Ball Pitch – Length
Ball to Edge Spacing – Width
Ball to Edge Spacing – Length
K
L
0.5
0.618
1.056
0.643
1.081
0.668
1.106
M
Characteristics subject to change without notice. 23 of 25
REV 1.4 4/13/04
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X9251
PACKAGING INFORMATION
24-Lead Plastic, TSSOP, Package Code V24
.026 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
(7.72)
(4.16)
0°–8°
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
(0.42)
Detail A (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 24 of 25
REV 1.4 4/13/04
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X9251
PACKAGING INFORMATION
24-Lead Plastic, SOIC, Package Code S24
0.393 (10.00)
0.290 (7.37)
0.299 (7.60)
0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" Typical
24 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
©Xicor, Inc. 2004 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 25 of 25
REV 1.4 4/13/04
www.xicor.com
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